Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
0004  *      http://www.samsung.com
0005  *
0006  * PATA driver for Samsung SoCs.
0007  * Supports CF Interface in True IDE mode. Currently only PIO mode has been
0008  * implemented; UDMA support has to be added.
0009  *
0010  * Based on:
0011  *  PATA driver for AT91SAM9260 Static Memory Controller
0012  *  PATA driver for Toshiba SCC controller
0013 */
0014 
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/mod_devicetable.h>
0018 #include <linux/init.h>
0019 #include <linux/clk.h>
0020 #include <linux/libata.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/slab.h>
0023 
0024 #include <linux/platform_data/ata-samsung_cf.h>
0025 
0026 #define DRV_NAME "pata_samsung_cf"
0027 #define DRV_VERSION "0.1"
0028 
0029 #define S3C_CFATA_REG(x)    (x)
0030 #define S3C_CFATA_MUX       S3C_CFATA_REG(0x0)
0031 #define S3C_ATA_CTRL        S3C_CFATA_REG(0x0)
0032 #define S3C_ATA_CMD     S3C_CFATA_REG(0x8)
0033 #define S3C_ATA_IRQ     S3C_CFATA_REG(0x10)
0034 #define S3C_ATA_IRQ_MSK     S3C_CFATA_REG(0x14)
0035 #define S3C_ATA_CFG     S3C_CFATA_REG(0x18)
0036 
0037 #define S3C_ATA_PIO_TIME    S3C_CFATA_REG(0x2c)
0038 #define S3C_ATA_PIO_DTR     S3C_CFATA_REG(0x54)
0039 #define S3C_ATA_PIO_FED     S3C_CFATA_REG(0x58)
0040 #define S3C_ATA_PIO_SCR     S3C_CFATA_REG(0x5c)
0041 #define S3C_ATA_PIO_LLR     S3C_CFATA_REG(0x60)
0042 #define S3C_ATA_PIO_LMR     S3C_CFATA_REG(0x64)
0043 #define S3C_ATA_PIO_LHR     S3C_CFATA_REG(0x68)
0044 #define S3C_ATA_PIO_DVR     S3C_CFATA_REG(0x6c)
0045 #define S3C_ATA_PIO_CSD     S3C_CFATA_REG(0x70)
0046 #define S3C_ATA_PIO_DAD     S3C_CFATA_REG(0x74)
0047 #define S3C_ATA_PIO_RDATA   S3C_CFATA_REG(0x7c)
0048 
0049 #define S3C_CFATA_MUX_TRUEIDE   0x01
0050 #define S3C_ATA_CFG_SWAP    0x40
0051 #define S3C_ATA_CFG_IORDYEN 0x02
0052 
0053 enum s3c_cpu_type {
0054     TYPE_S3C64XX,
0055     TYPE_S5PV210,
0056 };
0057 
0058 /*
0059  * struct s3c_ide_info - S3C PATA instance.
0060  * @clk: The clock resource for this controller.
0061  * @ide_addr: The area mapped for the hardware registers.
0062  * @sfr_addr: The area mapped for the special function registers.
0063  * @irq: The IRQ number we are using.
0064  * @cpu_type: The exact type of this controller.
0065  * @fifo_status_reg: The ATA_FIFO_STATUS register offset.
0066  */
0067 struct s3c_ide_info {
0068     struct clk *clk;
0069     void __iomem *ide_addr;
0070     void __iomem *sfr_addr;
0071     int irq;
0072     enum s3c_cpu_type cpu_type;
0073     unsigned int fifo_status_reg;
0074 };
0075 
0076 static void pata_s3c_set_endian(void __iomem *s3c_ide_regbase, u8 mode)
0077 {
0078     u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG);
0079     reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg | S3C_ATA_CFG_SWAP);
0080     writel(reg, s3c_ide_regbase + S3C_ATA_CFG);
0081 }
0082 
0083 static void pata_s3c_cfg_mode(void __iomem *s3c_ide_sfrbase)
0084 {
0085     /* Select true-ide as the internal operating mode */
0086     writel(readl(s3c_ide_sfrbase + S3C_CFATA_MUX) | S3C_CFATA_MUX_TRUEIDE,
0087         s3c_ide_sfrbase + S3C_CFATA_MUX);
0088 }
0089 
0090 static unsigned long
0091 pata_s3c_setup_timing(struct s3c_ide_info *info, const struct ata_timing *ata)
0092 {
0093     int t1 = ata->setup;
0094     int t2 = ata->act8b;
0095     int t2i = ata->rec8b;
0096     ulong piotime;
0097 
0098     piotime = ((t2i & 0xff) << 12) | ((t2 & 0xff) << 4) | (t1 & 0xf);
0099 
0100     return piotime;
0101 }
0102 
0103 static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
0104 {
0105     struct s3c_ide_info *info = ap->host->private_data;
0106     struct ata_timing timing;
0107     int cycle_time;
0108     ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
0109     ulong piotime;
0110 
0111     /* Enables IORDY if mode requires it */
0112     if (ata_pio_need_iordy(adev))
0113         ata_cfg |= S3C_ATA_CFG_IORDYEN;
0114     else
0115         ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
0116 
0117     cycle_time = (int)(1000000000UL / clk_get_rate(info->clk));
0118 
0119     ata_timing_compute(adev, adev->pio_mode, &timing,
0120                     cycle_time * 1000, 0);
0121 
0122     piotime = pata_s3c_setup_timing(info, &timing);
0123 
0124     writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
0125     writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
0126 }
0127 
0128 /*
0129  * Waits until the IDE controller is able to perform next read/write
0130  * operation to the disk. Needed for 64XX series boards only.
0131  */
0132 static int wait_for_host_ready(struct s3c_ide_info *info)
0133 {
0134     ulong timeout;
0135     void __iomem *fifo_reg = info->ide_addr + info->fifo_status_reg;
0136 
0137     /* wait for maximum of 20 msec */
0138     timeout = jiffies + msecs_to_jiffies(20);
0139     while (time_before(jiffies, timeout)) {
0140         if ((readl(fifo_reg) >> 28) == 0)
0141             return 0;
0142     }
0143     return -EBUSY;
0144 }
0145 
0146 /*
0147  * Writes to one of the task file registers.
0148  */
0149 static void ata_outb(struct ata_host *host, u8 addr, void __iomem *reg)
0150 {
0151     struct s3c_ide_info *info = host->private_data;
0152 
0153     wait_for_host_ready(info);
0154     writeb(addr, reg);
0155 }
0156 
0157 /*
0158  * Reads from one of the task file registers.
0159  */
0160 static u8 ata_inb(struct ata_host *host, void __iomem *reg)
0161 {
0162     struct s3c_ide_info *info = host->private_data;
0163     u8 temp;
0164 
0165     wait_for_host_ready(info);
0166     (void) readb(reg);
0167     wait_for_host_ready(info);
0168     temp = readb(info->ide_addr + S3C_ATA_PIO_RDATA);
0169     return temp;
0170 }
0171 
0172 /*
0173  * pata_s3c_tf_load - send taskfile registers to host controller
0174  */
0175 static void pata_s3c_tf_load(struct ata_port *ap,
0176                 const struct ata_taskfile *tf)
0177 {
0178     struct ata_ioports *ioaddr = &ap->ioaddr;
0179     unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
0180 
0181     if (tf->ctl != ap->last_ctl) {
0182         ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
0183         ap->last_ctl = tf->ctl;
0184         ata_wait_idle(ap);
0185     }
0186 
0187     if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
0188         ata_outb(ap->host, tf->hob_feature, ioaddr->feature_addr);
0189         ata_outb(ap->host, tf->hob_nsect, ioaddr->nsect_addr);
0190         ata_outb(ap->host, tf->hob_lbal, ioaddr->lbal_addr);
0191         ata_outb(ap->host, tf->hob_lbam, ioaddr->lbam_addr);
0192         ata_outb(ap->host, tf->hob_lbah, ioaddr->lbah_addr);
0193     }
0194 
0195     if (is_addr) {
0196         ata_outb(ap->host, tf->feature, ioaddr->feature_addr);
0197         ata_outb(ap->host, tf->nsect, ioaddr->nsect_addr);
0198         ata_outb(ap->host, tf->lbal, ioaddr->lbal_addr);
0199         ata_outb(ap->host, tf->lbam, ioaddr->lbam_addr);
0200         ata_outb(ap->host, tf->lbah, ioaddr->lbah_addr);
0201     }
0202 
0203     if (tf->flags & ATA_TFLAG_DEVICE)
0204         ata_outb(ap->host, tf->device, ioaddr->device_addr);
0205 
0206     ata_wait_idle(ap);
0207 }
0208 
0209 /*
0210  * pata_s3c_tf_read - input device's ATA taskfile shadow registers
0211  */
0212 static void pata_s3c_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
0213 {
0214     struct ata_ioports *ioaddr = &ap->ioaddr;
0215 
0216     tf->error = ata_inb(ap->host, ioaddr->error_addr);
0217     tf->nsect = ata_inb(ap->host, ioaddr->nsect_addr);
0218     tf->lbal = ata_inb(ap->host, ioaddr->lbal_addr);
0219     tf->lbam = ata_inb(ap->host, ioaddr->lbam_addr);
0220     tf->lbah = ata_inb(ap->host, ioaddr->lbah_addr);
0221     tf->device = ata_inb(ap->host, ioaddr->device_addr);
0222 
0223     if (tf->flags & ATA_TFLAG_LBA48) {
0224         ata_outb(ap->host, tf->ctl | ATA_HOB, ioaddr->ctl_addr);
0225         tf->hob_feature = ata_inb(ap->host, ioaddr->error_addr);
0226         tf->hob_nsect = ata_inb(ap->host, ioaddr->nsect_addr);
0227         tf->hob_lbal = ata_inb(ap->host, ioaddr->lbal_addr);
0228         tf->hob_lbam = ata_inb(ap->host, ioaddr->lbam_addr);
0229         tf->hob_lbah = ata_inb(ap->host, ioaddr->lbah_addr);
0230         ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
0231         ap->last_ctl = tf->ctl;
0232     }
0233 }
0234 
0235 /*
0236  * pata_s3c_exec_command - issue ATA command to host controller
0237  */
0238 static void pata_s3c_exec_command(struct ata_port *ap,
0239                 const struct ata_taskfile *tf)
0240 {
0241     ata_outb(ap->host, tf->command, ap->ioaddr.command_addr);
0242     ata_sff_pause(ap);
0243 }
0244 
0245 /*
0246  * pata_s3c_check_status - Read device status register
0247  */
0248 static u8 pata_s3c_check_status(struct ata_port *ap)
0249 {
0250     return ata_inb(ap->host, ap->ioaddr.status_addr);
0251 }
0252 
0253 /*
0254  * pata_s3c_check_altstatus - Read alternate device status register
0255  */
0256 static u8 pata_s3c_check_altstatus(struct ata_port *ap)
0257 {
0258     return ata_inb(ap->host, ap->ioaddr.altstatus_addr);
0259 }
0260 
0261 /*
0262  * pata_s3c_data_xfer - Transfer data by PIO
0263  */
0264 static unsigned int pata_s3c_data_xfer(struct ata_queued_cmd *qc,
0265                 unsigned char *buf, unsigned int buflen, int rw)
0266 {
0267     struct ata_port *ap = qc->dev->link->ap;
0268     struct s3c_ide_info *info = ap->host->private_data;
0269     void __iomem *data_addr = ap->ioaddr.data_addr;
0270     unsigned int words = buflen >> 1, i;
0271     u16 *data_ptr = (u16 *)buf;
0272 
0273     /* Requires wait same as in ata_inb/ata_outb */
0274     if (rw == READ)
0275         for (i = 0; i < words; i++, data_ptr++) {
0276             wait_for_host_ready(info);
0277             (void) readw(data_addr);
0278             wait_for_host_ready(info);
0279             *data_ptr = readw(info->ide_addr
0280                     + S3C_ATA_PIO_RDATA);
0281         }
0282     else
0283         for (i = 0; i < words; i++, data_ptr++) {
0284             wait_for_host_ready(info);
0285             writew(*data_ptr, data_addr);
0286         }
0287 
0288     if (buflen & 0x01)
0289         dev_err(ap->dev, "unexpected trailing data\n");
0290 
0291     return words << 1;
0292 }
0293 
0294 /*
0295  * pata_s3c_dev_select - Select device on ATA bus
0296  */
0297 static void pata_s3c_dev_select(struct ata_port *ap, unsigned int device)
0298 {
0299     u8 tmp = ATA_DEVICE_OBS;
0300 
0301     if (device != 0)
0302         tmp |= ATA_DEV1;
0303 
0304     ata_outb(ap->host, tmp, ap->ioaddr.device_addr);
0305     ata_sff_pause(ap);
0306 }
0307 
0308 /*
0309  * pata_s3c_devchk - PATA device presence detection
0310  */
0311 static bool pata_s3c_devchk(struct ata_port *ap, unsigned int device)
0312 {
0313     struct ata_ioports *ioaddr = &ap->ioaddr;
0314     u8 nsect, lbal;
0315 
0316     pata_s3c_dev_select(ap, device);
0317 
0318     ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
0319     ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
0320 
0321     ata_outb(ap->host, 0xaa, ioaddr->nsect_addr);
0322     ata_outb(ap->host, 0x55, ioaddr->lbal_addr);
0323 
0324     ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
0325     ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
0326 
0327     nsect = ata_inb(ap->host, ioaddr->nsect_addr);
0328     lbal = ata_inb(ap->host, ioaddr->lbal_addr);
0329 
0330     if ((nsect == 0x55) && (lbal == 0xaa))
0331         return true;    /* we found a device */
0332 
0333     return false;       /* nothing found */
0334 }
0335 
0336 /*
0337  * pata_s3c_wait_after_reset - wait for devices to become ready after reset
0338  */
0339 static int pata_s3c_wait_after_reset(struct ata_link *link,
0340         unsigned long deadline)
0341 {
0342     int rc;
0343 
0344     ata_msleep(link->ap, ATA_WAIT_AFTER_RESET);
0345 
0346     /* always check readiness of the master device */
0347     rc = ata_sff_wait_ready(link, deadline);
0348     /* -ENODEV means the odd clown forgot the D7 pulldown resistor
0349      * and TF status is 0xff, bail out on it too.
0350      */
0351     if (rc)
0352         return rc;
0353 
0354     return 0;
0355 }
0356 
0357 /*
0358  * pata_s3c_bus_softreset - PATA device software reset
0359  */
0360 static int pata_s3c_bus_softreset(struct ata_port *ap,
0361         unsigned long deadline)
0362 {
0363     struct ata_ioports *ioaddr = &ap->ioaddr;
0364 
0365     /* software reset.  causes dev0 to be selected */
0366     ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
0367     udelay(20);
0368     ata_outb(ap->host, ap->ctl | ATA_SRST, ioaddr->ctl_addr);
0369     udelay(20);
0370     ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
0371     ap->last_ctl = ap->ctl;
0372 
0373     return pata_s3c_wait_after_reset(&ap->link, deadline);
0374 }
0375 
0376 /*
0377  * pata_s3c_softreset - reset host port via ATA SRST
0378  */
0379 static int pata_s3c_softreset(struct ata_link *link, unsigned int *classes,
0380              unsigned long deadline)
0381 {
0382     struct ata_port *ap = link->ap;
0383     unsigned int devmask = 0;
0384     int rc;
0385     u8 err;
0386 
0387     /* determine if device 0 is present */
0388     if (pata_s3c_devchk(ap, 0))
0389         devmask |= (1 << 0);
0390 
0391     /* select device 0 again */
0392     pata_s3c_dev_select(ap, 0);
0393 
0394     /* issue bus reset */
0395     rc = pata_s3c_bus_softreset(ap, deadline);
0396     /* if link is occupied, -ENODEV too is an error */
0397     if (rc && rc != -ENODEV) {
0398         ata_link_err(link, "SRST failed (errno=%d)\n", rc);
0399         return rc;
0400     }
0401 
0402     /* determine by signature whether we have ATA or ATAPI devices */
0403     classes[0] = ata_sff_dev_classify(&ap->link.device[0],
0404                       devmask & (1 << 0), &err);
0405 
0406     return 0;
0407 }
0408 
0409 /*
0410  * pata_s3c_set_devctl - Write device control register
0411  */
0412 static void pata_s3c_set_devctl(struct ata_port *ap, u8 ctl)
0413 {
0414     ata_outb(ap->host, ctl, ap->ioaddr.ctl_addr);
0415 }
0416 
0417 static struct scsi_host_template pata_s3c_sht = {
0418     ATA_PIO_SHT(DRV_NAME),
0419 };
0420 
0421 static struct ata_port_operations pata_s3c_port_ops = {
0422     .inherits       = &ata_sff_port_ops,
0423     .sff_check_status   = pata_s3c_check_status,
0424     .sff_check_altstatus    = pata_s3c_check_altstatus,
0425     .sff_tf_load        = pata_s3c_tf_load,
0426     .sff_tf_read        = pata_s3c_tf_read,
0427     .sff_data_xfer      = pata_s3c_data_xfer,
0428     .sff_exec_command   = pata_s3c_exec_command,
0429     .sff_dev_select         = pata_s3c_dev_select,
0430     .sff_set_devctl         = pata_s3c_set_devctl,
0431     .softreset      = pata_s3c_softreset,
0432     .set_piomode        = pata_s3c_set_piomode,
0433 };
0434 
0435 static struct ata_port_operations pata_s5p_port_ops = {
0436     .inherits       = &ata_sff_port_ops,
0437     .set_piomode        = pata_s3c_set_piomode,
0438 };
0439 
0440 static void pata_s3c_enable(void __iomem *s3c_ide_regbase, bool state)
0441 {
0442     u32 temp = readl(s3c_ide_regbase + S3C_ATA_CTRL);
0443     temp = state ? (temp | 1) : (temp & ~1);
0444     writel(temp, s3c_ide_regbase + S3C_ATA_CTRL);
0445 }
0446 
0447 static irqreturn_t pata_s3c_irq(int irq, void *dev_instance)
0448 {
0449     struct ata_host *host = dev_instance;
0450     struct s3c_ide_info *info = host->private_data;
0451     u32 reg;
0452 
0453     reg = readl(info->ide_addr + S3C_ATA_IRQ);
0454     writel(reg, info->ide_addr + S3C_ATA_IRQ);
0455 
0456     return ata_sff_interrupt(irq, dev_instance);
0457 }
0458 
0459 static void pata_s3c_hwinit(struct s3c_ide_info *info,
0460                 struct s3c_ide_platdata *pdata)
0461 {
0462     switch (info->cpu_type) {
0463     case TYPE_S3C64XX:
0464         /* Configure as big endian */
0465         pata_s3c_cfg_mode(info->sfr_addr);
0466         pata_s3c_set_endian(info->ide_addr, 1);
0467         pata_s3c_enable(info->ide_addr, true);
0468         msleep(100);
0469 
0470         /* Remove IRQ Status */
0471         writel(0x1f, info->ide_addr + S3C_ATA_IRQ);
0472         writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
0473         break;
0474 
0475     case TYPE_S5PV210:
0476         /* Configure as little endian */
0477         pata_s3c_set_endian(info->ide_addr, 0);
0478         pata_s3c_enable(info->ide_addr, true);
0479         msleep(100);
0480 
0481         /* Remove IRQ Status */
0482         writel(0x3f, info->ide_addr + S3C_ATA_IRQ);
0483         writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK);
0484         break;
0485 
0486     default:
0487         BUG();
0488     }
0489 }
0490 
0491 static int __init pata_s3c_probe(struct platform_device *pdev)
0492 {
0493     struct s3c_ide_platdata *pdata = dev_get_platdata(&pdev->dev);
0494     struct device *dev = &pdev->dev;
0495     struct s3c_ide_info *info;
0496     struct resource *res;
0497     struct ata_port *ap;
0498     struct ata_host *host;
0499     enum s3c_cpu_type cpu_type;
0500     int ret;
0501 
0502     cpu_type = platform_get_device_id(pdev)->driver_data;
0503 
0504     info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
0505     if (!info)
0506         return -ENOMEM;
0507 
0508     info->irq = platform_get_irq(pdev, 0);
0509 
0510     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0511 
0512     info->ide_addr = devm_ioremap_resource(dev, res);
0513     if (IS_ERR(info->ide_addr))
0514         return PTR_ERR(info->ide_addr);
0515 
0516     info->clk = devm_clk_get(&pdev->dev, "cfcon");
0517     if (IS_ERR(info->clk)) {
0518         dev_err(dev, "failed to get access to cf controller clock\n");
0519         ret = PTR_ERR(info->clk);
0520         info->clk = NULL;
0521         return ret;
0522     }
0523 
0524     clk_enable(info->clk);
0525 
0526     /* init ata host */
0527     host = ata_host_alloc(dev, 1);
0528     if (!host) {
0529         dev_err(dev, "failed to allocate ide host\n");
0530         ret = -ENOMEM;
0531         goto stop_clk;
0532     }
0533 
0534     ap = host->ports[0];
0535     ap->pio_mask = ATA_PIO4;
0536 
0537     if (cpu_type == TYPE_S3C64XX) {
0538         ap->ops = &pata_s3c_port_ops;
0539         info->sfr_addr = info->ide_addr + 0x1800;
0540         info->ide_addr += 0x1900;
0541         info->fifo_status_reg = 0x94;
0542     } else {
0543         ap->ops = &pata_s5p_port_ops;
0544         info->fifo_status_reg = 0x84;
0545     }
0546 
0547     info->cpu_type = cpu_type;
0548 
0549     if (info->irq <= 0) {
0550         ap->flags |= ATA_FLAG_PIO_POLLING;
0551         info->irq = 0;
0552         ata_port_desc(ap, "no IRQ, using PIO polling\n");
0553     }
0554 
0555     ap->ioaddr.cmd_addr =  info->ide_addr + S3C_ATA_CMD;
0556     ap->ioaddr.data_addr = info->ide_addr + S3C_ATA_PIO_DTR;
0557     ap->ioaddr.error_addr = info->ide_addr + S3C_ATA_PIO_FED;
0558     ap->ioaddr.feature_addr = info->ide_addr + S3C_ATA_PIO_FED;
0559     ap->ioaddr.nsect_addr = info->ide_addr + S3C_ATA_PIO_SCR;
0560     ap->ioaddr.lbal_addr = info->ide_addr + S3C_ATA_PIO_LLR;
0561     ap->ioaddr.lbam_addr = info->ide_addr + S3C_ATA_PIO_LMR;
0562     ap->ioaddr.lbah_addr = info->ide_addr + S3C_ATA_PIO_LHR;
0563     ap->ioaddr.device_addr = info->ide_addr + S3C_ATA_PIO_DVR;
0564     ap->ioaddr.status_addr = info->ide_addr + S3C_ATA_PIO_CSD;
0565     ap->ioaddr.command_addr = info->ide_addr + S3C_ATA_PIO_CSD;
0566     ap->ioaddr.altstatus_addr = info->ide_addr + S3C_ATA_PIO_DAD;
0567     ap->ioaddr.ctl_addr = info->ide_addr + S3C_ATA_PIO_DAD;
0568 
0569     ata_port_desc(ap, "mmio cmd 0x%llx ",
0570             (unsigned long long)res->start);
0571 
0572     host->private_data = info;
0573 
0574     if (pdata && pdata->setup_gpio)
0575         pdata->setup_gpio();
0576 
0577     /* Set endianness and enable the interface */
0578     pata_s3c_hwinit(info, pdata);
0579 
0580     ret = ata_host_activate(host, info->irq,
0581                 info->irq ? pata_s3c_irq : NULL,
0582                 0, &pata_s3c_sht);
0583     if (ret)
0584         goto stop_clk;
0585 
0586     return 0;
0587 
0588 stop_clk:
0589     clk_disable(info->clk);
0590     return ret;
0591 }
0592 
0593 static int __exit pata_s3c_remove(struct platform_device *pdev)
0594 {
0595     struct ata_host *host = platform_get_drvdata(pdev);
0596     struct s3c_ide_info *info = host->private_data;
0597 
0598     ata_host_detach(host);
0599 
0600     clk_disable(info->clk);
0601 
0602     return 0;
0603 }
0604 
0605 #ifdef CONFIG_PM_SLEEP
0606 static int pata_s3c_suspend(struct device *dev)
0607 {
0608     struct ata_host *host = dev_get_drvdata(dev);
0609 
0610     ata_host_suspend(host, PMSG_SUSPEND);
0611     return 0;
0612 }
0613 
0614 static int pata_s3c_resume(struct device *dev)
0615 {
0616     struct ata_host *host = dev_get_drvdata(dev);
0617     struct s3c_ide_platdata *pdata = dev_get_platdata(dev);
0618     struct s3c_ide_info *info = host->private_data;
0619 
0620     pata_s3c_hwinit(info, pdata);
0621     ata_host_resume(host);
0622 
0623     return 0;
0624 }
0625 
0626 static const struct dev_pm_ops pata_s3c_pm_ops = {
0627     .suspend    = pata_s3c_suspend,
0628     .resume     = pata_s3c_resume,
0629 };
0630 #endif
0631 
0632 /* driver device registration */
0633 static const struct platform_device_id pata_s3c_driver_ids[] = {
0634     {
0635         .name       = "s3c64xx-pata",
0636         .driver_data    = TYPE_S3C64XX,
0637     }, {
0638         .name       = "s5pv210-pata",
0639         .driver_data    = TYPE_S5PV210,
0640     },
0641     { }
0642 };
0643 
0644 MODULE_DEVICE_TABLE(platform, pata_s3c_driver_ids);
0645 
0646 static struct platform_driver pata_s3c_driver = {
0647     .remove     = __exit_p(pata_s3c_remove),
0648     .id_table   = pata_s3c_driver_ids,
0649     .driver     = {
0650         .name   = DRV_NAME,
0651 #ifdef CONFIG_PM_SLEEP
0652         .pm = &pata_s3c_pm_ops,
0653 #endif
0654     },
0655 };
0656 
0657 module_platform_driver_probe(pata_s3c_driver, pata_s3c_probe);
0658 
0659 MODULE_AUTHOR("Abhilash Kesavan, <a.kesavan@samsung.com>");
0660 MODULE_DESCRIPTION("low-level driver for Samsung PATA controller");
0661 MODULE_LICENSE("GPL");
0662 MODULE_VERSION(DRV_VERSION);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!