drivers/ata/pata_rdc.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  pata_rdc        -   Driver for later RDC PATA controllers
0004  *
0005  *  This is actually a driver for hardware meeting
0006  *  INCITS 370-2004 (1510D): ATA Host Adapter Standards
0007  *
0008  *  Based on ata_piix.
0009  */
0010
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/pci.h>
0014 #include <linux/blkdev.h>
0015 #include <linux/delay.h>
0016 #include <linux/device.h>
0017 #include <linux/gfp.h>
0018 #include <scsi/scsi_host.h>
0019 #include <linux/libata.h>
0020 #include <linux/dmi.h>
0021
0022 #define DRV_NAME    "pata_rdc"
0023 #define DRV_VERSION "0.01"
0024
0025 struct rdc_host_priv {
0026     u32 saved_iocfg;
0027 };
0028
0029 /**
0030  *  rdc_pata_cable_detect - Probe host controller cable detect info
0031  *  @ap: Port for which cable detect info is desired
0032  *
0033  *  Read 80c cable indicator from ATA PCI device's PCI config
0034  *  register.  This register is normally set by firmware (BIOS).
0035  *
0036  *  LOCKING:
0037  *  None (inherited from caller).
0038  */
0039
0040 static int rdc_pata_cable_detect(struct ata_port *ap)
0041 {
0042     struct rdc_host_priv *hpriv = ap->host->private_data;
0043     u8 mask;
0044
0045     /* check BIOS cable detect results */
0046     mask = 0x30 << (2 * ap->port_no);
0047     if ((hpriv->saved_iocfg & mask) == 0)
0048         return ATA_CBL_PATA40;
0049     return ATA_CBL_PATA80;
0050 }
0051
0052 /**
0053  *  rdc_pata_prereset - prereset for PATA host controller
0054  *  @link: Target link
0055  *  @deadline: deadline jiffies for the operation
0056  *
0057  *  LOCKING:
0058  *  None (inherited from caller).
0059  */
0060 static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline)
0061 {
0062     struct ata_port *ap = link->ap;
0063     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0064
0065     static const struct pci_bits rdc_enable_bits[] = {
0066         { 0x41U, 1U, 0x80UL, 0x80UL },  /* port 0 */
0067         { 0x43U, 1U, 0x80UL, 0x80UL },  /* port 1 */
0068     };
0069
0070     if (!pci_test_config_bits(pdev, &rdc_enable_bits[ap->port_no]))
0071         return -ENOENT;
0072     return ata_sff_prereset(link, deadline);
0073 }
0074
0075 static DEFINE_SPINLOCK(rdc_lock);
0076
0077 /**
0078  *  rdc_set_piomode - Initialize host controller PATA PIO timings
0079  *  @ap: Port whose timings we are configuring
0080  *  @adev: um
0081  *
0082  *  Set PIO mode for device, in host controller PCI config space.
0083  *
0084  *  LOCKING:
0085  *  None (inherited from caller).
0086  */
0087
0088 static void rdc_set_piomode(struct ata_port *ap, struct ata_device *adev)
0089 {
0090     unsigned int pio    = adev->pio_mode - XFER_PIO_0;
0091     struct pci_dev *dev = to_pci_dev(ap->host->dev);
0092     unsigned long flags;
0093     unsigned int is_slave   = (adev->devno != 0);
0094     unsigned int master_port= ap->port_no ? 0x42 : 0x40;
0095     unsigned int slave_port = 0x44;
0096     u16 master_data;
0097     u8 slave_data;
0098     u8 udma_enable;
0099     int control = 0;
0100
0101     static const     /* ISP  RTC */
0102     u8 timings[][2] = { { 0, 0 },
0103                 { 0, 0 },
0104                 { 1, 0 },
0105                 { 2, 1 },
0106                 { 2, 3 }, };
0107
0108     if (pio >= 2)
0109         control |= 1;   /* TIME1 enable */
0110     if (ata_pio_need_iordy(adev))
0111         control |= 2;   /* IE enable */
0112
0113     if (adev->class == ATA_DEV_ATA)
0114         control |= 4;   /* PPE enable */
0115
0116     spin_lock_irqsave(&rdc_lock, flags);
0117
0118     /* PIO configuration clears DTE unconditionally.  It will be
0119      * programmed in set_dmamode which is guaranteed to be called
0120      * after set_piomode if any DMA mode is available.
0121      */
0122     pci_read_config_word(dev, master_port, &master_data);
0123     if (is_slave) {
0124         /* clear TIME1|IE1|PPE1|DTE1 */
0125         master_data &= 0xff0f;
0126         /* Enable SITRE (separate slave timing register) */
0127         master_data |= 0x4000;
0128         /* enable PPE1, IE1 and TIME1 as needed */
0129         master_data |= (control << 4);
0130         pci_read_config_byte(dev, slave_port, &slave_data);
0131         slave_data &= (ap->port_no ? 0x0f : 0xf0);
0132         /* Load the timing nibble for this slave */
0133         slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
0134                         << (ap->port_no ? 4 : 0);
0135     } else {
0136         /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
0137         master_data &= 0xccf0;
0138         /* Enable PPE, IE and TIME as appropriate */
0139         master_data |= control;
0140         /* load ISP and RCT */
0141         master_data |=
0142             (timings[pio][0] << 12) |
0143             (timings[pio][1] << 8);
0144     }
0145     pci_write_config_word(dev, master_port, master_data);
0146     if (is_slave)
0147         pci_write_config_byte(dev, slave_port, slave_data);
0148
0149     /* Ensure the UDMA bit is off - it will be turned back on if
0150        UDMA is selected */
0151
0152     pci_read_config_byte(dev, 0x48, &udma_enable);
0153     udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
0154     pci_write_config_byte(dev, 0x48, udma_enable);
0155
0156     spin_unlock_irqrestore(&rdc_lock, flags);
0157 }
0158
0159 /**
0160  *  rdc_set_dmamode - Initialize host controller PATA PIO timings
0161  *  @ap: Port whose timings we are configuring
0162  *  @adev: Drive in question
0163  *
0164  *  Set UDMA mode for device, in host controller PCI config space.
0165  *
0166  *  LOCKING:
0167  *  None (inherited from caller).
0168  */
0169
0170 static void rdc_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0171 {
0172     struct pci_dev *dev = to_pci_dev(ap->host->dev);
0173     unsigned long flags;
0174     u8 master_port      = ap->port_no ? 0x42 : 0x40;
0175     u16 master_data;
0176     u8 speed        = adev->dma_mode;
0177     int devid       = adev->devno + 2 * ap->port_no;
0178     u8 udma_enable      = 0;
0179
0180     static const     /* ISP  RTC */
0181     u8 timings[][2] = { { 0, 0 },
0182                 { 0, 0 },
0183                 { 1, 0 },
0184                 { 2, 1 },
0185                 { 2, 3 }, };
0186
0187     spin_lock_irqsave(&rdc_lock, flags);
0188
0189     pci_read_config_word(dev, master_port, &master_data);
0190     pci_read_config_byte(dev, 0x48, &udma_enable);
0191
0192     if (speed >= XFER_UDMA_0) {
0193         unsigned int udma = adev->dma_mode - XFER_UDMA_0;
0194         u16 udma_timing;
0195         u16 ideconf;
0196         int u_clock, u_speed;
0197
0198         /*
0199          * UDMA is handled by a combination of clock switching and
0200          * selection of dividers
0201          *
0202          * Handy rule: Odd modes are UDMATIMx 01, even are 02
0203          *         except UDMA0 which is 00
0204          */
0205         u_speed = min(2 - (udma & 1), udma);
0206         if (udma == 5)
0207             u_clock = 0x1000;   /* 100Mhz */
0208         else if (udma > 2)
0209             u_clock = 1;        /* 66Mhz */
0210         else
0211             u_clock = 0;        /* 33Mhz */
0212
0213         udma_enable |= (1 << devid);
0214
0215         /* Load the CT/RP selection */
0216         pci_read_config_word(dev, 0x4A, &udma_timing);
0217         udma_timing &= ~(3 << (4 * devid));
0218         udma_timing |= u_speed << (4 * devid);
0219         pci_write_config_word(dev, 0x4A, udma_timing);
0220
0221         /* Select a 33/66/100Mhz clock */
0222         pci_read_config_word(dev, 0x54, &ideconf);
0223         ideconf &= ~(0x1001 << devid);
0224         ideconf |= u_clock << devid;
0225         pci_write_config_word(dev, 0x54, ideconf);
0226     } else {
0227         /*
0228          * MWDMA is driven by the PIO timings. We must also enable
0229          * IORDY unconditionally along with TIME1. PPE has already
0230          * been set when the PIO timing was set.
0231          */
0232         unsigned int mwdma  = adev->dma_mode - XFER_MW_DMA_0;
0233         unsigned int control;
0234         u8 slave_data;
0235         const unsigned int needed_pio[3] = {
0236             XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
0237         };
0238         int pio = needed_pio[mwdma] - XFER_PIO_0;
0239
0240         control = 3;    /* IORDY|TIME1 */
0241
0242         /* If the drive MWDMA is faster than it can do PIO then
0243            we must force PIO into PIO0 */
0244
0245         if (adev->pio_mode < needed_pio[mwdma])
0246             /* Enable DMA timing only */
0247             control |= 8;   /* PIO cycles in PIO0 */
0248
0249         if (adev->devno) {  /* Slave */
0250             master_data &= 0xFF4F;  /* Mask out IORDY|TIME1|DMAONLY */
0251             master_data |= control << 4;
0252             pci_read_config_byte(dev, 0x44, &slave_data);
0253             slave_data &= (ap->port_no ? 0x0f : 0xf0);
0254             /* Load the matching timing */
0255             slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
0256             pci_write_config_byte(dev, 0x44, slave_data);
0257         } else {    /* Master */
0258             master_data &= 0xCCF4;  /* Mask out IORDY|TIME1|DMAONLY
0259                            and master timing bits */
0260             master_data |= control;
0261             master_data |=
0262                 (timings[pio][0] << 12) |
0263                 (timings[pio][1] << 8);
0264         }
0265
0266         udma_enable &= ~(1 << devid);
0267         pci_write_config_word(dev, master_port, master_data);
0268     }
0269     pci_write_config_byte(dev, 0x48, udma_enable);
0270
0271     spin_unlock_irqrestore(&rdc_lock, flags);
0272 }
0273
0274 static struct ata_port_operations rdc_pata_ops = {
0275     .inherits       = &ata_bmdma32_port_ops,
0276     .cable_detect       = rdc_pata_cable_detect,
0277     .set_piomode        = rdc_set_piomode,
0278     .set_dmamode        = rdc_set_dmamode,
0279     .prereset       = rdc_pata_prereset,
0280 };
0281
0282 static const struct ata_port_info rdc_port_info = {
0283
0284     .flags      = ATA_FLAG_SLAVE_POSS,
0285     .pio_mask   = ATA_PIO4,
0286     .mwdma_mask = ATA_MWDMA12_ONLY,
0287     .udma_mask  = ATA_UDMA5,
0288     .port_ops   = &rdc_pata_ops,
0289 };
0290
0291 static struct scsi_host_template rdc_sht = {
0292     ATA_BMDMA_SHT(DRV_NAME),
0293 };
0294
0295 /**
0296  *  rdc_init_one - Register PIIX ATA PCI device with kernel services
0297  *  @pdev: PCI device to register
0298  *  @ent: Entry in rdc_pci_tbl matching with @pdev
0299  *
0300  *  Called from kernel PCI layer.  We probe for combined mode (sigh),
0301  *  and then hand over control to libata, for it to do the rest.
0302  *
0303  *  LOCKING:
0304  *  Inherited from PCI layer (may sleep).
0305  *
0306  *  RETURNS:
0307  *  Zero on success, or -ERRNO value.
0308  */
0309
0310 static int rdc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
0311 {
0312     struct device *dev = &pdev->dev;
0313     struct ata_port_info port_info[2];
0314     const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
0315     struct ata_host *host;
0316     struct rdc_host_priv *hpriv;
0317     int rc;
0318
0319     ata_print_version_once(&pdev->dev, DRV_VERSION);
0320
0321     port_info[0] = rdc_port_info;
0322     port_info[1] = rdc_port_info;
0323
0324     /* enable device and prepare host */
0325     rc = pcim_enable_device(pdev);
0326     if (rc)
0327         return rc;
0328
0329     hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
0330     if (!hpriv)
0331         return -ENOMEM;
0332
0333     /* Save IOCFG, this will be used for cable detection, quirk
0334      * detection and restoration on detach.
0335      */
0336     pci_read_config_dword(pdev, 0x54, &hpriv->saved_iocfg);
0337
0338     rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
0339     if (rc)
0340         return rc;
0341     host->private_data = hpriv;
0342
0343     pci_intx(pdev, 1);
0344
0345     host->flags |= ATA_HOST_PARALLEL_SCAN;
0346
0347     pci_set_master(pdev);
0348     return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, &rdc_sht);
0349 }
0350
0351 static void rdc_remove_one(struct pci_dev *pdev)
0352 {
0353     struct ata_host *host = pci_get_drvdata(pdev);
0354     struct rdc_host_priv *hpriv = host->private_data;
0355
0356     pci_write_config_dword(pdev, 0x54, hpriv->saved_iocfg);
0357
0358     ata_pci_remove_one(pdev);
0359 }
0360
0361 static const struct pci_device_id rdc_pci_tbl[] = {
0362     { PCI_DEVICE(0x17F3, 0x1011), },
0363     { PCI_DEVICE(0x17F3, 0x1012), },
0364     { } /* terminate list */
0365 };
0366
0367 static struct pci_driver rdc_pci_driver = {
0368     .name           = DRV_NAME,
0369     .id_table       = rdc_pci_tbl,
0370     .probe          = rdc_init_one,
0371     .remove         = rdc_remove_one,
0372 #ifdef CONFIG_PM_SLEEP
0373     .suspend        = ata_pci_device_suspend,
0374     .resume         = ata_pci_device_resume,
0375 #endif
0376 };
0377
0378
0379 module_pci_driver(rdc_pci_driver);
0380
0381 MODULE_AUTHOR("Alan Cox (based on ata_piix)");
0382 MODULE_DESCRIPTION("SCSI low-level driver for RDC PATA controllers");
0383 MODULE_LICENSE("GPL");
0384 MODULE_DEVICE_TABLE(pci, rdc_pci_tbl);
0385 MODULE_VERSION(DRV_VERSION);