drivers/ata/pata_pdc202xx_old.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * pata_pdc202xx_old.c  - Promise PDC202xx PATA for new ATA layer
0004  *            (C) 2005 Red Hat Inc
0005  *            Alan Cox <alan@lxorguk.ukuu.org.uk>
0006  *            (C) 2007,2009,2010 Bartlomiej Zolnierkiewicz
0007  *
0008  * Based in part on linux/drivers/ide/pci/pdc202xx_old.c
0009  *
0010  * First cut with LBA48/ATAPI
0011  *
0012  * TODO:
0013  *  Channel interlock/reset on both required ?
0014  */
0015
0016 #include <linux/kernel.h>
0017 #include <linux/module.h>
0018 #include <linux/pci.h>
0019 #include <linux/blkdev.h>
0020 #include <linux/delay.h>
0021 #include <scsi/scsi_host.h>
0022 #include <linux/libata.h>
0023
0024 #define DRV_NAME "pata_pdc202xx_old"
0025 #define DRV_VERSION "0.4.3"
0026
0027 static int pdc2026x_cable_detect(struct ata_port *ap)
0028 {
0029     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0030     u16 cis;
0031
0032     pci_read_config_word(pdev, 0x50, &cis);
0033     if (cis & (1 << (10 + ap->port_no)))
0034         return ATA_CBL_PATA40;
0035     return ATA_CBL_PATA80;
0036 }
0037
0038 static void pdc202xx_exec_command(struct ata_port *ap,
0039                   const struct ata_taskfile *tf)
0040 {
0041     iowrite8(tf->command, ap->ioaddr.command_addr);
0042     ndelay(400);
0043 }
0044
0045 static bool pdc202xx_irq_check(struct ata_port *ap)
0046 {
0047     struct pci_dev *pdev    = to_pci_dev(ap->host->dev);
0048     unsigned long master    = pci_resource_start(pdev, 4);
0049     u8 sc1d         = inb(master + 0x1d);
0050
0051     if (ap->port_no) {
0052         /*
0053          * bit 7: error, bit 6: interrupting,
0054          * bit 5: FIFO full, bit 4: FIFO empty
0055          */
0056         return sc1d & 0x40;
0057     } else  {
0058         /*
0059          * bit 3: error, bit 2: interrupting,
0060          * bit 1: FIFO full, bit 0: FIFO empty
0061          */
0062         return sc1d & 0x04;
0063     }
0064 }
0065
0066 /**
0067  *  pdc202xx_configure_piomode  -   set chip PIO timing
0068  *  @ap: ATA interface
0069  *  @adev: ATA device
0070  *  @pio: PIO mode
0071  *
0072  *  Called to do the PIO mode setup. Our timing registers are shared
0073  *  so a configure_dmamode call will undo any work we do here and vice
0074  *  versa
0075  */
0076
0077 static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
0078 {
0079     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0080     int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
0081     static const u16 pio_timing[5] = {
0082         0x0913, 0x050C , 0x0308, 0x0206, 0x0104
0083     };
0084     u8 r_ap, r_bp;
0085
0086     pci_read_config_byte(pdev, port, &r_ap);
0087     pci_read_config_byte(pdev, port + 1, &r_bp);
0088     r_ap &= ~0x3F;  /* Preserve ERRDY_EN, SYNC_IN */
0089     r_bp &= ~0x1F;
0090     r_ap |= (pio_timing[pio] >> 8);
0091     r_bp |= (pio_timing[pio] & 0xFF);
0092
0093     if (ata_pio_need_iordy(adev))
0094         r_ap |= 0x20;   /* IORDY enable */
0095     if (adev->class == ATA_DEV_ATA)
0096         r_ap |= 0x10;   /* FIFO enable */
0097     pci_write_config_byte(pdev, port, r_ap);
0098     pci_write_config_byte(pdev, port + 1, r_bp);
0099 }
0100
0101 /**
0102  *  pdc202xx_set_piomode    -   set initial PIO mode data
0103  *  @ap: ATA interface
0104  *  @adev: ATA device
0105  *
0106  *  Called to do the PIO mode setup. Our timing registers are shared
0107  *  but we want to set the PIO timing by default.
0108  */
0109
0110 static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
0111 {
0112     pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
0113 }
0114
0115 /**
0116  *  pdc202xx_set_dmamode    -   set DMA mode in chip
0117  *  @ap: ATA interface
0118  *  @adev: ATA device
0119  *
0120  *  Load DMA cycle times into the chip ready for a DMA transfer
0121  *  to occur.
0122  */
0123
0124 static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0125 {
0126     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0127     int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
0128     static u8 udma_timing[6][2] = {
0129         { 0x60, 0x03 }, /* 33 Mhz Clock */
0130         { 0x40, 0x02 },
0131         { 0x20, 0x01 },
0132         { 0x40, 0x02 }, /* 66 Mhz Clock */
0133         { 0x20, 0x01 },
0134         { 0x20, 0x01 }
0135     };
0136     static u8 mdma_timing[3][2] = {
0137         { 0xe0, 0x0f },
0138         { 0x60, 0x04 },
0139         { 0x60, 0x03 },
0140     };
0141     u8 r_bp, r_cp;
0142
0143     pci_read_config_byte(pdev, port + 1, &r_bp);
0144     pci_read_config_byte(pdev, port + 2, &r_cp);
0145
0146     r_bp &= ~0xE0;
0147     r_cp &= ~0x0F;
0148
0149     if (adev->dma_mode >= XFER_UDMA_0) {
0150         int speed = adev->dma_mode - XFER_UDMA_0;
0151         r_bp |= udma_timing[speed][0];
0152         r_cp |= udma_timing[speed][1];
0153
0154     } else {
0155         int speed = adev->dma_mode - XFER_MW_DMA_0;
0156         r_bp |= mdma_timing[speed][0];
0157         r_cp |= mdma_timing[speed][1];
0158     }
0159     pci_write_config_byte(pdev, port + 1, r_bp);
0160     pci_write_config_byte(pdev, port + 2, r_cp);
0161
0162 }
0163
0164 /**
0165  *  pdc2026x_bmdma_start        -   DMA engine begin
0166  *  @qc: ATA command
0167  *
0168  *  In UDMA3 or higher we have to clock switch for the duration of the
0169  *  DMA transfer sequence.
0170  *
0171  *  Note: The host lock held by the libata layer protects
0172  *  us from two channels both trying to set DMA bits at once
0173  */
0174
0175 static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
0176 {
0177     struct ata_port *ap = qc->ap;
0178     struct ata_device *adev = qc->dev;
0179     struct ata_taskfile *tf = &qc->tf;
0180     int sel66 = ap->port_no ? 0x08: 0x02;
0181
0182     void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
0183     void __iomem *clock = master + 0x11;
0184     void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
0185
0186     u32 len;
0187
0188     /* Check we keep host level locking here */
0189     if (adev->dma_mode > XFER_UDMA_2)
0190         iowrite8(ioread8(clock) | sel66, clock);
0191     else
0192         iowrite8(ioread8(clock) & ~sel66, clock);
0193
0194     /* The DMA clocks may have been trashed by a reset. FIXME: make conditional
0195        and move to qc_issue ? */
0196     pdc202xx_set_dmamode(ap, qc->dev);
0197
0198     /* Cases the state machine will not complete correctly without help */
0199     if ((tf->flags & ATA_TFLAG_LBA48) ||  tf->protocol == ATAPI_PROT_DMA) {
0200         len = qc->nbytes / 2;
0201
0202         if (tf->flags & ATA_TFLAG_WRITE)
0203             len |= 0x06000000;
0204         else
0205             len |= 0x05000000;
0206
0207         iowrite32(len, atapi_reg);
0208     }
0209
0210     /* Activate DMA */
0211     ata_bmdma_start(qc);
0212 }
0213
0214 /**
0215  *  pdc2026x_bmdma_stop     -   DMA engine stop
0216  *  @qc: ATA command
0217  *
0218  *  After a DMA completes we need to put the clock back to 33MHz for
0219  *  PIO timings.
0220  *
0221  *  Note: The host lock held by the libata layer protects
0222  *  us from two channels both trying to set DMA bits at once
0223  */
0224
0225 static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
0226 {
0227     struct ata_port *ap = qc->ap;
0228     struct ata_device *adev = qc->dev;
0229     struct ata_taskfile *tf = &qc->tf;
0230
0231     int sel66 = ap->port_no ? 0x08: 0x02;
0232     /* The clock bits are in the same register for both channels */
0233     void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
0234     void __iomem *clock = master + 0x11;
0235     void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);
0236
0237     /* Cases the state machine will not complete correctly */
0238     if (tf->protocol == ATAPI_PROT_DMA || (tf->flags & ATA_TFLAG_LBA48)) {
0239         iowrite32(0, atapi_reg);
0240         iowrite8(ioread8(clock) & ~sel66, clock);
0241     }
0242     /* Flip back to 33Mhz for PIO */
0243     if (adev->dma_mode > XFER_UDMA_2)
0244         iowrite8(ioread8(clock) & ~sel66, clock);
0245     ata_bmdma_stop(qc);
0246     pdc202xx_set_piomode(ap, adev);
0247 }
0248
0249 /**
0250  *  pdc2026x_dev_config -   device setup hook
0251  *  @adev: newly found device
0252  *
0253  *  Perform chip specific early setup. We need to lock the transfer
0254  *  sizes to 8bit to avoid making the state engine on the 2026x cards
0255  *  barf.
0256  */
0257
0258 static void pdc2026x_dev_config(struct ata_device *adev)
0259 {
0260     adev->max_sectors = 256;
0261 }
0262
0263 static int pdc2026x_port_start(struct ata_port *ap)
0264 {
0265     void __iomem *bmdma = ap->ioaddr.bmdma_addr;
0266     if (bmdma) {
0267         /* Enable burst mode */
0268         u8 burst = ioread8(bmdma + 0x1f);
0269         iowrite8(burst | 0x01, bmdma + 0x1f);
0270     }
0271     return ata_bmdma_port_start(ap);
0272 }
0273
0274 /**
0275  *  pdc2026x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
0276  *  @qc: Metadata associated with taskfile to check
0277  *
0278  *  Just say no - not supported on older Promise.
0279  *
0280  *  LOCKING:
0281  *  None (inherited from caller).
0282  *
0283  *  RETURNS: 0 when ATAPI DMA can be used
0284  *       1 otherwise
0285  */
0286
0287 static int pdc2026x_check_atapi_dma(struct ata_queued_cmd *qc)
0288 {
0289     return 1;
0290 }
0291
0292 static struct scsi_host_template pdc202xx_sht = {
0293     ATA_BMDMA_SHT(DRV_NAME),
0294 };
0295
0296 static struct ata_port_operations pdc2024x_port_ops = {
0297     .inherits       = &ata_bmdma_port_ops,
0298
0299     .cable_detect       = ata_cable_40wire,
0300     .set_piomode        = pdc202xx_set_piomode,
0301     .set_dmamode        = pdc202xx_set_dmamode,
0302
0303     .sff_exec_command   = pdc202xx_exec_command,
0304     .sff_irq_check      = pdc202xx_irq_check,
0305 };
0306
0307 static struct ata_port_operations pdc2026x_port_ops = {
0308     .inherits       = &pdc2024x_port_ops,
0309
0310     .check_atapi_dma    = pdc2026x_check_atapi_dma,
0311     .bmdma_start        = pdc2026x_bmdma_start,
0312     .bmdma_stop     = pdc2026x_bmdma_stop,
0313
0314     .cable_detect       = pdc2026x_cable_detect,
0315     .dev_config     = pdc2026x_dev_config,
0316
0317     .port_start     = pdc2026x_port_start,
0318
0319     .sff_exec_command   = pdc202xx_exec_command,
0320     .sff_irq_check      = pdc202xx_irq_check,
0321 };
0322
0323 static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
0324 {
0325     static const struct ata_port_info info[3] = {
0326         {
0327             .flags = ATA_FLAG_SLAVE_POSS,
0328             .pio_mask = ATA_PIO4,
0329             .mwdma_mask = ATA_MWDMA2,
0330             .udma_mask = ATA_UDMA2,
0331             .port_ops = &pdc2024x_port_ops
0332         },
0333         {
0334             .flags = ATA_FLAG_SLAVE_POSS,
0335             .pio_mask = ATA_PIO4,
0336             .mwdma_mask = ATA_MWDMA2,
0337             .udma_mask = ATA_UDMA4,
0338             .port_ops = &pdc2026x_port_ops
0339         },
0340         {
0341             .flags = ATA_FLAG_SLAVE_POSS,
0342             .pio_mask = ATA_PIO4,
0343             .mwdma_mask = ATA_MWDMA2,
0344             .udma_mask = ATA_UDMA5,
0345             .port_ops = &pdc2026x_port_ops
0346         }
0347
0348     };
0349     const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
0350
0351     if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
0352         struct pci_dev *bridge = dev->bus->self;
0353         /* Don't grab anything behind a Promise I2O RAID */
0354         if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
0355             if (bridge->device == PCI_DEVICE_ID_INTEL_I960)
0356                 return -ENODEV;
0357             if (bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
0358                 return -ENODEV;
0359         }
0360     }
0361     return ata_pci_bmdma_init_one(dev, ppi, &pdc202xx_sht, NULL, 0);
0362 }
0363
0364 static const struct pci_device_id pdc202xx[] = {
0365     { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
0366     { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
0367     { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
0368     { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
0369     { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
0370
0371     { },
0372 };
0373
0374 static struct pci_driver pdc202xx_pci_driver = {
0375     .name       = DRV_NAME,
0376     .id_table   = pdc202xx,
0377     .probe      = pdc202xx_init_one,
0378     .remove     = ata_pci_remove_one,
0379 #ifdef CONFIG_PM_SLEEP
0380     .suspend    = ata_pci_device_suspend,
0381     .resume     = ata_pci_device_resume,
0382 #endif
0383 };
0384
0385 module_pci_driver(pdc202xx_pci_driver);
0386
0387 MODULE_AUTHOR("Alan Cox");
0388 MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
0389 MODULE_LICENSE("GPL");
0390 MODULE_DEVICE_TABLE(pci, pdc202xx);
0391 MODULE_VERSION(DRV_VERSION);