drivers/ata/pata_optidma.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * pata_optidma.c   - Opti DMA PATA for new ATA layer
0004  *            (C) 2006 Red Hat Inc
0005  *
0006  *  The Opti DMA controllers are related to the older PIO PCI controllers
0007  *  and indeed the VLB ones. The main differences are that the timing
0008  *  numbers are now based off PCI clocks not VLB and differ, and that
0009  *  MWDMA is supported.
0010  *
0011  *  This driver should support Viper-N+, FireStar, FireStar Plus.
0012  *
0013  *  These devices support virtual DMA for read (aka the CS5520). Later
0014  *  chips support UDMA33, but only if the rest of the board logic does,
0015  *  so you have to get this right. We don't support the virtual DMA
0016  *  but we do handle UDMA.
0017  *
0018  *  Bits that are worth knowing
0019  *      Most control registers are shadowed into I/O registers
0020  *      0x1F5 bit 0 tells you if the PCI/VLB clock is 33 or 25Mhz
0021  *      Virtual DMA registers *move* between rev 0x02 and rev 0x10
0022  *      UDMA requires a 66MHz FSB
0023  *
0024  */
0025
0026 #include <linux/kernel.h>
0027 #include <linux/module.h>
0028 #include <linux/pci.h>
0029 #include <linux/blkdev.h>
0030 #include <linux/delay.h>
0031 #include <scsi/scsi_host.h>
0032 #include <linux/libata.h>
0033
0034 #define DRV_NAME "pata_optidma"
0035 #define DRV_VERSION "0.3.2"
0036
0037 enum {
0038     READ_REG    = 0,    /* index of Read cycle timing register */
0039     WRITE_REG   = 1,    /* index of Write cycle timing register */
0040     CNTRL_REG   = 3,    /* index of Control register */
0041     STRAP_REG   = 5,    /* index of Strap register */
0042     MISC_REG    = 6 /* index of Miscellaneous register */
0043 };
0044
0045 static int pci_clock;   /* 0 = 33 1 = 25 */
0046
0047 /**
0048  *  optidma_pre_reset       -   probe begin
0049  *  @link: ATA link
0050  *  @deadline: deadline jiffies for the operation
0051  *
0052  *  Set up cable type and use generic probe init
0053  */
0054
0055 static int optidma_pre_reset(struct ata_link *link, unsigned long deadline)
0056 {
0057     struct ata_port *ap = link->ap;
0058     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0059     static const struct pci_bits optidma_enable_bits = {
0060         0x40, 1, 0x08, 0x00
0061     };
0062
0063     if (ap->port_no && !pci_test_config_bits(pdev, &optidma_enable_bits))
0064         return -ENOENT;
0065
0066     return ata_sff_prereset(link, deadline);
0067 }
0068
0069 /**
0070  *  optidma_unlock      -   unlock control registers
0071  *  @ap: ATA port
0072  *
0073  *  Unlock the control register block for this adapter. Registers must not
0074  *  be unlocked in a situation where libata might look at them.
0075  */
0076
0077 static void optidma_unlock(struct ata_port *ap)
0078 {
0079     void __iomem *regio = ap->ioaddr.cmd_addr;
0080
0081     /* These 3 unlock the control register access */
0082     ioread16(regio + 1);
0083     ioread16(regio + 1);
0084     iowrite8(3, regio + 2);
0085 }
0086
0087 /**
0088  *  optidma_lock        -   issue temporary relock
0089  *  @ap: ATA port
0090  *
0091  *  Re-lock the configuration register settings.
0092  */
0093
0094 static void optidma_lock(struct ata_port *ap)
0095 {
0096     void __iomem *regio = ap->ioaddr.cmd_addr;
0097
0098     /* Relock */
0099     iowrite8(0x83, regio + 2);
0100 }
0101
0102 /**
0103  *  optidma_mode_setup  -   set mode data
0104  *  @ap: ATA interface
0105  *  @adev: ATA device
0106  *  @mode: Mode to set
0107  *
0108  *  Called to do the DMA or PIO mode setup. Timing numbers are all
0109  *  pre computed to keep the code clean. There are two tables depending
0110  *  on the hardware clock speed.
0111  *
0112  *  WARNING: While we do this the IDE registers vanish. If we take an
0113  *  IRQ here we depend on the host set locking to avoid catastrophe.
0114  */
0115
0116 static void optidma_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
0117 {
0118     struct ata_device *pair = ata_dev_pair(adev);
0119     int pio = adev->pio_mode - XFER_PIO_0;
0120     int dma = adev->dma_mode - XFER_MW_DMA_0;
0121     void __iomem *regio = ap->ioaddr.cmd_addr;
0122     u8 addr;
0123
0124     /* Address table precomputed with a DCLK of 2 */
0125     static const u8 addr_timing[2][5] = {
0126         { 0x30, 0x20, 0x20, 0x10, 0x10 },
0127         { 0x20, 0x20, 0x10, 0x10, 0x10 }
0128     };
0129     static const u8 data_rec_timing[2][5] = {
0130         { 0x59, 0x46, 0x30, 0x20, 0x20 },
0131         { 0x46, 0x32, 0x20, 0x20, 0x10 }
0132     };
0133     static const u8 dma_data_rec_timing[2][3] = {
0134         { 0x76, 0x20, 0x20 },
0135         { 0x54, 0x20, 0x10 }
0136     };
0137
0138     /* Switch from IDE to control mode */
0139     optidma_unlock(ap);
0140
0141
0142     /*
0143      *  As with many controllers the address setup time is shared
0144      *  and must suit both devices if present. FIXME: Check if we
0145      *  need to look at slowest of PIO/DMA mode of either device
0146      */
0147
0148     if (mode >= XFER_MW_DMA_0)
0149         addr = 0;
0150     else
0151         addr = addr_timing[pci_clock][pio];
0152
0153     if (pair) {
0154         u8 pair_addr;
0155         /* Hardware constraint */
0156         if (ata_dma_enabled(pair))
0157             pair_addr = 0;
0158         else
0159             pair_addr = addr_timing[pci_clock][pair->pio_mode - XFER_PIO_0];
0160         if (pair_addr > addr)
0161             addr = pair_addr;
0162     }
0163
0164     /* Commence primary programming sequence */
0165     /* First we load the device number into the timing select */
0166     iowrite8(adev->devno, regio + MISC_REG);
0167     /* Now we load the data timings into read data/write data */
0168     if (mode < XFER_MW_DMA_0) {
0169         iowrite8(data_rec_timing[pci_clock][pio], regio + READ_REG);
0170         iowrite8(data_rec_timing[pci_clock][pio], regio + WRITE_REG);
0171     } else if (mode < XFER_UDMA_0) {
0172         iowrite8(dma_data_rec_timing[pci_clock][dma], regio + READ_REG);
0173         iowrite8(dma_data_rec_timing[pci_clock][dma], regio + WRITE_REG);
0174     }
0175     /* Finally we load the address setup into the misc register */
0176     iowrite8(addr | adev->devno, regio + MISC_REG);
0177
0178     /* Programming sequence complete, timing 0 dev 0, timing 1 dev 1 */
0179     iowrite8(0x85, regio + CNTRL_REG);
0180
0181     /* Switch back to IDE mode */
0182     optidma_lock(ap);
0183
0184     /* Note: at this point our programming is incomplete. We are
0185        not supposed to program PCI 0x43 "things we hacked onto the chip"
0186        until we've done both sets of PIO/DMA timings */
0187 }
0188
0189 /**
0190  *  optiplus_mode_setup -   DMA setup for Firestar Plus
0191  *  @ap: ATA port
0192  *  @adev: device
0193  *  @mode: desired mode
0194  *
0195  *  The Firestar plus has additional UDMA functionality for UDMA0-2 and
0196  *  requires we do some additional work. Because the base work we must do
0197  *  is mostly shared we wrap the Firestar setup functionality in this
0198  *  one
0199  */
0200
0201 static void optiplus_mode_setup(struct ata_port *ap, struct ata_device *adev, u8 mode)
0202 {
0203     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0204     u8 udcfg;
0205     u8 udslave;
0206     int dev2 = 2 * adev->devno;
0207     int unit = 2 * ap->port_no + adev->devno;
0208     int udma = mode - XFER_UDMA_0;
0209
0210     pci_read_config_byte(pdev, 0x44, &udcfg);
0211     if (mode <= XFER_UDMA_0) {
0212         udcfg &= ~(1 << unit);
0213         optidma_mode_setup(ap, adev, adev->dma_mode);
0214     } else {
0215         udcfg |=  (1 << unit);
0216         if (ap->port_no) {
0217             pci_read_config_byte(pdev, 0x45, &udslave);
0218             udslave &= ~(0x03 << dev2);
0219             udslave |= (udma << dev2);
0220             pci_write_config_byte(pdev, 0x45, udslave);
0221         } else {
0222             udcfg &= ~(0x30 << dev2);
0223             udcfg |= (udma << dev2);
0224         }
0225     }
0226     pci_write_config_byte(pdev, 0x44, udcfg);
0227 }
0228
0229 /**
0230  *  optidma_set_pio_mode    -   PIO setup callback
0231  *  @ap: ATA port
0232  *  @adev: Device
0233  *
0234  *  The libata core provides separate functions for handling PIO and
0235  *  DMA programming. The architecture of the Firestar makes it easier
0236  *  for us to have a common function so we provide wrappers
0237  */
0238
0239 static void optidma_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
0240 {
0241     optidma_mode_setup(ap, adev, adev->pio_mode);
0242 }
0243
0244 /**
0245  *  optidma_set_dma_mode    -   DMA setup callback
0246  *  @ap: ATA port
0247  *  @adev: Device
0248  *
0249  *  The libata core provides separate functions for handling PIO and
0250  *  DMA programming. The architecture of the Firestar makes it easier
0251  *  for us to have a common function so we provide wrappers
0252  */
0253
0254 static void optidma_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
0255 {
0256     optidma_mode_setup(ap, adev, adev->dma_mode);
0257 }
0258
0259 /**
0260  *  optiplus_set_pio_mode   -   PIO setup callback
0261  *  @ap: ATA port
0262  *  @adev: Device
0263  *
0264  *  The libata core provides separate functions for handling PIO and
0265  *  DMA programming. The architecture of the Firestar makes it easier
0266  *  for us to have a common function so we provide wrappers
0267  */
0268
0269 static void optiplus_set_pio_mode(struct ata_port *ap, struct ata_device *adev)
0270 {
0271     optiplus_mode_setup(ap, adev, adev->pio_mode);
0272 }
0273
0274 /**
0275  *  optiplus_set_dma_mode   -   DMA setup callback
0276  *  @ap: ATA port
0277  *  @adev: Device
0278  *
0279  *  The libata core provides separate functions for handling PIO and
0280  *  DMA programming. The architecture of the Firestar makes it easier
0281  *  for us to have a common function so we provide wrappers
0282  */
0283
0284 static void optiplus_set_dma_mode(struct ata_port *ap, struct ata_device *adev)
0285 {
0286     optiplus_mode_setup(ap, adev, adev->dma_mode);
0287 }
0288
0289 /**
0290  *  optidma_make_bits43 -   PCI setup helper
0291  *  @adev: ATA device
0292  *
0293  *  Turn the ATA device setup into PCI configuration bits
0294  *  for register 0x43 and return the two bits needed.
0295  */
0296
0297 static u8 optidma_make_bits43(struct ata_device *adev)
0298 {
0299     static const u8 bits43[5] = {
0300         0, 0, 0, 1, 2
0301     };
0302     if (!ata_dev_enabled(adev))
0303         return 0;
0304     if (ata_dma_enabled(adev))
0305         return adev->dma_mode - XFER_MW_DMA_0;
0306     return bits43[adev->pio_mode - XFER_PIO_0];
0307 }
0308
0309 /**
0310  *  optidma_set_mode    -   mode setup
0311  *  @link: link to set up
0312  *  @r_failed: out parameter for failed device
0313  *
0314  *  Use the standard setup to tune the chipset and then finalise the
0315  *  configuration by writing the nibble of extra bits of data into
0316  *  the chip.
0317  */
0318
0319 static int optidma_set_mode(struct ata_link *link, struct ata_device **r_failed)
0320 {
0321     struct ata_port *ap = link->ap;
0322     u8 r;
0323     int nybble = 4 * ap->port_no;
0324     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0325     int rc  = ata_do_set_mode(link, r_failed);
0326     if (rc == 0) {
0327         pci_read_config_byte(pdev, 0x43, &r);
0328
0329         r &= (0x0F << nybble);
0330         r |= (optidma_make_bits43(&link->device[0]) +
0331              (optidma_make_bits43(&link->device[0]) << 2)) << nybble;
0332         pci_write_config_byte(pdev, 0x43, r);
0333     }
0334     return rc;
0335 }
0336
0337 static struct scsi_host_template optidma_sht = {
0338     ATA_BMDMA_SHT(DRV_NAME),
0339 };
0340
0341 static struct ata_port_operations optidma_port_ops = {
0342     .inherits   = &ata_bmdma_port_ops,
0343     .cable_detect   = ata_cable_40wire,
0344     .set_piomode    = optidma_set_pio_mode,
0345     .set_dmamode    = optidma_set_dma_mode,
0346     .set_mode   = optidma_set_mode,
0347     .prereset   = optidma_pre_reset,
0348 };
0349
0350 static struct ata_port_operations optiplus_port_ops = {
0351     .inherits   = &optidma_port_ops,
0352     .set_piomode    = optiplus_set_pio_mode,
0353     .set_dmamode    = optiplus_set_dma_mode,
0354 };
0355
0356 /**
0357  *  optiplus_with_udma  -   Look for UDMA capable setup
0358  *  @pdev: ATA controller
0359  */
0360
0361 static int optiplus_with_udma(struct pci_dev *pdev)
0362 {
0363     u8 r;
0364     int ret = 0;
0365     int ioport = 0x22;
0366     struct pci_dev *dev1;
0367
0368     /* Find function 1 */
0369     dev1 = pci_get_device(0x1045, 0xC701, NULL);
0370     if (dev1 == NULL)
0371         return 0;
0372
0373     /* Rev must be >= 0x10 */
0374     pci_read_config_byte(dev1, 0x08, &r);
0375     if (r < 0x10)
0376         goto done_nomsg;
0377     /* Read the chipset system configuration to check our mode */
0378     pci_read_config_byte(dev1, 0x5F, &r);
0379     ioport |= (r << 8);
0380     outb(0x10, ioport);
0381     /* Must be 66Mhz sync */
0382     if ((inb(ioport + 2) & 1) == 0)
0383         goto done;
0384
0385     /* Check the ATA arbitration/timing is suitable */
0386     pci_read_config_byte(pdev, 0x42, &r);
0387     if ((r & 0x36) != 0x36)
0388         goto done;
0389     pci_read_config_byte(dev1, 0x52, &r);
0390     if (r & 0x80)   /* IDEDIR disabled */
0391         ret = 1;
0392 done:
0393     printk(KERN_WARNING "UDMA not supported in this configuration.\n");
0394 done_nomsg:     /* Wrong chip revision */
0395     pci_dev_put(dev1);
0396     return ret;
0397 }
0398
0399 static int optidma_init_one(struct pci_dev *dev, const struct pci_device_id *id)
0400 {
0401     static const struct ata_port_info info_82c700 = {
0402         .flags = ATA_FLAG_SLAVE_POSS,
0403         .pio_mask = ATA_PIO4,
0404         .mwdma_mask = ATA_MWDMA2,
0405         .port_ops = &optidma_port_ops
0406     };
0407     static const struct ata_port_info info_82c700_udma = {
0408         .flags = ATA_FLAG_SLAVE_POSS,
0409         .pio_mask = ATA_PIO4,
0410         .mwdma_mask = ATA_MWDMA2,
0411         .udma_mask = ATA_UDMA2,
0412         .port_ops = &optiplus_port_ops
0413     };
0414     const struct ata_port_info *ppi[] = { &info_82c700, NULL };
0415     int rc;
0416
0417     ata_print_version_once(&dev->dev, DRV_VERSION);
0418
0419     rc = pcim_enable_device(dev);
0420     if (rc)
0421         return rc;
0422
0423     /* Fixed location chipset magic */
0424     inw(0x1F1);
0425     inw(0x1F1);
0426     pci_clock = inb(0x1F5) & 1;     /* 0 = 33Mhz, 1 = 25Mhz */
0427
0428     if (optiplus_with_udma(dev))
0429         ppi[0] = &info_82c700_udma;
0430
0431     return ata_pci_bmdma_init_one(dev, ppi, &optidma_sht, NULL, 0);
0432 }
0433
0434 static const struct pci_device_id optidma[] = {
0435     { PCI_VDEVICE(OPTI, 0xD568), },     /* Opti 82C700 */
0436
0437     { },
0438 };
0439
0440 static struct pci_driver optidma_pci_driver = {
0441     .name       = DRV_NAME,
0442     .id_table   = optidma,
0443     .probe      = optidma_init_one,
0444     .remove     = ata_pci_remove_one,
0445 #ifdef CONFIG_PM_SLEEP
0446     .suspend    = ata_pci_device_suspend,
0447     .resume     = ata_pci_device_resume,
0448 #endif
0449 };
0450
0451 module_pci_driver(optidma_pci_driver);
0452
0453 MODULE_AUTHOR("Alan Cox");
0454 MODULE_DESCRIPTION("low-level driver for Opti Firestar/Firestar Plus");
0455 MODULE_LICENSE("GPL");
0456 MODULE_DEVICE_TABLE(pci, optidma);
0457 MODULE_VERSION(DRV_VERSION);