drivers/ata/pata_oldpiix.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *    pata_oldpiix.c - Intel PATA/SATA controllers
0004  *
0005  *  (C) 2005 Red Hat
0006  *
0007  *    Some parts based on ata_piix.c by Jeff Garzik and others.
0008  *
0009  *    Early PIIX differs significantly from the later PIIX as it lacks
0010  *    SITRE and the slave timing registers. This means that you have to
0011  *    set timing per channel, or be clever. Libata tells us whenever it
0012  *    does drive selection and we use this to reload the timings.
0013  *
0014  *    Because of these behaviour differences PIIX gets its own driver module.
0015  */
0016
0017 #include <linux/kernel.h>
0018 #include <linux/module.h>
0019 #include <linux/pci.h>
0020 #include <linux/blkdev.h>
0021 #include <linux/delay.h>
0022 #include <linux/device.h>
0023 #include <scsi/scsi_host.h>
0024 #include <linux/libata.h>
0025 #include <linux/ata.h>
0026
0027 #define DRV_NAME    "pata_oldpiix"
0028 #define DRV_VERSION "0.5.5"
0029
0030 /**
0031  *  oldpiix_pre_reset       -   probe begin
0032  *  @link: ATA link
0033  *  @deadline: deadline jiffies for the operation
0034  *
0035  *  Set up cable type and use generic probe init
0036  */
0037
0038 static int oldpiix_pre_reset(struct ata_link *link, unsigned long deadline)
0039 {
0040     struct ata_port *ap = link->ap;
0041     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0042     static const struct pci_bits oldpiix_enable_bits[] = {
0043         { 0x41U, 1U, 0x80UL, 0x80UL },  /* port 0 */
0044         { 0x43U, 1U, 0x80UL, 0x80UL },  /* port 1 */
0045     };
0046
0047     if (!pci_test_config_bits(pdev, &oldpiix_enable_bits[ap->port_no]))
0048         return -ENOENT;
0049
0050     return ata_sff_prereset(link, deadline);
0051 }
0052
0053 /**
0054  *  oldpiix_set_piomode - Initialize host controller PATA PIO timings
0055  *  @ap: Port whose timings we are configuring
0056  *  @adev: Device whose timings we are configuring
0057  *
0058  *  Set PIO mode for device, in host controller PCI config space.
0059  *
0060  *  LOCKING:
0061  *  None (inherited from caller).
0062  */
0063
0064 static void oldpiix_set_piomode (struct ata_port *ap, struct ata_device *adev)
0065 {
0066     unsigned int pio    = adev->pio_mode - XFER_PIO_0;
0067     struct pci_dev *dev = to_pci_dev(ap->host->dev);
0068     unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
0069     u16 idetm_data;
0070     int control = 0;
0071
0072     /*
0073      *  See Intel Document 298600-004 for the timing programing rules
0074      *  for PIIX/ICH. Note that the early PIIX does not have the slave
0075      *  timing port at 0x44.
0076      */
0077
0078     static const     /* ISP  RTC */
0079     u8 timings[][2] = { { 0, 0 },
0080                 { 0, 0 },
0081                 { 1, 0 },
0082                 { 2, 1 },
0083                 { 2, 3 }, };
0084
0085     if (pio > 1)
0086         control |= 1;   /* TIME */
0087     if (ata_pio_need_iordy(adev))
0088         control |= 2;   /* IE */
0089
0090     /* Intel specifies that the prefetch/posting is for disk only */
0091     if (adev->class == ATA_DEV_ATA)
0092         control |= 4;   /* PPE */
0093
0094     pci_read_config_word(dev, idetm_port, &idetm_data);
0095
0096     /*
0097      * Set PPE, IE and TIME as appropriate.
0098      * Clear the other drive's timing bits.
0099      */
0100     if (adev->devno == 0) {
0101         idetm_data &= 0xCCE0;
0102         idetm_data |= control;
0103     } else {
0104         idetm_data &= 0xCC0E;
0105         idetm_data |= (control << 4);
0106     }
0107     idetm_data |= (timings[pio][0] << 12) |
0108             (timings[pio][1] << 8);
0109     pci_write_config_word(dev, idetm_port, idetm_data);
0110
0111     /* Track which port is configured */
0112     ap->private_data = adev;
0113 }
0114
0115 /**
0116  *  oldpiix_set_dmamode - Initialize host controller PATA DMA timings
0117  *  @ap: Port whose timings we are configuring
0118  *  @adev: Device to program
0119  *
0120  *  Set MWDMA mode for device, in host controller PCI config space.
0121  *
0122  *  LOCKING:
0123  *  None (inherited from caller).
0124  */
0125
0126 static void oldpiix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
0127 {
0128     struct pci_dev *dev = to_pci_dev(ap->host->dev);
0129     u8 idetm_port       = ap->port_no ? 0x42 : 0x40;
0130     u16 idetm_data;
0131
0132     static const     /* ISP  RTC */
0133     u8 timings[][2] = { { 0, 0 },
0134                 { 0, 0 },
0135                 { 1, 0 },
0136                 { 2, 1 },
0137                 { 2, 3 }, };
0138
0139     /*
0140      * MWDMA is driven by the PIO timings. We must also enable
0141      * IORDY unconditionally along with TIME1. PPE has already
0142      * been set when the PIO timing was set.
0143      */
0144
0145     unsigned int mwdma  = adev->dma_mode - XFER_MW_DMA_0;
0146     unsigned int control;
0147     const unsigned int needed_pio[3] = {
0148         XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
0149     };
0150     int pio = needed_pio[mwdma] - XFER_PIO_0;
0151
0152     pci_read_config_word(dev, idetm_port, &idetm_data);
0153
0154     control = 3;    /* IORDY|TIME0 */
0155     /* Intel specifies that the PPE functionality is for disk only */
0156     if (adev->class == ATA_DEV_ATA)
0157         control |= 4;   /* PPE enable */
0158
0159     /* If the drive MWDMA is faster than it can do PIO then
0160        we must force PIO into PIO0 */
0161
0162     if (adev->pio_mode < needed_pio[mwdma])
0163         /* Enable DMA timing only */
0164         control |= 8;   /* PIO cycles in PIO0 */
0165
0166     /* Mask out the relevant control and timing bits we will load. Also
0167        clear the other drive TIME register as a precaution */
0168     if (adev->devno == 0) {
0169         idetm_data &= 0xCCE0;
0170         idetm_data |= control;
0171     } else {
0172         idetm_data &= 0xCC0E;
0173         idetm_data |= (control << 4);
0174     }
0175     idetm_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
0176     pci_write_config_word(dev, idetm_port, idetm_data);
0177
0178     /* Track which port is configured */
0179     ap->private_data = adev;
0180 }
0181
0182 /**
0183  *  oldpiix_qc_issue    -   command issue
0184  *  @qc: command pending
0185  *
0186  *  Called when the libata layer is about to issue a command. We wrap
0187  *  this interface so that we can load the correct ATA timings if
0188  *  necessary. Our logic also clears TIME0/TIME1 for the other device so
0189  *  that, even if we get this wrong, cycles to the other device will
0190  *  be made PIO0.
0191  */
0192
0193 static unsigned int oldpiix_qc_issue(struct ata_queued_cmd *qc)
0194 {
0195     struct ata_port *ap = qc->ap;
0196     struct ata_device *adev = qc->dev;
0197
0198     if (adev != ap->private_data) {
0199         oldpiix_set_piomode(ap, adev);
0200         if (ata_dma_enabled(adev))
0201             oldpiix_set_dmamode(ap, adev);
0202     }
0203     return ata_bmdma_qc_issue(qc);
0204 }
0205
0206
0207 static struct scsi_host_template oldpiix_sht = {
0208     ATA_BMDMA_SHT(DRV_NAME),
0209 };
0210
0211 static struct ata_port_operations oldpiix_pata_ops = {
0212     .inherits       = &ata_bmdma_port_ops,
0213     .qc_issue       = oldpiix_qc_issue,
0214     .cable_detect       = ata_cable_40wire,
0215     .set_piomode        = oldpiix_set_piomode,
0216     .set_dmamode        = oldpiix_set_dmamode,
0217     .prereset       = oldpiix_pre_reset,
0218 };
0219
0220
0221 /**
0222  *  oldpiix_init_one - Register PIIX ATA PCI device with kernel services
0223  *  @pdev: PCI device to register
0224  *  @ent: Entry in oldpiix_pci_tbl matching with @pdev
0225  *
0226  *  Called from kernel PCI layer.  We probe for combined mode (sigh),
0227  *  and then hand over control to libata, for it to do the rest.
0228  *
0229  *  LOCKING:
0230  *  Inherited from PCI layer (may sleep).
0231  *
0232  *  RETURNS:
0233  *  Zero on success, or -ERRNO value.
0234  */
0235
0236 static int oldpiix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
0237 {
0238     static const struct ata_port_info info = {
0239         .flags      = ATA_FLAG_SLAVE_POSS,
0240         .pio_mask   = ATA_PIO4,
0241         .mwdma_mask = ATA_MWDMA12_ONLY,
0242         .port_ops   = &oldpiix_pata_ops,
0243     };
0244     const struct ata_port_info *ppi[] = { &info, NULL };
0245
0246     ata_print_version_once(&pdev->dev, DRV_VERSION);
0247
0248     return ata_pci_bmdma_init_one(pdev, ppi, &oldpiix_sht, NULL, 0);
0249 }
0250
0251 static const struct pci_device_id oldpiix_pci_tbl[] = {
0252     { PCI_VDEVICE(INTEL, 0x1230), },
0253
0254     { } /* terminate list */
0255 };
0256
0257 static struct pci_driver oldpiix_pci_driver = {
0258     .name           = DRV_NAME,
0259     .id_table       = oldpiix_pci_tbl,
0260     .probe          = oldpiix_init_one,
0261     .remove         = ata_pci_remove_one,
0262 #ifdef CONFIG_PM_SLEEP
0263     .suspend        = ata_pci_device_suspend,
0264     .resume         = ata_pci_device_resume,
0265 #endif
0266 };
0267
0268 module_pci_driver(oldpiix_pci_driver);
0269
0270 MODULE_AUTHOR("Alan Cox");
0271 MODULE_DESCRIPTION("SCSI low-level driver for early PIIX series controllers");
0272 MODULE_LICENSE("GPL");
0273 MODULE_DEVICE_TABLE(pci, oldpiix_pci_tbl);
0274 MODULE_VERSION(DRV_VERSION);