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0001 /*
0002  * Driver for the Octeon bootbus compact flash.
0003  *
0004  * This file is subject to the terms and conditions of the GNU General Public
0005  * License.  See the file "COPYING" in the main directory of this archive
0006  * for more details.
0007  *
0008  * Copyright (C) 2005 - 2012 Cavium Inc.
0009  * Copyright (C) 2008 Wind River Systems
0010  */
0011 
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/libata.h>
0015 #include <linux/hrtimer.h>
0016 #include <linux/slab.h>
0017 #include <linux/irq.h>
0018 #include <linux/of.h>
0019 #include <linux/of_platform.h>
0020 #include <linux/platform_device.h>
0021 #include <scsi/scsi_host.h>
0022 #include <trace/events/libata.h>
0023 #include <asm/byteorder.h>
0024 #include <asm/octeon/octeon.h>
0025 
0026 /*
0027  * The Octeon bootbus compact flash interface is connected in at least
0028  * 3 different configurations on various evaluation boards:
0029  *
0030  * -- 8  bits no irq, no DMA
0031  * -- 16 bits no irq, no DMA
0032  * -- 16 bits True IDE mode with DMA, but no irq.
0033  *
0034  * In the last case the DMA engine can generate an interrupt when the
0035  * transfer is complete.  For the first two cases only PIO is supported.
0036  *
0037  */
0038 
0039 #define DRV_NAME    "pata_octeon_cf"
0040 #define DRV_VERSION "2.2"
0041 
0042 /* Poll interval in nS. */
0043 #define OCTEON_CF_BUSY_POLL_INTERVAL 500000
0044 
0045 #define DMA_CFG 0
0046 #define DMA_TIM 0x20
0047 #define DMA_INT 0x38
0048 #define DMA_INT_EN 0x50
0049 
0050 struct octeon_cf_port {
0051     struct hrtimer delayed_finish;
0052     struct ata_port *ap;
0053     int dma_finished;
0054     void        *c0;
0055     unsigned int cs0;
0056     unsigned int cs1;
0057     bool is_true_ide;
0058     u64 dma_base;
0059 };
0060 
0061 static struct scsi_host_template octeon_cf_sht = {
0062     ATA_PIO_SHT(DRV_NAME),
0063 };
0064 
0065 static int enable_dma;
0066 module_param(enable_dma, int, 0444);
0067 MODULE_PARM_DESC(enable_dma,
0068          "Enable use of DMA on interfaces that support it (0=no dma [default], 1=use dma)");
0069 
0070 /**
0071  * Convert nanosecond based time to setting used in the
0072  * boot bus timing register, based on timing multiple
0073  */
0074 static unsigned int ns_to_tim_reg(unsigned int tim_mult, unsigned int nsecs)
0075 {
0076     /*
0077      * Compute # of eclock periods to get desired duration in
0078      * nanoseconds.
0079      */
0080     return DIV_ROUND_UP(nsecs * (octeon_get_io_clock_rate() / 1000000),
0081               1000 * tim_mult);
0082 }
0083 
0084 static void octeon_cf_set_boot_reg_cfg(int cs, unsigned int multiplier)
0085 {
0086     union cvmx_mio_boot_reg_cfgx reg_cfg;
0087     unsigned int tim_mult;
0088 
0089     switch (multiplier) {
0090     case 8:
0091         tim_mult = 3;
0092         break;
0093     case 4:
0094         tim_mult = 0;
0095         break;
0096     case 2:
0097         tim_mult = 2;
0098         break;
0099     default:
0100         tim_mult = 1;
0101         break;
0102     }
0103 
0104     reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
0105     reg_cfg.s.dmack = 0;    /* Don't assert DMACK on access */
0106     reg_cfg.s.tim_mult = tim_mult;  /* Timing mutiplier */
0107     reg_cfg.s.rd_dly = 0;   /* Sample on falling edge of BOOT_OE */
0108     reg_cfg.s.sam = 0;  /* Don't combine write and output enable */
0109     reg_cfg.s.we_ext = 0;   /* No write enable extension */
0110     reg_cfg.s.oe_ext = 0;   /* No read enable extension */
0111     reg_cfg.s.en = 1;   /* Enable this region */
0112     reg_cfg.s.orbit = 0;    /* Don't combine with previous region */
0113     reg_cfg.s.ale = 0;  /* Don't do address multiplexing */
0114     cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), reg_cfg.u64);
0115 }
0116 
0117 /**
0118  * Called after libata determines the needed PIO mode. This
0119  * function programs the Octeon bootbus regions to support the
0120  * timing requirements of the PIO mode.
0121  *
0122  * @ap:     ATA port information
0123  * @dev:    ATA device
0124  */
0125 static void octeon_cf_set_piomode(struct ata_port *ap, struct ata_device *dev)
0126 {
0127     struct octeon_cf_port *cf_port = ap->private_data;
0128     union cvmx_mio_boot_reg_timx reg_tim;
0129     int T;
0130     struct ata_timing timing;
0131 
0132     unsigned int div;
0133     int use_iordy;
0134     int trh;
0135     int pause;
0136     /* These names are timing parameters from the ATA spec */
0137     int t2;
0138 
0139     /*
0140      * A divisor value of four will overflow the timing fields at
0141      * clock rates greater than 800MHz
0142      */
0143     if (octeon_get_io_clock_rate() <= 800000000)
0144         div = 4;
0145     else
0146         div = 8;
0147     T = (int)((1000000000000LL * div) / octeon_get_io_clock_rate());
0148 
0149     BUG_ON(ata_timing_compute(dev, dev->pio_mode, &timing, T, T));
0150 
0151     t2 = timing.active;
0152     if (t2)
0153         t2--;
0154 
0155     trh = ns_to_tim_reg(div, 20);
0156     if (trh)
0157         trh--;
0158 
0159     pause = (int)timing.cycle - (int)timing.active -
0160         (int)timing.setup - trh;
0161     if (pause < 0)
0162         pause = 0;
0163     if (pause)
0164         pause--;
0165 
0166     octeon_cf_set_boot_reg_cfg(cf_port->cs0, div);
0167     if (cf_port->is_true_ide)
0168         /* True IDE mode, program both chip selects.  */
0169         octeon_cf_set_boot_reg_cfg(cf_port->cs1, div);
0170 
0171 
0172     use_iordy = ata_pio_need_iordy(dev);
0173 
0174     reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0));
0175     /* Disable page mode */
0176     reg_tim.s.pagem = 0;
0177     /* Enable dynamic timing */
0178     reg_tim.s.waitm = use_iordy;
0179     /* Pages are disabled */
0180     reg_tim.s.pages = 0;
0181     /* We don't use multiplexed address mode */
0182     reg_tim.s.ale = 0;
0183     /* Not used */
0184     reg_tim.s.page = 0;
0185     /* Time after IORDY to coninue to assert the data */
0186     reg_tim.s.wait = 0;
0187     /* Time to wait to complete the cycle. */
0188     reg_tim.s.pause = pause;
0189     /* How long to hold after a write to de-assert CE. */
0190     reg_tim.s.wr_hld = trh;
0191     /* How long to wait after a read to de-assert CE. */
0192     reg_tim.s.rd_hld = trh;
0193     /* How long write enable is asserted */
0194     reg_tim.s.we = t2;
0195     /* How long read enable is asserted */
0196     reg_tim.s.oe = t2;
0197     /* Time after CE that read/write starts */
0198     reg_tim.s.ce = ns_to_tim_reg(div, 5);
0199     /* Time before CE that address is valid */
0200     reg_tim.s.adr = 0;
0201 
0202     /* Program the bootbus region timing for the data port chip select. */
0203     cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0), reg_tim.u64);
0204     if (cf_port->is_true_ide)
0205         /* True IDE mode, program both chip selects.  */
0206         cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs1),
0207                    reg_tim.u64);
0208 }
0209 
0210 static void octeon_cf_set_dmamode(struct ata_port *ap, struct ata_device *dev)
0211 {
0212     struct octeon_cf_port *cf_port = ap->private_data;
0213     union cvmx_mio_boot_pin_defs pin_defs;
0214     union cvmx_mio_boot_dma_timx dma_tim;
0215     unsigned int oe_a;
0216     unsigned int oe_n;
0217     unsigned int dma_ackh;
0218     unsigned int dma_arq;
0219     unsigned int pause;
0220     unsigned int T0, Tkr, Td;
0221     unsigned int tim_mult;
0222     int c;
0223 
0224     const struct ata_timing *timing;
0225 
0226     timing = ata_timing_find_mode(dev->dma_mode);
0227     T0  = timing->cycle;
0228     Td  = timing->active;
0229     Tkr = timing->recover;
0230     dma_ackh = timing->dmack_hold;
0231 
0232     dma_tim.u64 = 0;
0233     /* dma_tim.s.tim_mult = 0 --> 4x */
0234     tim_mult = 4;
0235 
0236     /* not spec'ed, value in eclocks, not affected by tim_mult */
0237     dma_arq = 8;
0238     pause = 25 - dma_arq * 1000 /
0239         (octeon_get_io_clock_rate() / 1000000); /* Tz */
0240 
0241     oe_a = Td;
0242     /* Tkr from cf spec, lengthened to meet T0 */
0243     oe_n = max(T0 - oe_a, Tkr);
0244 
0245     pin_defs.u64 = cvmx_read_csr(CVMX_MIO_BOOT_PIN_DEFS);
0246 
0247     /* DMA channel number. */
0248     c = (cf_port->dma_base & 8) >> 3;
0249 
0250     /* Invert the polarity if the default is 0*/
0251     dma_tim.s.dmack_pi = (pin_defs.u64 & (1ull << (11 + c))) ? 0 : 1;
0252 
0253     dma_tim.s.oe_n = ns_to_tim_reg(tim_mult, oe_n);
0254     dma_tim.s.oe_a = ns_to_tim_reg(tim_mult, oe_a);
0255 
0256     /*
0257      * This is tI, C.F. spec. says 0, but Sony CF card requires
0258      * more, we use 20 nS.
0259      */
0260     dma_tim.s.dmack_s = ns_to_tim_reg(tim_mult, 20);
0261     dma_tim.s.dmack_h = ns_to_tim_reg(tim_mult, dma_ackh);
0262 
0263     dma_tim.s.dmarq = dma_arq;
0264     dma_tim.s.pause = ns_to_tim_reg(tim_mult, pause);
0265 
0266     dma_tim.s.rd_dly = 0;   /* Sample right on edge */
0267 
0268     /*  writes only */
0269     dma_tim.s.we_n = ns_to_tim_reg(tim_mult, oe_n);
0270     dma_tim.s.we_a = ns_to_tim_reg(tim_mult, oe_a);
0271 
0272     ata_dev_dbg(dev, "ns to ticks (mult %d) of %d is: %d\n", tim_mult, 60,
0273          ns_to_tim_reg(tim_mult, 60));
0274     ata_dev_dbg(dev, "oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: %d, dmarq: %d, pause: %d\n",
0275          dma_tim.s.oe_n, dma_tim.s.oe_a, dma_tim.s.dmack_s,
0276          dma_tim.s.dmack_h, dma_tim.s.dmarq, dma_tim.s.pause);
0277 
0278     cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64);
0279 }
0280 
0281 /**
0282  * Handle an 8 bit I/O request.
0283  *
0284  * @qc:         Queued command
0285  * @buffer:     Data buffer
0286  * @buflen:     Length of the buffer.
0287  * @rw:         True to write.
0288  */
0289 static unsigned int octeon_cf_data_xfer8(struct ata_queued_cmd *qc,
0290                      unsigned char *buffer,
0291                      unsigned int buflen,
0292                      int rw)
0293 {
0294     struct ata_port *ap     = qc->dev->link->ap;
0295     void __iomem *data_addr     = ap->ioaddr.data_addr;
0296     unsigned long words;
0297     int count;
0298 
0299     words = buflen;
0300     if (rw) {
0301         count = 16;
0302         while (words--) {
0303             iowrite8(*buffer, data_addr);
0304             buffer++;
0305             /*
0306              * Every 16 writes do a read so the bootbus
0307              * FIFO doesn't fill up.
0308              */
0309             if (--count == 0) {
0310                 ioread8(ap->ioaddr.altstatus_addr);
0311                 count = 16;
0312             }
0313         }
0314     } else {
0315         ioread8_rep(data_addr, buffer, words);
0316     }
0317     return buflen;
0318 }
0319 
0320 /**
0321  * Handle a 16 bit I/O request.
0322  *
0323  * @qc:         Queued command
0324  * @buffer:     Data buffer
0325  * @buflen:     Length of the buffer.
0326  * @rw:         True to write.
0327  */
0328 static unsigned int octeon_cf_data_xfer16(struct ata_queued_cmd *qc,
0329                       unsigned char *buffer,
0330                       unsigned int buflen,
0331                       int rw)
0332 {
0333     struct ata_port *ap     = qc->dev->link->ap;
0334     void __iomem *data_addr     = ap->ioaddr.data_addr;
0335     unsigned long words;
0336     int count;
0337 
0338     words = buflen / 2;
0339     if (rw) {
0340         count = 16;
0341         while (words--) {
0342             iowrite16(*(uint16_t *)buffer, data_addr);
0343             buffer += sizeof(uint16_t);
0344             /*
0345              * Every 16 writes do a read so the bootbus
0346              * FIFO doesn't fill up.
0347              */
0348             if (--count == 0) {
0349                 ioread8(ap->ioaddr.altstatus_addr);
0350                 count = 16;
0351             }
0352         }
0353     } else {
0354         while (words--) {
0355             *(uint16_t *)buffer = ioread16(data_addr);
0356             buffer += sizeof(uint16_t);
0357         }
0358     }
0359     /* Transfer trailing 1 byte, if any. */
0360     if (unlikely(buflen & 0x01)) {
0361         __le16 align_buf[1] = { 0 };
0362 
0363         if (rw == READ) {
0364             align_buf[0] = cpu_to_le16(ioread16(data_addr));
0365             memcpy(buffer, align_buf, 1);
0366         } else {
0367             memcpy(align_buf, buffer, 1);
0368             iowrite16(le16_to_cpu(align_buf[0]), data_addr);
0369         }
0370         words++;
0371     }
0372     return buflen;
0373 }
0374 
0375 /**
0376  * Read the taskfile for 16bit non-True IDE only.
0377  */
0378 static void octeon_cf_tf_read16(struct ata_port *ap, struct ata_taskfile *tf)
0379 {
0380     u16 blob;
0381     /* The base of the registers is at ioaddr.data_addr. */
0382     void __iomem *base = ap->ioaddr.data_addr;
0383 
0384     blob = __raw_readw(base + 0xc);
0385     tf->error = blob >> 8;
0386 
0387     blob = __raw_readw(base + 2);
0388     tf->nsect = blob & 0xff;
0389     tf->lbal = blob >> 8;
0390 
0391     blob = __raw_readw(base + 4);
0392     tf->lbam = blob & 0xff;
0393     tf->lbah = blob >> 8;
0394 
0395     blob = __raw_readw(base + 6);
0396     tf->device = blob & 0xff;
0397     tf->status = blob >> 8;
0398 
0399     if (tf->flags & ATA_TFLAG_LBA48) {
0400         if (likely(ap->ioaddr.ctl_addr)) {
0401             iowrite8(tf->ctl | ATA_HOB, ap->ioaddr.ctl_addr);
0402 
0403             blob = __raw_readw(base + 0xc);
0404             tf->hob_feature = blob >> 8;
0405 
0406             blob = __raw_readw(base + 2);
0407             tf->hob_nsect = blob & 0xff;
0408             tf->hob_lbal = blob >> 8;
0409 
0410             blob = __raw_readw(base + 4);
0411             tf->hob_lbam = blob & 0xff;
0412             tf->hob_lbah = blob >> 8;
0413 
0414             iowrite8(tf->ctl, ap->ioaddr.ctl_addr);
0415             ap->last_ctl = tf->ctl;
0416         } else {
0417             WARN_ON(1);
0418         }
0419     }
0420 }
0421 
0422 static u8 octeon_cf_check_status16(struct ata_port *ap)
0423 {
0424     u16 blob;
0425     void __iomem *base = ap->ioaddr.data_addr;
0426 
0427     blob = __raw_readw(base + 6);
0428     return blob >> 8;
0429 }
0430 
0431 static int octeon_cf_softreset16(struct ata_link *link, unsigned int *classes,
0432                  unsigned long deadline)
0433 {
0434     struct ata_port *ap = link->ap;
0435     void __iomem *base = ap->ioaddr.data_addr;
0436     int rc;
0437     u8 err;
0438 
0439     __raw_writew(ap->ctl, base + 0xe);
0440     udelay(20);
0441     __raw_writew(ap->ctl | ATA_SRST, base + 0xe);
0442     udelay(20);
0443     __raw_writew(ap->ctl, base + 0xe);
0444 
0445     rc = ata_sff_wait_after_reset(link, 1, deadline);
0446     if (rc) {
0447         ata_link_err(link, "SRST failed (errno=%d)\n", rc);
0448         return rc;
0449     }
0450 
0451     /* determine by signature whether we have ATA or ATAPI devices */
0452     classes[0] = ata_sff_dev_classify(&link->device[0], 1, &err);
0453     return 0;
0454 }
0455 
0456 /**
0457  * Load the taskfile for 16bit non-True IDE only.  The device_addr is
0458  * not loaded, we do this as part of octeon_cf_exec_command16.
0459  */
0460 static void octeon_cf_tf_load16(struct ata_port *ap,
0461                 const struct ata_taskfile *tf)
0462 {
0463     unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
0464     /* The base of the registers is at ioaddr.data_addr. */
0465     void __iomem *base = ap->ioaddr.data_addr;
0466 
0467     if (tf->ctl != ap->last_ctl) {
0468         iowrite8(tf->ctl, ap->ioaddr.ctl_addr);
0469         ap->last_ctl = tf->ctl;
0470         ata_wait_idle(ap);
0471     }
0472     if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
0473         __raw_writew(tf->hob_feature << 8, base + 0xc);
0474         __raw_writew(tf->hob_nsect | tf->hob_lbal << 8, base + 2);
0475         __raw_writew(tf->hob_lbam | tf->hob_lbah << 8, base + 4);
0476     }
0477     if (is_addr) {
0478         __raw_writew(tf->feature << 8, base + 0xc);
0479         __raw_writew(tf->nsect | tf->lbal << 8, base + 2);
0480         __raw_writew(tf->lbam | tf->lbah << 8, base + 4);
0481     }
0482     ata_wait_idle(ap);
0483 }
0484 
0485 
0486 static void octeon_cf_dev_select(struct ata_port *ap, unsigned int device)
0487 {
0488 /*  There is only one device, do nothing. */
0489     return;
0490 }
0491 
0492 /*
0493  * Issue ATA command to host controller.  The device_addr is also sent
0494  * as it must be written in a combined write with the command.
0495  */
0496 static void octeon_cf_exec_command16(struct ata_port *ap,
0497                 const struct ata_taskfile *tf)
0498 {
0499     /* The base of the registers is at ioaddr.data_addr. */
0500     void __iomem *base = ap->ioaddr.data_addr;
0501     u16 blob = 0;
0502 
0503     if (tf->flags & ATA_TFLAG_DEVICE)
0504         blob = tf->device;
0505 
0506     blob |= (tf->command << 8);
0507     __raw_writew(blob, base + 6);
0508 
0509     ata_wait_idle(ap);
0510 }
0511 
0512 static void octeon_cf_ata_port_noaction(struct ata_port *ap)
0513 {
0514 }
0515 
0516 static void octeon_cf_dma_setup(struct ata_queued_cmd *qc)
0517 {
0518     struct ata_port *ap = qc->ap;
0519     struct octeon_cf_port *cf_port;
0520 
0521     cf_port = ap->private_data;
0522     /* issue r/w command */
0523     qc->cursg = qc->sg;
0524     cf_port->dma_finished = 0;
0525     ap->ops->sff_exec_command(ap, &qc->tf);
0526 }
0527 
0528 /**
0529  * Start a DMA transfer that was already setup
0530  *
0531  * @qc:     Information about the DMA
0532  */
0533 static void octeon_cf_dma_start(struct ata_queued_cmd *qc)
0534 {
0535     struct octeon_cf_port *cf_port = qc->ap->private_data;
0536     union cvmx_mio_boot_dma_cfgx mio_boot_dma_cfg;
0537     union cvmx_mio_boot_dma_intx mio_boot_dma_int;
0538     struct scatterlist *sg;
0539 
0540     /* Get the scatter list entry we need to DMA into */
0541     sg = qc->cursg;
0542     BUG_ON(!sg);
0543 
0544     /*
0545      * Clear the DMA complete status.
0546      */
0547     mio_boot_dma_int.u64 = 0;
0548     mio_boot_dma_int.s.done = 1;
0549     cvmx_write_csr(cf_port->dma_base + DMA_INT, mio_boot_dma_int.u64);
0550 
0551     /* Enable the interrupt.  */
0552     cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, mio_boot_dma_int.u64);
0553 
0554     /* Set the direction of the DMA */
0555     mio_boot_dma_cfg.u64 = 0;
0556 #ifdef __LITTLE_ENDIAN
0557     mio_boot_dma_cfg.s.endian = 1;
0558 #endif
0559     mio_boot_dma_cfg.s.en = 1;
0560     mio_boot_dma_cfg.s.rw = ((qc->tf.flags & ATA_TFLAG_WRITE) != 0);
0561 
0562     /*
0563      * Don't stop the DMA if the device deasserts DMARQ. Many
0564      * compact flashes deassert DMARQ for a short time between
0565      * sectors. Instead of stopping and restarting the DMA, we'll
0566      * let the hardware do it. If the DMA is really stopped early
0567      * due to an error condition, a later timeout will force us to
0568      * stop.
0569      */
0570     mio_boot_dma_cfg.s.clr = 0;
0571 
0572     /* Size is specified in 16bit words and minus one notation */
0573     mio_boot_dma_cfg.s.size = sg_dma_len(sg) / 2 - 1;
0574 
0575     /* We need to swap the high and low bytes of every 16 bits */
0576     mio_boot_dma_cfg.s.swap8 = 1;
0577 
0578     mio_boot_dma_cfg.s.adr = sg_dma_address(sg);
0579 
0580     cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64);
0581 }
0582 
0583 /**
0584  *
0585  *  LOCKING:
0586  *  spin_lock_irqsave(host lock)
0587  *
0588  */
0589 static unsigned int octeon_cf_dma_finished(struct ata_port *ap,
0590                     struct ata_queued_cmd *qc)
0591 {
0592     struct ata_eh_info *ehi = &ap->link.eh_info;
0593     struct octeon_cf_port *cf_port = ap->private_data;
0594     union cvmx_mio_boot_dma_cfgx dma_cfg;
0595     union cvmx_mio_boot_dma_intx dma_int;
0596     u8 status;
0597 
0598     trace_ata_bmdma_stop(ap, &qc->tf, qc->tag);
0599 
0600     if (ap->hsm_task_state != HSM_ST_LAST)
0601         return 0;
0602 
0603     dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
0604     if (dma_cfg.s.size != 0xfffff) {
0605         /* Error, the transfer was not complete.  */
0606         qc->err_mask |= AC_ERR_HOST_BUS;
0607         ap->hsm_task_state = HSM_ST_ERR;
0608     }
0609 
0610     /* Stop and clear the dma engine.  */
0611     dma_cfg.u64 = 0;
0612     dma_cfg.s.size = -1;
0613     cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
0614 
0615     /* Disable the interrupt.  */
0616     dma_int.u64 = 0;
0617     cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
0618 
0619     /* Clear the DMA complete status */
0620     dma_int.s.done = 1;
0621     cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
0622 
0623     status = ap->ops->sff_check_status(ap);
0624 
0625     ata_sff_hsm_move(ap, qc, status, 0);
0626 
0627     if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA))
0628         ata_ehi_push_desc(ehi, "DMA stat 0x%x", status);
0629 
0630     return 1;
0631 }
0632 
0633 /*
0634  * Check if any queued commands have more DMAs, if so start the next
0635  * transfer, else do end of transfer handling.
0636  */
0637 static irqreturn_t octeon_cf_interrupt(int irq, void *dev_instance)
0638 {
0639     struct ata_host *host = dev_instance;
0640     struct octeon_cf_port *cf_port;
0641     int i;
0642     unsigned int handled = 0;
0643     unsigned long flags;
0644 
0645     spin_lock_irqsave(&host->lock, flags);
0646 
0647     for (i = 0; i < host->n_ports; i++) {
0648         u8 status;
0649         struct ata_port *ap;
0650         struct ata_queued_cmd *qc;
0651         union cvmx_mio_boot_dma_intx dma_int;
0652         union cvmx_mio_boot_dma_cfgx dma_cfg;
0653 
0654         ap = host->ports[i];
0655         cf_port = ap->private_data;
0656 
0657         dma_int.u64 = cvmx_read_csr(cf_port->dma_base + DMA_INT);
0658         dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
0659 
0660         qc = ata_qc_from_tag(ap, ap->link.active_tag);
0661 
0662         if (!qc || (qc->tf.flags & ATA_TFLAG_POLLING))
0663             continue;
0664 
0665         if (dma_int.s.done && !dma_cfg.s.en) {
0666             if (!sg_is_last(qc->cursg)) {
0667                 qc->cursg = sg_next(qc->cursg);
0668                 handled = 1;
0669                 trace_ata_bmdma_start(ap, &qc->tf, qc->tag);
0670                 octeon_cf_dma_start(qc);
0671                 continue;
0672             } else {
0673                 cf_port->dma_finished = 1;
0674             }
0675         }
0676         if (!cf_port->dma_finished)
0677             continue;
0678         status = ioread8(ap->ioaddr.altstatus_addr);
0679         if (status & (ATA_BUSY | ATA_DRQ)) {
0680             /*
0681              * We are busy, try to handle it later.  This
0682              * is the DMA finished interrupt, and it could
0683              * take a little while for the card to be
0684              * ready for more commands.
0685              */
0686             /* Clear DMA irq. */
0687             dma_int.u64 = 0;
0688             dma_int.s.done = 1;
0689             cvmx_write_csr(cf_port->dma_base + DMA_INT,
0690                        dma_int.u64);
0691             hrtimer_start_range_ns(&cf_port->delayed_finish,
0692                            ns_to_ktime(OCTEON_CF_BUSY_POLL_INTERVAL),
0693                            OCTEON_CF_BUSY_POLL_INTERVAL / 5,
0694                            HRTIMER_MODE_REL);
0695             handled = 1;
0696         } else {
0697             handled |= octeon_cf_dma_finished(ap, qc);
0698         }
0699     }
0700     spin_unlock_irqrestore(&host->lock, flags);
0701     return IRQ_RETVAL(handled);
0702 }
0703 
0704 static enum hrtimer_restart octeon_cf_delayed_finish(struct hrtimer *hrt)
0705 {
0706     struct octeon_cf_port *cf_port = container_of(hrt,
0707                               struct octeon_cf_port,
0708                               delayed_finish);
0709     struct ata_port *ap = cf_port->ap;
0710     struct ata_host *host = ap->host;
0711     struct ata_queued_cmd *qc;
0712     unsigned long flags;
0713     u8 status;
0714     enum hrtimer_restart rv = HRTIMER_NORESTART;
0715 
0716     spin_lock_irqsave(&host->lock, flags);
0717 
0718     /*
0719      * If the port is not waiting for completion, it must have
0720      * handled it previously.  The hsm_task_state is
0721      * protected by host->lock.
0722      */
0723     if (ap->hsm_task_state != HSM_ST_LAST || !cf_port->dma_finished)
0724         goto out;
0725 
0726     status = ioread8(ap->ioaddr.altstatus_addr);
0727     if (status & (ATA_BUSY | ATA_DRQ)) {
0728         /* Still busy, try again. */
0729         hrtimer_forward_now(hrt,
0730                     ns_to_ktime(OCTEON_CF_BUSY_POLL_INTERVAL));
0731         rv = HRTIMER_RESTART;
0732         goto out;
0733     }
0734     qc = ata_qc_from_tag(ap, ap->link.active_tag);
0735     if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
0736         octeon_cf_dma_finished(ap, qc);
0737 out:
0738     spin_unlock_irqrestore(&host->lock, flags);
0739     return rv;
0740 }
0741 
0742 static void octeon_cf_dev_config(struct ata_device *dev)
0743 {
0744     /*
0745      * A maximum of 2^20 - 1 16 bit transfers are possible with
0746      * the bootbus DMA.  So we need to throttle max_sectors to
0747      * (2^12 - 1 == 4095) to assure that this can never happen.
0748      */
0749     dev->max_sectors = min(dev->max_sectors, 4095U);
0750 }
0751 
0752 /*
0753  * We don't do ATAPI DMA so return 0.
0754  */
0755 static int octeon_cf_check_atapi_dma(struct ata_queued_cmd *qc)
0756 {
0757     return 0;
0758 }
0759 
0760 static unsigned int octeon_cf_qc_issue(struct ata_queued_cmd *qc)
0761 {
0762     struct ata_port *ap = qc->ap;
0763 
0764     switch (qc->tf.protocol) {
0765     case ATA_PROT_DMA:
0766         WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING);
0767 
0768         trace_ata_tf_load(ap, &qc->tf);
0769         ap->ops->sff_tf_load(ap, &qc->tf);  /* load tf registers */
0770         trace_ata_bmdma_setup(ap, &qc->tf, qc->tag);
0771         octeon_cf_dma_setup(qc);        /* set up dma */
0772         trace_ata_bmdma_start(ap, &qc->tf, qc->tag);
0773         octeon_cf_dma_start(qc);        /* initiate dma */
0774         ap->hsm_task_state = HSM_ST_LAST;
0775         break;
0776 
0777     case ATAPI_PROT_DMA:
0778         dev_err(ap->dev, "Error, ATAPI not supported\n");
0779         BUG();
0780 
0781     default:
0782         return ata_sff_qc_issue(qc);
0783     }
0784 
0785     return 0;
0786 }
0787 
0788 static struct ata_port_operations octeon_cf_ops = {
0789     .inherits       = &ata_sff_port_ops,
0790     .check_atapi_dma    = octeon_cf_check_atapi_dma,
0791     .qc_prep        = ata_noop_qc_prep,
0792     .qc_issue       = octeon_cf_qc_issue,
0793     .sff_dev_select     = octeon_cf_dev_select,
0794     .sff_irq_on     = octeon_cf_ata_port_noaction,
0795     .sff_irq_clear      = octeon_cf_ata_port_noaction,
0796     .cable_detect       = ata_cable_40wire,
0797     .set_piomode        = octeon_cf_set_piomode,
0798     .set_dmamode        = octeon_cf_set_dmamode,
0799     .dev_config     = octeon_cf_dev_config,
0800 };
0801 
0802 static int octeon_cf_probe(struct platform_device *pdev)
0803 {
0804     struct resource *res_cs0, *res_cs1;
0805 
0806     bool is_16bit;
0807     const __be32 *cs_num;
0808     struct property *reg_prop;
0809     int n_addr, n_size, reg_len;
0810     struct device_node *node;
0811     void __iomem *cs0;
0812     void __iomem *cs1 = NULL;
0813     struct ata_host *host;
0814     struct ata_port *ap;
0815     int irq = 0;
0816     irq_handler_t irq_handler = NULL;
0817     void __iomem *base;
0818     struct octeon_cf_port *cf_port;
0819     int rv = -ENOMEM;
0820     u32 bus_width;
0821 
0822     node = pdev->dev.of_node;
0823     if (node == NULL)
0824         return -EINVAL;
0825 
0826     cf_port = devm_kzalloc(&pdev->dev, sizeof(*cf_port), GFP_KERNEL);
0827     if (!cf_port)
0828         return -ENOMEM;
0829 
0830     cf_port->is_true_ide = of_property_read_bool(node, "cavium,true-ide");
0831 
0832     if (of_property_read_u32(node, "cavium,bus-width", &bus_width) == 0)
0833         is_16bit = (bus_width == 16);
0834     else
0835         is_16bit = false;
0836 
0837     n_addr = of_n_addr_cells(node);
0838     n_size = of_n_size_cells(node);
0839 
0840     reg_prop = of_find_property(node, "reg", &reg_len);
0841     if (!reg_prop || reg_len < sizeof(__be32))
0842         return -EINVAL;
0843 
0844     cs_num = reg_prop->value;
0845     cf_port->cs0 = be32_to_cpup(cs_num);
0846 
0847     if (cf_port->is_true_ide) {
0848         struct device_node *dma_node;
0849         dma_node = of_parse_phandle(node,
0850                         "cavium,dma-engine-handle", 0);
0851         if (dma_node) {
0852             struct platform_device *dma_dev;
0853             dma_dev = of_find_device_by_node(dma_node);
0854             if (dma_dev) {
0855                 struct resource *res_dma;
0856                 int i;
0857                 res_dma = platform_get_resource(dma_dev, IORESOURCE_MEM, 0);
0858                 if (!res_dma) {
0859                     put_device(&dma_dev->dev);
0860                     of_node_put(dma_node);
0861                     return -EINVAL;
0862                 }
0863                 cf_port->dma_base = (u64)devm_ioremap(&pdev->dev, res_dma->start,
0864                                      resource_size(res_dma));
0865                 if (!cf_port->dma_base) {
0866                     put_device(&dma_dev->dev);
0867                     of_node_put(dma_node);
0868                     return -EINVAL;
0869                 }
0870 
0871                 i = platform_get_irq(dma_dev, 0);
0872                 if (i > 0) {
0873                     irq = i;
0874                     irq_handler = octeon_cf_interrupt;
0875                 }
0876                 put_device(&dma_dev->dev);
0877             }
0878             of_node_put(dma_node);
0879         }
0880         res_cs1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0881         if (!res_cs1)
0882             return -EINVAL;
0883 
0884         cs1 = devm_ioremap(&pdev->dev, res_cs1->start,
0885                        resource_size(res_cs1));
0886         if (!cs1)
0887             return rv;
0888 
0889         if (reg_len < (n_addr + n_size + 1) * sizeof(__be32))
0890             return -EINVAL;
0891 
0892         cs_num += n_addr + n_size;
0893         cf_port->cs1 = be32_to_cpup(cs_num);
0894     }
0895 
0896     res_cs0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0897     if (!res_cs0)
0898         return -EINVAL;
0899 
0900     cs0 = devm_ioremap(&pdev->dev, res_cs0->start,
0901                    resource_size(res_cs0));
0902     if (!cs0)
0903         return rv;
0904 
0905     /* allocate host */
0906     host = ata_host_alloc(&pdev->dev, 1);
0907     if (!host)
0908         return rv;
0909 
0910     ap = host->ports[0];
0911     ap->private_data = cf_port;
0912     pdev->dev.platform_data = cf_port;
0913     cf_port->ap = ap;
0914     ap->ops = &octeon_cf_ops;
0915     ap->pio_mask = ATA_PIO6;
0916     ap->flags |= ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING;
0917 
0918     if (!is_16bit) {
0919         base = cs0 + 0x800;
0920         ap->ioaddr.cmd_addr = base;
0921         ata_sff_std_ports(&ap->ioaddr);
0922 
0923         ap->ioaddr.altstatus_addr = base + 0xe;
0924         ap->ioaddr.ctl_addr = base + 0xe;
0925         octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer8;
0926     } else if (cf_port->is_true_ide) {
0927         base = cs0;
0928         ap->ioaddr.cmd_addr = base + (ATA_REG_CMD << 1) + 1;
0929         ap->ioaddr.data_addr    = base + (ATA_REG_DATA << 1);
0930         ap->ioaddr.error_addr   = base + (ATA_REG_ERR << 1) + 1;
0931         ap->ioaddr.feature_addr = base + (ATA_REG_FEATURE << 1) + 1;
0932         ap->ioaddr.nsect_addr   = base + (ATA_REG_NSECT << 1) + 1;
0933         ap->ioaddr.lbal_addr    = base + (ATA_REG_LBAL << 1) + 1;
0934         ap->ioaddr.lbam_addr    = base + (ATA_REG_LBAM << 1) + 1;
0935         ap->ioaddr.lbah_addr    = base + (ATA_REG_LBAH << 1) + 1;
0936         ap->ioaddr.device_addr  = base + (ATA_REG_DEVICE << 1) + 1;
0937         ap->ioaddr.status_addr  = base + (ATA_REG_STATUS << 1) + 1;
0938         ap->ioaddr.command_addr = base + (ATA_REG_CMD << 1) + 1;
0939         ap->ioaddr.altstatus_addr = cs1 + (6 << 1) + 1;
0940         ap->ioaddr.ctl_addr = cs1 + (6 << 1) + 1;
0941         octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16;
0942 
0943         ap->mwdma_mask  = enable_dma ? ATA_MWDMA4 : 0;
0944 
0945         /* True IDE mode needs a timer to poll for not-busy.  */
0946         hrtimer_init(&cf_port->delayed_finish, CLOCK_MONOTONIC,
0947                  HRTIMER_MODE_REL);
0948         cf_port->delayed_finish.function = octeon_cf_delayed_finish;
0949     } else {
0950         /* 16 bit but not True IDE */
0951         base = cs0 + 0x800;
0952         octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16;
0953         octeon_cf_ops.softreset     = octeon_cf_softreset16;
0954         octeon_cf_ops.sff_check_status  = octeon_cf_check_status16;
0955         octeon_cf_ops.sff_tf_read   = octeon_cf_tf_read16;
0956         octeon_cf_ops.sff_tf_load   = octeon_cf_tf_load16;
0957         octeon_cf_ops.sff_exec_command  = octeon_cf_exec_command16;
0958 
0959         ap->ioaddr.data_addr    = base + ATA_REG_DATA;
0960         ap->ioaddr.nsect_addr   = base + ATA_REG_NSECT;
0961         ap->ioaddr.lbal_addr    = base + ATA_REG_LBAL;
0962         ap->ioaddr.ctl_addr = base + 0xe;
0963         ap->ioaddr.altstatus_addr = base + 0xe;
0964     }
0965     cf_port->c0 = ap->ioaddr.ctl_addr;
0966 
0967     rv = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
0968     if (rv)
0969         return rv;
0970 
0971     ata_port_desc(ap, "cmd %p ctl %p", base, ap->ioaddr.ctl_addr);
0972 
0973     dev_info(&pdev->dev, "version " DRV_VERSION" %d bit%s.\n",
0974          is_16bit ? 16 : 8,
0975          cf_port->is_true_ide ? ", True IDE" : "");
0976 
0977     return ata_host_activate(host, irq, irq_handler,
0978                  IRQF_SHARED, &octeon_cf_sht);
0979 }
0980 
0981 static void octeon_cf_shutdown(struct device *dev)
0982 {
0983     union cvmx_mio_boot_dma_cfgx dma_cfg;
0984     union cvmx_mio_boot_dma_intx dma_int;
0985 
0986     struct octeon_cf_port *cf_port = dev_get_platdata(dev);
0987 
0988     if (cf_port->dma_base) {
0989         /* Stop and clear the dma engine.  */
0990         dma_cfg.u64 = 0;
0991         dma_cfg.s.size = -1;
0992         cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
0993 
0994         /* Disable the interrupt.  */
0995         dma_int.u64 = 0;
0996         cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
0997 
0998         /* Clear the DMA complete status */
0999         dma_int.s.done = 1;
1000         cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
1001 
1002         __raw_writeb(0, cf_port->c0);
1003         udelay(20);
1004         __raw_writeb(ATA_SRST, cf_port->c0);
1005         udelay(20);
1006         __raw_writeb(0, cf_port->c0);
1007         mdelay(100);
1008     }
1009 }
1010 
1011 static const struct of_device_id octeon_cf_match[] = {
1012     { .compatible = "cavium,ebt3000-compact-flash", },
1013     { /* sentinel */ }
1014 };
1015 MODULE_DEVICE_TABLE(of, octeon_cf_match);
1016 
1017 static struct platform_driver octeon_cf_driver = {
1018     .probe      = octeon_cf_probe,
1019     .driver     = {
1020         .name   = DRV_NAME,
1021         .of_match_table = octeon_cf_match,
1022         .shutdown = octeon_cf_shutdown
1023     },
1024 };
1025 
1026 static int __init octeon_cf_init(void)
1027 {
1028     return platform_driver_register(&octeon_cf_driver);
1029 }
1030 
1031 
1032 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
1033 MODULE_DESCRIPTION("low-level driver for Cavium OCTEON Compact Flash PATA");
1034 MODULE_LICENSE("GPL");
1035 MODULE_VERSION(DRV_VERSION);
1036 MODULE_ALIAS("platform:" DRV_NAME);
1037 
1038 module_init(octeon_cf_init);
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