drivers/ata/pata_ns87415.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *    pata_ns87415.c - NS87415 (and PARISC SUPERIO 87560) PATA
0004  *
0005  *  (C) 2005 Red Hat <alan@lxorguk.ukuu.org.uk>
0006  *
0007  *    This is a fairly generic MWDMA controller. It has some limitations
0008  *    as it requires timing reloads on PIO/DMA transitions but it is otherwise
0009  *    fairly well designed.
0010  *
0011  *    This driver assumes the firmware has left the chip in a valid ST506
0012  *    compliant state, either legacy IRQ 14/15 or native INTA shared. You
0013  *    may need to add platform code if your system fails to do this.
0014  *
0015  *    The same cell appears in the 87560 controller used by some PARISC
0016  *    systems. This has its own special mountain of errata.
0017  *
0018  *    TODO:
0019  *  Get someone to test on SPARC
0020  *  Implement lazy pio/dma switching for better performance
0021  *  8bit shared timing.
0022  *  See if we need to kill the FIFO for ATAPI
0023  */
0024
0025 #include <linux/kernel.h>
0026 #include <linux/module.h>
0027 #include <linux/pci.h>
0028 #include <linux/blkdev.h>
0029 #include <linux/delay.h>
0030 #include <linux/device.h>
0031 #include <scsi/scsi_host.h>
0032 #include <linux/libata.h>
0033 #include <linux/ata.h>
0034
0035 #define DRV_NAME    "pata_ns87415"
0036 #define DRV_VERSION "0.0.1"
0037
0038 /**
0039  *  ns87415_set_mode - Initialize host controller mode timings
0040  *  @ap: Port whose timings we are configuring
0041  *  @adev: Device whose timings we are configuring
0042  *  @mode: Mode to set
0043  *
0044  *  Program the mode registers for this controller, channel and
0045  *  device. Because the chip is quite an old design we have to do this
0046  *  for PIO/DMA switches.
0047  *
0048  *  LOCKING:
0049  *  None (inherited from caller).
0050  */
0051
0052 static void ns87415_set_mode(struct ata_port *ap, struct ata_device *adev, u8 mode)
0053 {
0054     struct pci_dev *dev = to_pci_dev(ap->host->dev);
0055     int unit        = 2 * ap->port_no + adev->devno;
0056     int timing      = 0x44 + 2 * unit;
0057     unsigned long T     = 1000000000 / 33333;   /* PCI clocks */
0058     struct ata_timing t;
0059     u16 clocking;
0060     u8 iordy;
0061     u8 status;
0062
0063     /* Timing register format is 17 - low nybble read timing with
0064        the high nybble being 16 - x for recovery time in PCI clocks */
0065
0066     ata_timing_compute(adev, adev->pio_mode, &t, T, 0);
0067
0068     clocking = 17 - clamp_val(t.active, 2, 17);
0069     clocking |= (16 - clamp_val(t.recover, 1, 16)) << 4;
0070     /* Use the same timing for read and write bytes */
0071     clocking |= (clocking << 8);
0072     pci_write_config_word(dev, timing, clocking);
0073
0074     /* Set the IORDY enable versus DMA enable on or off properly */
0075     pci_read_config_byte(dev, 0x42, &iordy);
0076     iordy &= ~(1 << (4 + unit));
0077     if (mode >= XFER_MW_DMA_0 || !ata_pio_need_iordy(adev))
0078         iordy |= (1 << (4 + unit));
0079
0080     /* Paranoia: We shouldn't ever get here with busy write buffers
0081        but if so wait */
0082
0083     pci_read_config_byte(dev, 0x43, &status);
0084     while (status & 0x03) {
0085         udelay(1);
0086         pci_read_config_byte(dev, 0x43, &status);
0087     }
0088     /* Flip the IORDY/DMA bits now we are sure the write buffers are
0089        clear */
0090     pci_write_config_byte(dev, 0x42, iordy);
0091
0092     /* TODO: Set byte 54 command timing to the best 8bit
0093        mode shared by all four devices */
0094 }
0095
0096 /**
0097  *  ns87415_set_piomode - Initialize host controller PATA PIO timings
0098  *  @ap: Port whose timings we are configuring
0099  *  @adev: Device to program
0100  *
0101  *  Set PIO mode for device, in host controller PCI config space.
0102  *
0103  *  LOCKING:
0104  *  None (inherited from caller).
0105  */
0106
0107 static void ns87415_set_piomode(struct ata_port *ap, struct ata_device *adev)
0108 {
0109     ns87415_set_mode(ap, adev, adev->pio_mode);
0110 }
0111
0112 /**
0113  *  ns87415_bmdma_setup     -   Set up DMA
0114  *  @qc: Command block
0115  *
0116  *  Set up for bus mastering DMA. We have to do this ourselves
0117  *  rather than use the helper due to a chip erratum
0118  */
0119
0120 static void ns87415_bmdma_setup(struct ata_queued_cmd *qc)
0121 {
0122     struct ata_port *ap = qc->ap;
0123     unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
0124     u8 dmactl;
0125
0126     /* load PRD table addr. */
0127     mb();   /* make sure PRD table writes are visible to controller */
0128     iowrite32(ap->bmdma_prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
0129
0130     /* specify data direction, triple-check start bit is clear */
0131     dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
0132     dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
0133     /* Due to an erratum we need to write these bits to the wrong
0134        place - which does save us an I/O bizarrely */
0135     dmactl |= ATA_DMA_INTR | ATA_DMA_ERR;
0136     if (!rw)
0137         dmactl |= ATA_DMA_WR;
0138     iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
0139     /* issue r/w command */
0140     ap->ops->sff_exec_command(ap, &qc->tf);
0141 }
0142
0143 /**
0144  *  ns87415_bmdma_start     -   Begin DMA transfer
0145  *  @qc: Command block
0146  *
0147  *  Switch the timings for the chip and set up for a DMA transfer
0148  *  before the DMA burst begins.
0149  *
0150  *  FIXME: We should do lazy switching on bmdma_start versus
0151  *  ata_pio_data_xfer for better performance.
0152  */
0153
0154 static void ns87415_bmdma_start(struct ata_queued_cmd *qc)
0155 {
0156     ns87415_set_mode(qc->ap, qc->dev, qc->dev->dma_mode);
0157     ata_bmdma_start(qc);
0158 }
0159
0160 /**
0161  *  ns87415_bmdma_stop      -   End DMA transfer
0162  *  @qc: Command block
0163  *
0164  *  End DMA mode and switch the controller back into PIO mode
0165  */
0166
0167 static void ns87415_bmdma_stop(struct ata_queued_cmd *qc)
0168 {
0169     ata_bmdma_stop(qc);
0170     ns87415_set_mode(qc->ap, qc->dev, qc->dev->pio_mode);
0171 }
0172
0173 /**
0174  *  ns87415_irq_clear       -   Clear interrupt
0175  *  @ap: Channel to clear
0176  *
0177  *  Erratum: Due to a chip bug registers 02 and 0A bit 1 and 2 (the
0178  *  error bits) are reset by writing to register 00 or 08.
0179  */
0180
0181 static void ns87415_irq_clear(struct ata_port *ap)
0182 {
0183     void __iomem *mmio = ap->ioaddr.bmdma_addr;
0184
0185     if (!mmio)
0186         return;
0187     iowrite8((ioread8(mmio + ATA_DMA_CMD) | ATA_DMA_INTR | ATA_DMA_ERR),
0188             mmio + ATA_DMA_CMD);
0189 }
0190
0191 /**
0192  *  ns87415_check_atapi_dma     -   ATAPI DMA filter
0193  *  @qc: Command block
0194  *
0195  *  Disable ATAPI DMA (for now). We may be able to do DMA if we
0196  *  kill the prefetching. This isn't clear.
0197  */
0198
0199 static int ns87415_check_atapi_dma(struct ata_queued_cmd *qc)
0200 {
0201     return -EOPNOTSUPP;
0202 }
0203
0204 #if defined(CONFIG_SUPERIO)
0205
0206 /* SUPERIO 87560 is a PoS chip that NatSem denies exists.
0207  * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
0208  * which use the integrated NS87514 cell for CD-ROM support.
0209  * i.e we have to support for CD-ROM installs.
0210  * See drivers/parisc/superio.c for more gory details.
0211  *
0212  * Workarounds taken from drivers/ide/pci/ns87415.c
0213  */
0214
0215 #include <asm/superio.h>
0216
0217 #define SUPERIO_IDE_MAX_RETRIES 25
0218
0219 /**
0220  *  ns87560_read_buggy  -   workaround buggy Super I/O chip
0221  *  @port: Port to read
0222  *
0223  *  Work around chipset problems in the 87560 SuperIO chip
0224  */
0225
0226 static u8 ns87560_read_buggy(void __iomem *port)
0227 {
0228     u8 tmp;
0229     int retries = SUPERIO_IDE_MAX_RETRIES;
0230     do {
0231         tmp = ioread8(port);
0232         if (tmp != 0)
0233             return tmp;
0234         udelay(50);
0235     } while(retries-- > 0);
0236     return tmp;
0237 }
0238
0239 /**
0240  *  ns87560_check_status
0241  *  @ap: channel to check
0242  *
0243  *  Return the status of the channel working around the
0244  *  87560 flaws.
0245  */
0246
0247 static u8 ns87560_check_status(struct ata_port *ap)
0248 {
0249     return ns87560_read_buggy(ap->ioaddr.status_addr);
0250 }
0251
0252 /**
0253  *  ns87560_tf_read - input device's ATA taskfile shadow registers
0254  *  @ap: Port from which input is read
0255  *  @tf: ATA taskfile register set for storing input
0256  *
0257  *  Reads ATA taskfile registers for currently-selected device
0258  *  into @tf. Work around the 87560 bugs.
0259  *
0260  *  LOCKING:
0261  *  Inherited from caller.
0262  */
0263 void ns87560_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
0264 {
0265     struct ata_ioports *ioaddr = &ap->ioaddr;
0266
0267     tf->status = ns87560_check_status(ap);
0268     tf->error = ioread8(ioaddr->error_addr);
0269     tf->nsect = ioread8(ioaddr->nsect_addr);
0270     tf->lbal = ioread8(ioaddr->lbal_addr);
0271     tf->lbam = ioread8(ioaddr->lbam_addr);
0272     tf->lbah = ioread8(ioaddr->lbah_addr);
0273     tf->device = ns87560_read_buggy(ioaddr->device_addr);
0274
0275     if (tf->flags & ATA_TFLAG_LBA48) {
0276         iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
0277         tf->hob_feature = ioread8(ioaddr->error_addr);
0278         tf->hob_nsect = ioread8(ioaddr->nsect_addr);
0279         tf->hob_lbal = ioread8(ioaddr->lbal_addr);
0280         tf->hob_lbam = ioread8(ioaddr->lbam_addr);
0281         tf->hob_lbah = ioread8(ioaddr->lbah_addr);
0282         iowrite8(tf->ctl, ioaddr->ctl_addr);
0283         ap->last_ctl = tf->ctl;
0284     }
0285 }
0286
0287 /**
0288  *  ns87560_bmdma_status
0289  *  @ap: channel to check
0290  *
0291  *  Return the DMA status of the channel working around the
0292  *  87560 flaws.
0293  */
0294
0295 static u8 ns87560_bmdma_status(struct ata_port *ap)
0296 {
0297     return ns87560_read_buggy(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
0298 }
0299 #endif      /* 87560 SuperIO Support */
0300
0301 static struct ata_port_operations ns87415_pata_ops = {
0302     .inherits       = &ata_bmdma_port_ops,
0303
0304     .check_atapi_dma    = ns87415_check_atapi_dma,
0305     .bmdma_setup        = ns87415_bmdma_setup,
0306     .bmdma_start        = ns87415_bmdma_start,
0307     .bmdma_stop     = ns87415_bmdma_stop,
0308     .sff_irq_clear      = ns87415_irq_clear,
0309
0310     .cable_detect       = ata_cable_40wire,
0311     .set_piomode        = ns87415_set_piomode,
0312 };
0313
0314 #if defined(CONFIG_SUPERIO)
0315 static struct ata_port_operations ns87560_pata_ops = {
0316     .inherits       = &ns87415_pata_ops,
0317     .sff_tf_read        = ns87560_tf_read,
0318     .sff_check_status   = ns87560_check_status,
0319     .bmdma_status       = ns87560_bmdma_status,
0320 };
0321 #endif
0322
0323 static struct scsi_host_template ns87415_sht = {
0324     ATA_BMDMA_SHT(DRV_NAME),
0325 };
0326
0327 static void ns87415_fixup(struct pci_dev *pdev)
0328 {
0329     /* Select 512 byte sectors */
0330     pci_write_config_byte(pdev, 0x55, 0xEE);
0331     /* Select PIO0 8bit clocking */
0332     pci_write_config_byte(pdev, 0x54, 0xB7);
0333 }
0334
0335 /**
0336  *  ns87415_init_one - Register 87415 ATA PCI device with kernel services
0337  *  @pdev: PCI device to register
0338  *  @ent: Entry in ns87415_pci_tbl matching with @pdev
0339  *
0340  *  Called from kernel PCI layer.  We probe for combined mode (sigh),
0341  *  and then hand over control to libata, for it to do the rest.
0342  *
0343  *  LOCKING:
0344  *  Inherited from PCI layer (may sleep).
0345  *
0346  *  RETURNS:
0347  *  Zero on success, or -ERRNO value.
0348  */
0349
0350 static int ns87415_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
0351 {
0352     static const struct ata_port_info info = {
0353         .flags      = ATA_FLAG_SLAVE_POSS,
0354         .pio_mask   = ATA_PIO4,
0355         .mwdma_mask = ATA_MWDMA2,
0356         .port_ops   = &ns87415_pata_ops,
0357     };
0358     const struct ata_port_info *ppi[] = { &info, NULL };
0359     int rc;
0360 #if defined(CONFIG_SUPERIO)
0361     static const struct ata_port_info info87560 = {
0362         .flags      = ATA_FLAG_SLAVE_POSS,
0363         .pio_mask   = ATA_PIO4,
0364         .mwdma_mask = ATA_MWDMA2,
0365         .port_ops   = &ns87560_pata_ops,
0366     };
0367
0368     if (PCI_SLOT(pdev->devfn) == 0x0E)
0369         ppi[0] = &info87560;
0370 #endif
0371     ata_print_version_once(&pdev->dev, DRV_VERSION);
0372
0373     rc = pcim_enable_device(pdev);
0374     if (rc)
0375         return rc;
0376
0377     ns87415_fixup(pdev);
0378
0379     return ata_pci_bmdma_init_one(pdev, ppi, &ns87415_sht, NULL, 0);
0380 }
0381
0382 static const struct pci_device_id ns87415_pci_tbl[] = {
0383     { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), },
0384
0385     { } /* terminate list */
0386 };
0387
0388 #ifdef CONFIG_PM_SLEEP
0389 static int ns87415_reinit_one(struct pci_dev *pdev)
0390 {
0391     struct ata_host *host = pci_get_drvdata(pdev);
0392     int rc;
0393
0394     rc = ata_pci_device_do_resume(pdev);
0395     if (rc)
0396         return rc;
0397
0398     ns87415_fixup(pdev);
0399
0400     ata_host_resume(host);
0401     return 0;
0402 }
0403 #endif
0404
0405 static struct pci_driver ns87415_pci_driver = {
0406     .name           = DRV_NAME,
0407     .id_table       = ns87415_pci_tbl,
0408     .probe          = ns87415_init_one,
0409     .remove         = ata_pci_remove_one,
0410 #ifdef CONFIG_PM_SLEEP
0411     .suspend        = ata_pci_device_suspend,
0412     .resume         = ns87415_reinit_one,
0413 #endif
0414 };
0415
0416 module_pci_driver(ns87415_pci_driver);
0417
0418 MODULE_AUTHOR("Alan Cox");
0419 MODULE_DESCRIPTION("ATA low-level driver for NS87415 controllers");
0420 MODULE_LICENSE("GPL");
0421 MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
0422 MODULE_VERSION(DRV_VERSION);