drivers/ata/pata_ninja32.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * pata_ninja32.c   - Ninja32 PATA for new ATA layer
0004  *            (C) 2007 Red Hat Inc
0005  *
0006  * Note: The controller like many controllers has shared timings for
0007  * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
0008  * in the dma_stop function. Thus we actually don't need a set_dmamode
0009  * method as the PIO method is always called and will set the right PIO
0010  * timing parameters.
0011  *
0012  * The Ninja32 Cardbus is not a generic SFF controller. Instead it is
0013  * laid out as follows off BAR 0. This is based upon Mark Lord's delkin
0014  * driver and the extensive analysis done by the BSD developers, notably
0015  * ITOH Yasufumi.
0016  *
0017  *  Base + 0x00 IRQ Status
0018  *  Base + 0x01 IRQ control
0019  *  Base + 0x02 Chipset control
0020  *  Base + 0x03 Unknown
0021  *  Base + 0x04 VDMA and reset control + wait bits
0022  *  Base + 0x08 BMIMBA
0023  *  Base + 0x0C DMA Length
0024  *  Base + 0x10 Taskfile
0025  *  Base + 0x18 BMDMA Status ?
0026  *  Base + 0x1C
0027  *  Base + 0x1D Bus master control
0028  *      bit 0 = enable
0029  *      bit 1 = 0 write/1 read
0030  *      bit 2 = 1 sgtable
0031  *      bit 3 = go
0032  *      bit 4-6 wait bits
0033  *      bit 7 = done
0034  *  Base + 0x1E AltStatus
0035  *  Base + 0x1F timing register
0036  */
0037
0038 #include <linux/kernel.h>
0039 #include <linux/module.h>
0040 #include <linux/pci.h>
0041 #include <linux/blkdev.h>
0042 #include <linux/delay.h>
0043 #include <scsi/scsi_host.h>
0044 #include <linux/libata.h>
0045
0046 #define DRV_NAME "pata_ninja32"
0047 #define DRV_VERSION "0.1.5"
0048
0049
0050 /**
0051  *  ninja32_set_piomode -   set initial PIO mode data
0052  *  @ap: ATA interface
0053  *  @adev: ATA device
0054  *
0055  *  Called to do the PIO mode setup. Our timing registers are shared
0056  *  but we want to set the PIO timing by default.
0057  */
0058
0059 static void ninja32_set_piomode(struct ata_port *ap, struct ata_device *adev)
0060 {
0061     static u16 pio_timing[5] = {
0062         0xd6, 0x85, 0x44, 0x33, 0x13
0063     };
0064     iowrite8(pio_timing[adev->pio_mode - XFER_PIO_0],
0065          ap->ioaddr.bmdma_addr + 0x1f);
0066     ap->private_data = adev;
0067 }
0068
0069
0070 static void ninja32_dev_select(struct ata_port *ap, unsigned int device)
0071 {
0072     struct ata_device *adev = &ap->link.device[device];
0073     if (ap->private_data != adev) {
0074         iowrite8(0xd6, ap->ioaddr.bmdma_addr + 0x1f);
0075         ata_sff_dev_select(ap, device);
0076         ninja32_set_piomode(ap, adev);
0077     }
0078 }
0079
0080 static struct scsi_host_template ninja32_sht = {
0081     ATA_BMDMA_SHT(DRV_NAME),
0082 };
0083
0084 static struct ata_port_operations ninja32_port_ops = {
0085     .inherits   = &ata_bmdma_port_ops,
0086     .sff_dev_select = ninja32_dev_select,
0087     .cable_detect   = ata_cable_40wire,
0088     .set_piomode    = ninja32_set_piomode,
0089     .sff_data_xfer  = ata_sff_data_xfer32
0090 };
0091
0092 static void ninja32_program(void __iomem *base)
0093 {
0094     iowrite8(0x05, base + 0x01);    /* Enable interrupt lines */
0095     iowrite8(0xBE, base + 0x02);    /* Burst, ?? setup */
0096     iowrite8(0x01, base + 0x03);    /* Unknown */
0097     iowrite8(0x20, base + 0x04);    /* WAIT0 */
0098     iowrite8(0x8f, base + 0x05);    /* Unknown */
0099     iowrite8(0xa4, base + 0x1c);    /* Unknown */
0100     iowrite8(0x83, base + 0x1d);    /* BMDMA control: WAIT0 */
0101 }
0102
0103 static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id)
0104 {
0105     struct ata_host *host;
0106     struct ata_port *ap;
0107     void __iomem *base;
0108     int rc;
0109
0110     host = ata_host_alloc(&dev->dev, 1);
0111     if (!host)
0112         return -ENOMEM;
0113     ap = host->ports[0];
0114
0115     /* Set up the PCI device */
0116     rc = pcim_enable_device(dev);
0117     if (rc)
0118         return rc;
0119     rc = pcim_iomap_regions(dev, 1 << 0, DRV_NAME);
0120     if (rc == -EBUSY)
0121         pcim_pin_device(dev);
0122     if (rc)
0123         return rc;
0124
0125     host->iomap = pcim_iomap_table(dev);
0126     rc = dma_set_mask_and_coherent(&dev->dev, ATA_DMA_MASK);
0127     if (rc)
0128         return rc;
0129     pci_set_master(dev);
0130
0131     /* Set up the register mappings. We use the I/O mapping as only the
0132        older chips also have MMIO on BAR 1 */
0133     base = host->iomap[0];
0134     if (!base)
0135         return -ENOMEM;
0136     ap->ops = &ninja32_port_ops;
0137     ap->pio_mask = ATA_PIO4;
0138     ap->flags |= ATA_FLAG_SLAVE_POSS;
0139
0140     ap->ioaddr.cmd_addr = base + 0x10;
0141     ap->ioaddr.ctl_addr = base + 0x1E;
0142     ap->ioaddr.altstatus_addr = base + 0x1E;
0143     ap->ioaddr.bmdma_addr = base;
0144     ata_sff_std_ports(&ap->ioaddr);
0145     ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
0146
0147     ninja32_program(base);
0148     /* FIXME: Should we disable them at remove ? */
0149     return ata_host_activate(host, dev->irq, ata_bmdma_interrupt,
0150                  IRQF_SHARED, &ninja32_sht);
0151 }
0152
0153 #ifdef CONFIG_PM_SLEEP
0154 static int ninja32_reinit_one(struct pci_dev *pdev)
0155 {
0156     struct ata_host *host = pci_get_drvdata(pdev);
0157     int rc;
0158
0159     rc = ata_pci_device_do_resume(pdev);
0160     if (rc)
0161         return rc;
0162     ninja32_program(host->iomap[0]);
0163     ata_host_resume(host);
0164     return 0;
0165 }
0166 #endif
0167
0168 static const struct pci_device_id ninja32[] = {
0169     { 0x10FC, 0x0003, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
0170     { 0x1145, 0x8008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
0171     { 0x1145, 0xf008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
0172     { 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
0173     { 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
0174     { 0x1145, 0xf02C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
0175     { },
0176 };
0177
0178 static struct pci_driver ninja32_pci_driver = {
0179     .name       = DRV_NAME,
0180     .id_table   = ninja32,
0181     .probe      = ninja32_init_one,
0182     .remove     = ata_pci_remove_one,
0183 #ifdef CONFIG_PM_SLEEP
0184     .suspend    = ata_pci_device_suspend,
0185     .resume     = ninja32_reinit_one,
0186 #endif
0187 };
0188
0189 module_pci_driver(ninja32_pci_driver);
0190
0191 MODULE_AUTHOR("Alan Cox");
0192 MODULE_DESCRIPTION("low-level driver for Ninja32 ATA");
0193 MODULE_LICENSE("GPL");
0194 MODULE_DEVICE_TABLE(pci, ninja32);
0195 MODULE_VERSION(DRV_VERSION);