drivers/ata/pata_mpiix.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * pata_mpiix.c     - Intel MPIIX PATA for new ATA layer
0004  *            (C) 2005-2006 Red Hat Inc
0005  *            Alan Cox <alan@lxorguk.ukuu.org.uk>
0006  *
0007  * The MPIIX is different enough to the PIIX4 and friends that we give it
0008  * a separate driver. The old ide/pci code handles this by just not tuning
0009  * MPIIX at all.
0010  *
0011  * The MPIIX also differs in another important way from the majority of PIIX
0012  * devices. The chip is a bridge (pardon the pun) between the old world of
0013  * ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual
0014  * IDE controller is not decoded in PCI space and the chip does not claim to
0015  * be IDE class PCI. This requires slightly non-standard probe logic compared
0016  * with PCI IDE and also that we do not disable the device when our driver is
0017  * unloaded (as it has many other functions).
0018  *
0019  * The driver consciously keeps this logic internally to avoid pushing quirky
0020  * PATA history into the clean libata layer.
0021  *
0022  * Thinkpad specific note: If you boot an MPIIX using a thinkpad with a PCMCIA
0023  * hard disk present this driver will not detect it. This is not a bug. In this
0024  * configuration the secondary port of the MPIIX is disabled and the addresses
0025  * are decoded by the PCMCIA bridge and therefore are for a generic IDE driver
0026  * to operate.
0027  */
0028
0029 #include <linux/kernel.h>
0030 #include <linux/module.h>
0031 #include <linux/pci.h>
0032 #include <linux/blkdev.h>
0033 #include <linux/delay.h>
0034 #include <scsi/scsi_host.h>
0035 #include <linux/libata.h>
0036
0037 #define DRV_NAME "pata_mpiix"
0038 #define DRV_VERSION "0.7.7"
0039
0040 enum {
0041     IDETIM = 0x6C,      /* IDE control register */
0042     IORDY = (1 << 1),
0043     PPE = (1 << 2),
0044     FTIM = (1 << 0),
0045     ENABLED = (1 << 15),
0046     SECONDARY = (1 << 14)
0047 };
0048
0049 static int mpiix_pre_reset(struct ata_link *link, unsigned long deadline)
0050 {
0051     struct ata_port *ap = link->ap;
0052     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0053     static const struct pci_bits mpiix_enable_bits = { 0x6D, 1, 0x80, 0x80 };
0054
0055     if (!pci_test_config_bits(pdev, &mpiix_enable_bits))
0056         return -ENOENT;
0057
0058     return ata_sff_prereset(link, deadline);
0059 }
0060
0061 /**
0062  *  mpiix_set_piomode   -   set initial PIO mode data
0063  *  @ap: ATA interface
0064  *  @adev: ATA device
0065  *
0066  *  Called to do the PIO mode setup. The MPIIX allows us to program the
0067  *  IORDY sample point (2-5 clocks), recovery (1-4 clocks) and whether
0068  *  prefetching or IORDY are used.
0069  *
0070  *  This would get very ugly because we can only program timing for one
0071  *  device at a time, the other gets PIO0. Fortunately libata calls
0072  *  our qc_issue command before a command is issued so we can flip the
0073  *  timings back and forth to reduce the pain.
0074  */
0075
0076 static void mpiix_set_piomode(struct ata_port *ap, struct ata_device *adev)
0077 {
0078     int control = 0;
0079     int pio = adev->pio_mode - XFER_PIO_0;
0080     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0081     u16 idetim;
0082     static const     /* ISP  RTC */
0083     u8 timings[][2] = { { 0, 0 },
0084                 { 0, 0 },
0085                 { 1, 0 },
0086                 { 2, 1 },
0087                 { 2, 3 }, };
0088
0089     pci_read_config_word(pdev, IDETIM, &idetim);
0090
0091     /* Mask the IORDY/TIME/PPE for this device */
0092     if (adev->class == ATA_DEV_ATA)
0093         control |= PPE;     /* Enable prefetch/posting for disk */
0094     if (ata_pio_need_iordy(adev))
0095         control |= IORDY;
0096     if (pio > 1)
0097         control |= FTIM;    /* This drive is on the fast timing bank */
0098
0099     /* Mask out timing and clear both TIME bank selects */
0100     idetim &= 0xCCEE;
0101     idetim &= ~(0x07  << (4 * adev->devno));
0102     idetim |= control << (4 * adev->devno);
0103
0104     idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
0105     pci_write_config_word(pdev, IDETIM, idetim);
0106
0107     /* We use ap->private_data as a pointer to the device currently
0108        loaded for timing */
0109     ap->private_data = adev;
0110 }
0111
0112 /**
0113  *  mpiix_qc_issue      -   command issue
0114  *  @qc: command pending
0115  *
0116  *  Called when the libata layer is about to issue a command. We wrap
0117  *  this interface so that we can load the correct ATA timings if
0118  *  necessary. Our logic also clears TIME0/TIME1 for the other device so
0119  *  that, even if we get this wrong, cycles to the other device will
0120  *  be made PIO0.
0121  */
0122
0123 static unsigned int mpiix_qc_issue(struct ata_queued_cmd *qc)
0124 {
0125     struct ata_port *ap = qc->ap;
0126     struct ata_device *adev = qc->dev;
0127
0128     /* If modes have been configured and the channel data is not loaded
0129        then load it. We have to check if pio_mode is set as the core code
0130        does not set adev->pio_mode to XFER_PIO_0 while probing as would be
0131        logical */
0132
0133     if (adev->pio_mode && adev != ap->private_data)
0134         mpiix_set_piomode(ap, adev);
0135
0136     return ata_sff_qc_issue(qc);
0137 }
0138
0139 static struct scsi_host_template mpiix_sht = {
0140     ATA_PIO_SHT(DRV_NAME),
0141 };
0142
0143 static struct ata_port_operations mpiix_port_ops = {
0144     .inherits   = &ata_sff_port_ops,
0145     .qc_issue   = mpiix_qc_issue,
0146     .cable_detect   = ata_cable_40wire,
0147     .set_piomode    = mpiix_set_piomode,
0148     .prereset   = mpiix_pre_reset,
0149     .sff_data_xfer  = ata_sff_data_xfer32,
0150 };
0151
0152 static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
0153 {
0154     /* Single threaded by the PCI probe logic */
0155     struct ata_host *host;
0156     struct ata_port *ap;
0157     void __iomem *cmd_addr, *ctl_addr;
0158     u16 idetim;
0159     int cmd, ctl, irq;
0160
0161     ata_print_version_once(&dev->dev, DRV_VERSION);
0162
0163     host = ata_host_alloc(&dev->dev, 1);
0164     if (!host)
0165         return -ENOMEM;
0166     ap = host->ports[0];
0167
0168     /* MPIIX has many functions which can be turned on or off according
0169        to other devices present. Make sure IDE is enabled before we try
0170        and use it */
0171
0172     pci_read_config_word(dev, IDETIM, &idetim);
0173     if (!(idetim & ENABLED))
0174         return -ENODEV;
0175
0176     /* See if it's primary or secondary channel... */
0177     if (!(idetim & SECONDARY)) {
0178         cmd = 0x1F0;
0179         ctl = 0x3F6;
0180         irq = 14;
0181     } else {
0182         cmd = 0x170;
0183         ctl = 0x376;
0184         irq = 15;
0185     }
0186
0187     cmd_addr = devm_ioport_map(&dev->dev, cmd, 8);
0188     ctl_addr = devm_ioport_map(&dev->dev, ctl, 1);
0189     if (!cmd_addr || !ctl_addr)
0190         return -ENOMEM;
0191
0192     ata_port_desc(ap, "cmd 0x%x ctl 0x%x", cmd, ctl);
0193
0194     /* We do our own plumbing to avoid leaking special cases for whacko
0195        ancient hardware into the core code. There are two issues to
0196        worry about.  #1 The chip is a bridge so if in legacy mode and
0197        without BARs set fools the setup.  #2 If you pci_disable_device
0198        the MPIIX your box goes castors up */
0199
0200     ap->ops = &mpiix_port_ops;
0201     ap->pio_mask = ATA_PIO4;
0202     ap->flags |= ATA_FLAG_SLAVE_POSS;
0203
0204     ap->ioaddr.cmd_addr = cmd_addr;
0205     ap->ioaddr.ctl_addr = ctl_addr;
0206     ap->ioaddr.altstatus_addr = ctl_addr;
0207
0208     /* Let libata fill in the port details */
0209     ata_sff_std_ports(&ap->ioaddr);
0210
0211     /* activate host */
0212     return ata_host_activate(host, irq, ata_sff_interrupt, IRQF_SHARED,
0213                  &mpiix_sht);
0214 }
0215
0216 static const struct pci_device_id mpiix[] = {
0217     { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), },
0218
0219     { },
0220 };
0221
0222 static struct pci_driver mpiix_pci_driver = {
0223     .name       = DRV_NAME,
0224     .id_table   = mpiix,
0225     .probe      = mpiix_init_one,
0226     .remove     = ata_pci_remove_one,
0227 #ifdef CONFIG_PM_SLEEP
0228     .suspend    = ata_pci_device_suspend,
0229     .resume     = ata_pci_device_resume,
0230 #endif
0231 };
0232
0233 module_pci_driver(mpiix_pci_driver);
0234
0235 MODULE_AUTHOR("Alan Cox");
0236 MODULE_DESCRIPTION("low-level driver for Intel MPIIX");
0237 MODULE_LICENSE("GPL");
0238 MODULE_DEVICE_TABLE(pci, mpiix);
0239 MODULE_VERSION(DRV_VERSION);