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0001 /*
0002  * drivers/ata/pata_mpc52xx.c
0003  *
0004  * libata driver for the Freescale MPC52xx on-chip IDE interface
0005  *
0006  * Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com>
0007  * Copyright (C) 2003 Mipsys - Benjamin Herrenschmidt
0008  *
0009  * UDMA support based on patches by Freescale (Bernard Kuhn, John Rigby),
0010  * Domen Puncer and Tim Yamin.
0011  *
0012  * This file is licensed under the terms of the GNU General Public License
0013  * version 2. This program is licensed "as is" without any warranty of any
0014  * kind, whether express or implied.
0015  */
0016 
0017 #include <linux/kernel.h>
0018 #include <linux/module.h>
0019 #include <linux/gfp.h>
0020 #include <linux/delay.h>
0021 #include <linux/libata.h>
0022 #include <linux/of_address.h>
0023 #include <linux/of_irq.h>
0024 #include <linux/of_platform.h>
0025 #include <linux/types.h>
0026 
0027 #include <asm/cacheflush.h>
0028 #include <asm/mpc52xx.h>
0029 
0030 #include <linux/fsl/bestcomm/bestcomm.h>
0031 #include <linux/fsl/bestcomm/bestcomm_priv.h>
0032 #include <linux/fsl/bestcomm/ata.h>
0033 
0034 #define DRV_NAME    "mpc52xx_ata"
0035 
0036 /* Private structures used by the driver */
0037 struct mpc52xx_ata_timings {
0038     u32 pio1;
0039     u32 pio2;
0040     u32 mdma1;
0041     u32 mdma2;
0042     u32 udma1;
0043     u32 udma2;
0044     u32 udma3;
0045     u32 udma4;
0046     u32 udma5;
0047     int using_udma;
0048 };
0049 
0050 struct mpc52xx_ata_priv {
0051     unsigned int            ipb_period;
0052     struct mpc52xx_ata __iomem  *ata_regs;
0053     phys_addr_t         ata_regs_pa;
0054     int             ata_irq;
0055     struct mpc52xx_ata_timings  timings[2];
0056     int             csel;
0057 
0058     /* DMA */
0059     struct bcom_task        *dmatsk;
0060     const struct udmaspec       *udmaspec;
0061     const struct mdmaspec       *mdmaspec;
0062     int                 mpc52xx_ata_dma_last_write;
0063     int             waiting_for_dma;
0064 };
0065 
0066 
0067 /* ATAPI-4 PIO specs (in ns) */
0068 static const u16 ataspec_t0[5]      = {600, 383, 240, 180, 120};
0069 static const u16 ataspec_t1[5]      = { 70,  50,  30,  30,  25};
0070 static const u16 ataspec_t2_8[5]    = {290, 290, 290,  80,  70};
0071 static const u16 ataspec_t2_16[5]   = {165, 125, 100,  80,  70};
0072 static const u16 ataspec_t2i[5]     = {  0,   0,   0,  70,  25};
0073 static const u16 ataspec_t4[5]      = { 30,  20,  15,  10,  10};
0074 static const u16 ataspec_ta[5]      = { 35,  35,  35,  35,  35};
0075 
0076 #define CALC_CLKCYC(c,v) ((((v)+(c)-1)/(c)))
0077 
0078 /* ======================================================================== */
0079 
0080 /* ATAPI-4 MDMA specs (in clocks) */
0081 struct mdmaspec {
0082     u8 t0M;
0083     u8 td;
0084     u8 th;
0085     u8 tj;
0086     u8 tkw;
0087     u8 tm;
0088     u8 tn;
0089 };
0090 
0091 static const struct mdmaspec mdmaspec66[3] = {
0092     { .t0M = 32, .td = 15, .th = 2, .tj = 2, .tkw = 15, .tm = 4, .tn = 1 },
0093     { .t0M = 10, .td = 6,  .th = 1, .tj = 1, .tkw = 4,  .tm = 2, .tn = 1 },
0094     { .t0M = 8,  .td = 5,  .th = 1, .tj = 1, .tkw = 2,  .tm = 2, .tn = 1 },
0095 };
0096 
0097 static const struct mdmaspec mdmaspec132[3] = {
0098     { .t0M = 64, .td = 29, .th = 3, .tj = 3, .tkw = 29, .tm = 7, .tn = 2 },
0099     { .t0M = 20, .td = 11, .th = 2, .tj = 1, .tkw = 7,  .tm = 4, .tn = 1 },
0100     { .t0M = 16, .td = 10, .th = 2, .tj = 1, .tkw = 4,  .tm = 4, .tn = 1 },
0101 };
0102 
0103 /* ATAPI-4 UDMA specs (in clocks) */
0104 struct udmaspec {
0105     u8 tcyc;
0106     u8 t2cyc;
0107     u8 tds;
0108     u8 tdh;
0109     u8 tdvs;
0110     u8 tdvh;
0111     u8 tfs;
0112     u8 tli;
0113     u8 tmli;
0114     u8 taz;
0115     u8 tzah;
0116     u8 tenv;
0117     u8 tsr;
0118     u8 trfs;
0119     u8 trp;
0120     u8 tack;
0121     u8 tss;
0122 };
0123 
0124 static const struct udmaspec udmaspec66[6] = {
0125     { .tcyc = 8,  .t2cyc = 16, .tds  = 1,  .tdh  = 1, .tdvs = 5,  .tdvh = 1,
0126       .tfs  = 16, .tli   = 10, .tmli = 2,  .taz  = 1, .tzah = 2,  .tenv = 2,
0127       .tsr  = 3,  .trfs  = 5,  .trp  = 11, .tack = 2, .tss  = 4,
0128     },
0129     { .tcyc = 5,  .t2cyc = 11, .tds  = 1,  .tdh  = 1, .tdvs = 4,  .tdvh = 1,
0130       .tfs  = 14, .tli   = 10, .tmli = 2,  .taz  = 1, .tzah = 2,  .tenv = 2,
0131       .tsr  = 2,  .trfs  = 5,  .trp  = 9,  .tack = 2, .tss  = 4,
0132     },
0133     { .tcyc = 4,  .t2cyc = 8,  .tds  = 1,  .tdh  = 1, .tdvs = 3,  .tdvh = 1,
0134       .tfs  = 12, .tli   = 10, .tmli = 2,  .taz  = 1, .tzah = 2,  .tenv = 2,
0135       .tsr  = 2,  .trfs  = 4,  .trp  = 7,  .tack = 2, .tss  = 4,
0136     },
0137     { .tcyc = 3,  .t2cyc = 6,  .tds  = 1,  .tdh  = 1, .tdvs = 2,  .tdvh = 1,
0138       .tfs  = 9,  .tli   = 7,  .tmli = 2,  .taz  = 1, .tzah = 2,  .tenv = 2,
0139       .tsr  = 2,  .trfs  = 4,  .trp  = 7,  .tack = 2, .tss  = 4,
0140     },
0141     { .tcyc = 2,  .t2cyc = 4,  .tds  = 1,  .tdh  = 1, .tdvs = 1,  .tdvh = 1,
0142       .tfs  = 8,  .tli   = 8,  .tmli = 2,  .taz  = 1, .tzah = 2,  .tenv = 2,
0143       .tsr  = 2,  .trfs  = 4,  .trp  = 7,  .tack = 2, .tss  = 4,
0144     },
0145     { .tcyc = 2,  .t2cyc = 2,  .tds  = 1,  .tdh  = 1, .tdvs = 1,  .tdvh = 1,
0146       .tfs  = 6,  .tli   = 5,  .tmli = 2,  .taz  = 1, .tzah = 2,  .tenv = 2,
0147       .tsr  = 2,  .trfs  = 4,  .trp  = 6,  .tack = 2, .tss  = 4,
0148     },
0149 };
0150 
0151 static const struct udmaspec udmaspec132[6] = {
0152     { .tcyc = 15, .t2cyc = 31, .tds  = 2,  .tdh  = 1, .tdvs = 10, .tdvh = 1,
0153       .tfs  = 30, .tli   = 20, .tmli = 3,  .taz  = 2, .tzah = 3,  .tenv = 3,
0154       .tsr  = 7,  .trfs  = 10, .trp  = 22, .tack = 3, .tss  = 7,
0155     },
0156     { .tcyc = 10, .t2cyc = 21, .tds  = 2,  .tdh  = 1, .tdvs = 7,  .tdvh = 1,
0157       .tfs  = 27, .tli   = 20, .tmli = 3,  .taz  = 2, .tzah = 3,  .tenv = 3,
0158       .tsr  = 4,  .trfs  = 10, .trp  = 17, .tack = 3, .tss  = 7,
0159     },
0160     { .tcyc = 6,  .t2cyc = 12, .tds  = 1,  .tdh  = 1, .tdvs = 5,  .tdvh = 1,
0161       .tfs  = 23, .tli   = 20, .tmli = 3,  .taz  = 2, .tzah = 3,  .tenv = 3,
0162       .tsr  = 3,  .trfs  = 8,  .trp  = 14, .tack = 3, .tss  = 7,
0163     },
0164     { .tcyc = 7,  .t2cyc = 12, .tds  = 1,  .tdh  = 1, .tdvs = 3,  .tdvh = 1,
0165       .tfs  = 15, .tli   = 13, .tmli = 3,  .taz  = 2, .tzah = 3,  .tenv = 3,
0166       .tsr  = 3,  .trfs  = 8,  .trp  = 14, .tack = 3, .tss  = 7,
0167     },
0168     { .tcyc = 2,  .t2cyc = 5,  .tds  = 0,  .tdh  = 0, .tdvs = 1,  .tdvh = 1,
0169       .tfs  = 16, .tli   = 14, .tmli = 2,  .taz  = 1, .tzah = 2,  .tenv = 2,
0170       .tsr  = 2,  .trfs  = 7,  .trp  = 13, .tack = 2, .tss  = 6,
0171     },
0172     { .tcyc = 3,  .t2cyc = 6,  .tds  = 1,  .tdh  = 1, .tdvs = 1,  .tdvh = 1,
0173       .tfs  = 12, .tli   = 10, .tmli = 3,  .taz  = 2, .tzah = 3,  .tenv = 3,
0174       .tsr  = 3,  .trfs  = 7,  .trp  = 12, .tack = 3, .tss  = 7,
0175     },
0176 };
0177 
0178 /* ======================================================================== */
0179 
0180 /* Bit definitions inside the registers */
0181 #define MPC52xx_ATA_HOSTCONF_SMR    0x80000000UL /* State machine reset */
0182 #define MPC52xx_ATA_HOSTCONF_FR     0x40000000UL /* FIFO Reset */
0183 #define MPC52xx_ATA_HOSTCONF_IE     0x02000000UL /* Enable interrupt in PIO */
0184 #define MPC52xx_ATA_HOSTCONF_IORDY  0x01000000UL /* Drive supports IORDY protocol */
0185 
0186 #define MPC52xx_ATA_HOSTSTAT_TIP    0x80000000UL /* Transaction in progress */
0187 #define MPC52xx_ATA_HOSTSTAT_UREP   0x40000000UL /* UDMA Read Extended Pause */
0188 #define MPC52xx_ATA_HOSTSTAT_RERR   0x02000000UL /* Read Error */
0189 #define MPC52xx_ATA_HOSTSTAT_WERR   0x01000000UL /* Write Error */
0190 
0191 #define MPC52xx_ATA_FIFOSTAT_EMPTY  0x01 /* FIFO Empty */
0192 #define MPC52xx_ATA_FIFOSTAT_ERROR  0x40 /* FIFO Error */
0193 
0194 #define MPC52xx_ATA_DMAMODE_WRITE   0x01 /* Write DMA */
0195 #define MPC52xx_ATA_DMAMODE_READ    0x02 /* Read DMA */
0196 #define MPC52xx_ATA_DMAMODE_UDMA    0x04 /* UDMA enabled */
0197 #define MPC52xx_ATA_DMAMODE_IE      0x08 /* Enable drive interrupt to CPU in DMA mode */
0198 #define MPC52xx_ATA_DMAMODE_FE      0x10 /* FIFO Flush enable in Rx mode */
0199 #define MPC52xx_ATA_DMAMODE_FR      0x20 /* FIFO Reset */
0200 #define MPC52xx_ATA_DMAMODE_HUT     0x40 /* Host UDMA burst terminate */
0201 
0202 #define MAX_DMA_BUFFERS 128
0203 #define MAX_DMA_BUFFER_SIZE 0x20000u
0204 
0205 /* Structure of the hardware registers */
0206 struct mpc52xx_ata {
0207 
0208     /* Host interface registers */
0209     u32 config;     /* ATA + 0x00 Host configuration */
0210     u32 host_status;    /* ATA + 0x04 Host controller status */
0211     u32 pio1;       /* ATA + 0x08 PIO Timing 1 */
0212     u32 pio2;       /* ATA + 0x0c PIO Timing 2 */
0213     u32 mdma1;      /* ATA + 0x10 MDMA Timing 1 */
0214     u32 mdma2;      /* ATA + 0x14 MDMA Timing 2 */
0215     u32 udma1;      /* ATA + 0x18 UDMA Timing 1 */
0216     u32 udma2;      /* ATA + 0x1c UDMA Timing 2 */
0217     u32 udma3;      /* ATA + 0x20 UDMA Timing 3 */
0218     u32 udma4;      /* ATA + 0x24 UDMA Timing 4 */
0219     u32 udma5;      /* ATA + 0x28 UDMA Timing 5 */
0220     u32 share_cnt;      /* ATA + 0x2c ATA share counter */
0221     u32 reserved0[3];
0222 
0223     /* FIFO registers */
0224     u32 fifo_data;      /* ATA + 0x3c */
0225     u8  fifo_status_frame;  /* ATA + 0x40 */
0226     u8  fifo_status;    /* ATA + 0x41 */
0227     u16 reserved7[1];
0228     u8  fifo_control;   /* ATA + 0x44 */
0229     u8  reserved8[5];
0230     u16 fifo_alarm;     /* ATA + 0x4a */
0231     u16 reserved9;
0232     u16 fifo_rdp;       /* ATA + 0x4e */
0233     u16 reserved10;
0234     u16 fifo_wrp;       /* ATA + 0x52 */
0235     u16 reserved11;
0236     u16 fifo_lfrdp;     /* ATA + 0x56 */
0237     u16 reserved12;
0238     u16 fifo_lfwrp;     /* ATA + 0x5a */
0239 
0240     /* Drive TaskFile registers */
0241     u8  tf_control;     /* ATA + 0x5c TASKFILE Control/Alt Status */
0242     u8  reserved13[3];
0243     u16 tf_data;        /* ATA + 0x60 TASKFILE Data */
0244     u16 reserved14;
0245     u8  tf_features;    /* ATA + 0x64 TASKFILE Features/Error */
0246     u8  reserved15[3];
0247     u8  tf_sec_count;   /* ATA + 0x68 TASKFILE Sector Count */
0248     u8  reserved16[3];
0249     u8  tf_sec_num;     /* ATA + 0x6c TASKFILE Sector Number */
0250     u8  reserved17[3];
0251     u8  tf_cyl_low;     /* ATA + 0x70 TASKFILE Cylinder Low */
0252     u8  reserved18[3];
0253     u8  tf_cyl_high;    /* ATA + 0x74 TASKFILE Cylinder High */
0254     u8  reserved19[3];
0255     u8  tf_dev_head;    /* ATA + 0x78 TASKFILE Device/Head */
0256     u8  reserved20[3];
0257     u8  tf_command;     /* ATA + 0x7c TASKFILE Command/Status */
0258     u8  dma_mode;       /* ATA + 0x7d ATA Host DMA Mode configuration */
0259     u8  reserved21[2];
0260 };
0261 
0262 
0263 /* ======================================================================== */
0264 /* Aux fns                                                                  */
0265 /* ======================================================================== */
0266 
0267 
0268 /* MPC52xx low level hw control */
0269 static int
0270 mpc52xx_ata_compute_pio_timings(struct mpc52xx_ata_priv *priv, int dev, int pio)
0271 {
0272     struct mpc52xx_ata_timings *timing = &priv->timings[dev];
0273     unsigned int ipb_period = priv->ipb_period;
0274     u32 t0, t1, t2_8, t2_16, t2i, t4, ta;
0275 
0276     if ((pio < 0) || (pio > 4))
0277         return -EINVAL;
0278 
0279     t0  = CALC_CLKCYC(ipb_period, 1000 * ataspec_t0[pio]);
0280     t1  = CALC_CLKCYC(ipb_period, 1000 * ataspec_t1[pio]);
0281     t2_8    = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_8[pio]);
0282     t2_16   = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_16[pio]);
0283     t2i = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2i[pio]);
0284     t4  = CALC_CLKCYC(ipb_period, 1000 * ataspec_t4[pio]);
0285     ta  = CALC_CLKCYC(ipb_period, 1000 * ataspec_ta[pio]);
0286 
0287     timing->pio1 = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8) | (t2i);
0288     timing->pio2 = (t4 << 24) | (t1 << 16) | (ta << 8);
0289 
0290     return 0;
0291 }
0292 
0293 static int
0294 mpc52xx_ata_compute_mdma_timings(struct mpc52xx_ata_priv *priv, int dev,
0295                  int speed)
0296 {
0297     struct mpc52xx_ata_timings *t = &priv->timings[dev];
0298     const struct mdmaspec *s = &priv->mdmaspec[speed];
0299 
0300     if (speed < 0 || speed > 2)
0301         return -EINVAL;
0302 
0303     t->mdma1 = ((u32)s->t0M << 24) | ((u32)s->td << 16) | ((u32)s->tkw << 8) | s->tm;
0304     t->mdma2 = ((u32)s->th << 24) | ((u32)s->tj << 16) | ((u32)s->tn << 8);
0305     t->using_udma = 0;
0306 
0307     return 0;
0308 }
0309 
0310 static int
0311 mpc52xx_ata_compute_udma_timings(struct mpc52xx_ata_priv *priv, int dev,
0312                  int speed)
0313 {
0314     struct mpc52xx_ata_timings *t = &priv->timings[dev];
0315     const struct udmaspec *s = &priv->udmaspec[speed];
0316 
0317     if (speed < 0 || speed > 2)
0318         return -EINVAL;
0319 
0320     t->udma1 = ((u32)s->t2cyc << 24) | ((u32)s->tcyc << 16) | ((u32)s->tds << 8) | s->tdh;
0321     t->udma2 = ((u32)s->tdvs << 24) | ((u32)s->tdvh << 16) | ((u32)s->tfs << 8) | s->tli;
0322     t->udma3 = ((u32)s->tmli << 24) | ((u32)s->taz << 16) | ((u32)s->tenv << 8) | s->tsr;
0323     t->udma4 = ((u32)s->tss << 24) | ((u32)s->trfs << 16) | ((u32)s->trp << 8) | s->tack;
0324     t->udma5 = (u32)s->tzah << 24;
0325     t->using_udma = 1;
0326 
0327     return 0;
0328 }
0329 
0330 static void
0331 mpc52xx_ata_apply_timings(struct mpc52xx_ata_priv *priv, int device)
0332 {
0333     struct mpc52xx_ata __iomem *regs = priv->ata_regs;
0334     struct mpc52xx_ata_timings *timing = &priv->timings[device];
0335 
0336     out_be32(&regs->pio1,  timing->pio1);
0337     out_be32(&regs->pio2,  timing->pio2);
0338     out_be32(&regs->mdma1, timing->mdma1);
0339     out_be32(&regs->mdma2, timing->mdma2);
0340     out_be32(&regs->udma1, timing->udma1);
0341     out_be32(&regs->udma2, timing->udma2);
0342     out_be32(&regs->udma3, timing->udma3);
0343     out_be32(&regs->udma4, timing->udma4);
0344     out_be32(&regs->udma5, timing->udma5);
0345     priv->csel = device;
0346 }
0347 
0348 static int
0349 mpc52xx_ata_hw_init(struct mpc52xx_ata_priv *priv)
0350 {
0351     struct mpc52xx_ata __iomem *regs = priv->ata_regs;
0352     int tslot;
0353 
0354     /* Clear share_cnt (all sample code do this ...) */
0355     out_be32(&regs->share_cnt, 0);
0356 
0357     /* Configure and reset host */
0358     out_be32(&regs->config,
0359             MPC52xx_ATA_HOSTCONF_IE |
0360             MPC52xx_ATA_HOSTCONF_IORDY |
0361             MPC52xx_ATA_HOSTCONF_SMR |
0362             MPC52xx_ATA_HOSTCONF_FR);
0363 
0364     udelay(10);
0365 
0366     out_be32(&regs->config,
0367             MPC52xx_ATA_HOSTCONF_IE |
0368             MPC52xx_ATA_HOSTCONF_IORDY);
0369 
0370     /* Set the time slot to 1us */
0371     tslot = CALC_CLKCYC(priv->ipb_period, 1000000);
0372     out_be32(&regs->share_cnt, tslot << 16);
0373 
0374     /* Init timings to PIO0 */
0375     memset(priv->timings, 0x00, 2*sizeof(struct mpc52xx_ata_timings));
0376 
0377     mpc52xx_ata_compute_pio_timings(priv, 0, 0);
0378     mpc52xx_ata_compute_pio_timings(priv, 1, 0);
0379 
0380     mpc52xx_ata_apply_timings(priv, 0);
0381 
0382     return 0;
0383 }
0384 
0385 
0386 /* ======================================================================== */
0387 /* libata driver                                                            */
0388 /* ======================================================================== */
0389 
0390 static void
0391 mpc52xx_ata_set_piomode(struct ata_port *ap, struct ata_device *adev)
0392 {
0393     struct mpc52xx_ata_priv *priv = ap->host->private_data;
0394     int pio, rv;
0395 
0396     pio = adev->pio_mode - XFER_PIO_0;
0397 
0398     rv = mpc52xx_ata_compute_pio_timings(priv, adev->devno, pio);
0399 
0400     if (rv) {
0401         dev_err(ap->dev, "error: invalid PIO mode: %d\n", pio);
0402         return;
0403     }
0404 
0405     mpc52xx_ata_apply_timings(priv, adev->devno);
0406 }
0407 
0408 static void
0409 mpc52xx_ata_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0410 {
0411     struct mpc52xx_ata_priv *priv = ap->host->private_data;
0412     int rv;
0413 
0414     if (adev->dma_mode >= XFER_UDMA_0) {
0415         int dma = adev->dma_mode - XFER_UDMA_0;
0416         rv = mpc52xx_ata_compute_udma_timings(priv, adev->devno, dma);
0417     } else {
0418         int dma = adev->dma_mode - XFER_MW_DMA_0;
0419         rv = mpc52xx_ata_compute_mdma_timings(priv, adev->devno, dma);
0420     }
0421 
0422     if (rv) {
0423         dev_alert(ap->dev,
0424             "Trying to select invalid DMA mode %d\n",
0425             adev->dma_mode);
0426         return;
0427     }
0428 
0429     mpc52xx_ata_apply_timings(priv, adev->devno);
0430 }
0431 
0432 static void
0433 mpc52xx_ata_dev_select(struct ata_port *ap, unsigned int device)
0434 {
0435     struct mpc52xx_ata_priv *priv = ap->host->private_data;
0436 
0437     if (device != priv->csel)
0438         mpc52xx_ata_apply_timings(priv, device);
0439 
0440     ata_sff_dev_select(ap, device);
0441 }
0442 
0443 static int
0444 mpc52xx_ata_build_dmatable(struct ata_queued_cmd *qc)
0445 {
0446     struct ata_port *ap = qc->ap;
0447     struct mpc52xx_ata_priv *priv = ap->host->private_data;
0448     struct bcom_ata_bd *bd;
0449     unsigned int read = !(qc->tf.flags & ATA_TFLAG_WRITE), si;
0450     struct scatterlist *sg;
0451     int count = 0;
0452 
0453     if (read)
0454         bcom_ata_rx_prepare(priv->dmatsk);
0455     else
0456         bcom_ata_tx_prepare(priv->dmatsk);
0457 
0458     for_each_sg(qc->sg, sg, qc->n_elem, si) {
0459         dma_addr_t cur_addr = sg_dma_address(sg);
0460         u32 cur_len = sg_dma_len(sg);
0461 
0462         while (cur_len) {
0463             unsigned int tc = min(cur_len, MAX_DMA_BUFFER_SIZE);
0464             bd = (struct bcom_ata_bd *)
0465                 bcom_prepare_next_buffer(priv->dmatsk);
0466 
0467             if (read) {
0468                 bd->status = tc;
0469                 bd->src_pa = (__force u32) priv->ata_regs_pa +
0470                     offsetof(struct mpc52xx_ata, fifo_data);
0471                 bd->dst_pa = (__force u32) cur_addr;
0472             } else {
0473                 bd->status = tc;
0474                 bd->src_pa = (__force u32) cur_addr;
0475                 bd->dst_pa = (__force u32) priv->ata_regs_pa +
0476                     offsetof(struct mpc52xx_ata, fifo_data);
0477             }
0478 
0479             bcom_submit_next_buffer(priv->dmatsk, NULL);
0480 
0481             cur_addr += tc;
0482             cur_len -= tc;
0483             count++;
0484 
0485             if (count > MAX_DMA_BUFFERS) {
0486                 dev_alert(ap->dev, "dma table"
0487                     "too small\n");
0488                 goto use_pio_instead;
0489             }
0490         }
0491     }
0492     return 1;
0493 
0494  use_pio_instead:
0495     bcom_ata_reset_bd(priv->dmatsk);
0496     return 0;
0497 }
0498 
0499 static void
0500 mpc52xx_bmdma_setup(struct ata_queued_cmd *qc)
0501 {
0502     struct ata_port *ap = qc->ap;
0503     struct mpc52xx_ata_priv *priv = ap->host->private_data;
0504     struct mpc52xx_ata __iomem *regs = priv->ata_regs;
0505 
0506     unsigned int read = !(qc->tf.flags & ATA_TFLAG_WRITE);
0507     u8 dma_mode;
0508 
0509     if (!mpc52xx_ata_build_dmatable(qc))
0510         dev_alert(ap->dev, "%s: %i, return 1?\n",
0511             __func__, __LINE__);
0512 
0513     /* Check FIFO is OK... */
0514     if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR)
0515         dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n",
0516             __func__, in_8(&priv->ata_regs->fifo_status));
0517 
0518     if (read) {
0519         dma_mode = MPC52xx_ATA_DMAMODE_IE | MPC52xx_ATA_DMAMODE_READ |
0520                 MPC52xx_ATA_DMAMODE_FE;
0521 
0522         /* Setup FIFO if direction changed */
0523         if (priv->mpc52xx_ata_dma_last_write != 0) {
0524             priv->mpc52xx_ata_dma_last_write = 0;
0525 
0526             /* Configure FIFO with granularity to 7 */
0527             out_8(&regs->fifo_control, 7);
0528             out_be16(&regs->fifo_alarm, 128);
0529 
0530             /* Set FIFO Reset bit (FR) */
0531             out_8(&regs->dma_mode, MPC52xx_ATA_DMAMODE_FR);
0532         }
0533     } else {
0534         dma_mode = MPC52xx_ATA_DMAMODE_IE | MPC52xx_ATA_DMAMODE_WRITE;
0535 
0536         /* Setup FIFO if direction changed */
0537         if (priv->mpc52xx_ata_dma_last_write != 1) {
0538             priv->mpc52xx_ata_dma_last_write = 1;
0539 
0540             /* Configure FIFO with granularity to 4 */
0541             out_8(&regs->fifo_control, 4);
0542             out_be16(&regs->fifo_alarm, 128);
0543         }
0544     }
0545 
0546     if (priv->timings[qc->dev->devno].using_udma)
0547         dma_mode |= MPC52xx_ATA_DMAMODE_UDMA;
0548 
0549     out_8(&regs->dma_mode, dma_mode);
0550     priv->waiting_for_dma = ATA_DMA_ACTIVE;
0551 
0552     ata_wait_idle(ap);
0553     ap->ops->sff_exec_command(ap, &qc->tf);
0554 }
0555 
0556 static void
0557 mpc52xx_bmdma_start(struct ata_queued_cmd *qc)
0558 {
0559     struct ata_port *ap = qc->ap;
0560     struct mpc52xx_ata_priv *priv = ap->host->private_data;
0561 
0562     bcom_set_task_auto_start(priv->dmatsk->tasknum, priv->dmatsk->tasknum);
0563     bcom_enable(priv->dmatsk);
0564 }
0565 
0566 static void
0567 mpc52xx_bmdma_stop(struct ata_queued_cmd *qc)
0568 {
0569     struct ata_port *ap = qc->ap;
0570     struct mpc52xx_ata_priv *priv = ap->host->private_data;
0571 
0572     bcom_disable(priv->dmatsk);
0573     bcom_ata_reset_bd(priv->dmatsk);
0574     priv->waiting_for_dma = 0;
0575 
0576     /* Check FIFO is OK... */
0577     if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR)
0578         dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n",
0579             __func__, in_8(&priv->ata_regs->fifo_status));
0580 }
0581 
0582 static u8
0583 mpc52xx_bmdma_status(struct ata_port *ap)
0584 {
0585     struct mpc52xx_ata_priv *priv = ap->host->private_data;
0586 
0587     /* Check FIFO is OK... */
0588     if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR) {
0589         dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n",
0590             __func__, in_8(&priv->ata_regs->fifo_status));
0591         return priv->waiting_for_dma | ATA_DMA_ERR;
0592     }
0593 
0594     return priv->waiting_for_dma;
0595 }
0596 
0597 static irqreturn_t
0598 mpc52xx_ata_task_irq(int irq, void *vpriv)
0599 {
0600     struct mpc52xx_ata_priv *priv = vpriv;
0601     while (bcom_buffer_done(priv->dmatsk))
0602         bcom_retrieve_buffer(priv->dmatsk, NULL, NULL);
0603 
0604     priv->waiting_for_dma |= ATA_DMA_INTR;
0605 
0606     return IRQ_HANDLED;
0607 }
0608 
0609 static struct scsi_host_template mpc52xx_ata_sht = {
0610     ATA_PIO_SHT(DRV_NAME),
0611 };
0612 
0613 static struct ata_port_operations mpc52xx_ata_port_ops = {
0614     .inherits       = &ata_bmdma_port_ops,
0615     .sff_dev_select     = mpc52xx_ata_dev_select,
0616     .set_piomode        = mpc52xx_ata_set_piomode,
0617     .set_dmamode        = mpc52xx_ata_set_dmamode,
0618     .bmdma_setup        = mpc52xx_bmdma_setup,
0619     .bmdma_start        = mpc52xx_bmdma_start,
0620     .bmdma_stop     = mpc52xx_bmdma_stop,
0621     .bmdma_status       = mpc52xx_bmdma_status,
0622     .qc_prep        = ata_noop_qc_prep,
0623 };
0624 
0625 static int mpc52xx_ata_init_one(struct device *dev,
0626                 struct mpc52xx_ata_priv *priv,
0627                 unsigned long raw_ata_regs,
0628                 int mwdma_mask, int udma_mask)
0629 {
0630     struct ata_host *host;
0631     struct ata_port *ap;
0632     struct ata_ioports *aio;
0633 
0634     host = ata_host_alloc(dev, 1);
0635     if (!host)
0636         return -ENOMEM;
0637 
0638     ap = host->ports[0];
0639     ap->flags       |= ATA_FLAG_SLAVE_POSS;
0640     ap->pio_mask        = ATA_PIO4;
0641     ap->mwdma_mask      = mwdma_mask;
0642     ap->udma_mask       = udma_mask;
0643     ap->ops         = &mpc52xx_ata_port_ops;
0644     host->private_data  = priv;
0645 
0646     aio = &ap->ioaddr;
0647     aio->cmd_addr       = NULL; /* Don't have a classic reg block */
0648     aio->altstatus_addr = &priv->ata_regs->tf_control;
0649     aio->ctl_addr       = &priv->ata_regs->tf_control;
0650     aio->data_addr      = &priv->ata_regs->tf_data;
0651     aio->error_addr     = &priv->ata_regs->tf_features;
0652     aio->feature_addr   = &priv->ata_regs->tf_features;
0653     aio->nsect_addr     = &priv->ata_regs->tf_sec_count;
0654     aio->lbal_addr      = &priv->ata_regs->tf_sec_num;
0655     aio->lbam_addr      = &priv->ata_regs->tf_cyl_low;
0656     aio->lbah_addr      = &priv->ata_regs->tf_cyl_high;
0657     aio->device_addr    = &priv->ata_regs->tf_dev_head;
0658     aio->status_addr    = &priv->ata_regs->tf_command;
0659     aio->command_addr   = &priv->ata_regs->tf_command;
0660 
0661     ata_port_desc(ap, "ata_regs 0x%lx", raw_ata_regs);
0662 
0663     /* activate host */
0664     return ata_host_activate(host, priv->ata_irq, ata_bmdma_interrupt, 0,
0665                  &mpc52xx_ata_sht);
0666 }
0667 
0668 /* ======================================================================== */
0669 /* OF Platform driver                                                       */
0670 /* ======================================================================== */
0671 
0672 static int mpc52xx_ata_probe(struct platform_device *op)
0673 {
0674     unsigned int ipb_freq;
0675     struct resource res_mem;
0676     int ata_irq = 0;
0677     struct mpc52xx_ata __iomem *ata_regs;
0678     struct mpc52xx_ata_priv *priv = NULL;
0679     int rv, task_irq;
0680     int mwdma_mask = 0, udma_mask = 0;
0681     const __be32 *prop;
0682     int proplen;
0683     struct bcom_task *dmatsk;
0684 
0685     /* Get ipb frequency */
0686     ipb_freq = mpc5xxx_get_bus_frequency(&op->dev);
0687     if (!ipb_freq) {
0688         dev_err(&op->dev, "could not determine IPB bus frequency\n");
0689         return -ENODEV;
0690     }
0691 
0692     /* Get device base address from device tree, request the region
0693      * and ioremap it. */
0694     rv = of_address_to_resource(op->dev.of_node, 0, &res_mem);
0695     if (rv) {
0696         dev_err(&op->dev, "could not determine device base address\n");
0697         return rv;
0698     }
0699 
0700     if (!devm_request_mem_region(&op->dev, res_mem.start,
0701                      sizeof(*ata_regs), DRV_NAME)) {
0702         dev_err(&op->dev, "error requesting register region\n");
0703         return -EBUSY;
0704     }
0705 
0706     ata_regs = devm_ioremap(&op->dev, res_mem.start, sizeof(*ata_regs));
0707     if (!ata_regs) {
0708         dev_err(&op->dev, "error mapping device registers\n");
0709         return -ENOMEM;
0710     }
0711 
0712     /*
0713      * By default, all DMA modes are disabled for the MPC5200.  Some
0714      * boards don't have the required signals routed to make DMA work.
0715      * Also, the MPC5200B has a silicon bug that causes data corruption
0716      * with UDMA if it is used at the same time as the LocalPlus bus.
0717      *
0718      * Instead of trying to guess what modes are usable, check the
0719      * ATA device tree node to find out what DMA modes work on the board.
0720      * UDMA/MWDMA modes can also be forced by adding "libata.force=<mode>"
0721      * to the kernel boot parameters.
0722      *
0723      * The MPC5200 ATA controller supports MWDMA modes 0, 1 and 2 and
0724      * UDMA modes 0, 1 and 2.
0725      */
0726     prop = of_get_property(op->dev.of_node, "mwdma-mode", &proplen);
0727     if ((prop) && (proplen >= 4))
0728         mwdma_mask = ATA_MWDMA2 & ((1 << (*prop + 1)) - 1);
0729     prop = of_get_property(op->dev.of_node, "udma-mode", &proplen);
0730     if ((prop) && (proplen >= 4))
0731         udma_mask = ATA_UDMA2 & ((1 << (*prop + 1)) - 1);
0732 
0733     ata_irq = irq_of_parse_and_map(op->dev.of_node, 0);
0734     if (ata_irq == NO_IRQ) {
0735         dev_err(&op->dev, "error mapping irq\n");
0736         return -EINVAL;
0737     }
0738 
0739     /* Prepare our private structure */
0740     priv = devm_kzalloc(&op->dev, sizeof(*priv), GFP_KERNEL);
0741     if (!priv) {
0742         rv = -ENOMEM;
0743         goto err1;
0744     }
0745 
0746     priv->ipb_period = 1000000000 / (ipb_freq / 1000);
0747     priv->ata_regs = ata_regs;
0748     priv->ata_regs_pa = res_mem.start;
0749     priv->ata_irq = ata_irq;
0750     priv->csel = -1;
0751     priv->mpc52xx_ata_dma_last_write = -1;
0752 
0753     if (ipb_freq/1000000 == 66) {
0754         priv->mdmaspec = mdmaspec66;
0755         priv->udmaspec = udmaspec66;
0756     } else {
0757         priv->mdmaspec = mdmaspec132;
0758         priv->udmaspec = udmaspec132;
0759     }
0760 
0761     /* Allocate a BestComm task for DMA */
0762     dmatsk = bcom_ata_init(MAX_DMA_BUFFERS, MAX_DMA_BUFFER_SIZE);
0763     if (!dmatsk) {
0764         dev_err(&op->dev, "bestcomm initialization failed\n");
0765         rv = -ENOMEM;
0766         goto err1;
0767     }
0768 
0769     task_irq = bcom_get_task_irq(dmatsk);
0770     rv = devm_request_irq(&op->dev, task_irq, &mpc52xx_ata_task_irq, 0,
0771                 "ATA task", priv);
0772     if (rv) {
0773         dev_err(&op->dev, "error requesting DMA IRQ\n");
0774         goto err2;
0775     }
0776     priv->dmatsk = dmatsk;
0777 
0778     /* Init the hw */
0779     rv = mpc52xx_ata_hw_init(priv);
0780     if (rv) {
0781         dev_err(&op->dev, "error initializing hardware\n");
0782         goto err2;
0783     }
0784 
0785     /* Register ourselves to libata */
0786     rv = mpc52xx_ata_init_one(&op->dev, priv, res_mem.start,
0787                   mwdma_mask, udma_mask);
0788     if (rv) {
0789         dev_err(&op->dev, "error registering with ATA layer\n");
0790         goto err2;
0791     }
0792 
0793     return 0;
0794 
0795  err2:
0796     irq_dispose_mapping(task_irq);
0797     bcom_ata_release(dmatsk);
0798  err1:
0799     irq_dispose_mapping(ata_irq);
0800     return rv;
0801 }
0802 
0803 static int
0804 mpc52xx_ata_remove(struct platform_device *op)
0805 {
0806     struct ata_host *host = platform_get_drvdata(op);
0807     struct mpc52xx_ata_priv *priv = host->private_data;
0808     int task_irq;
0809 
0810     /* Deregister the ATA interface */
0811     ata_platform_remove_one(op);
0812 
0813     /* Clean up DMA */
0814     task_irq = bcom_get_task_irq(priv->dmatsk);
0815     irq_dispose_mapping(task_irq);
0816     bcom_ata_release(priv->dmatsk);
0817     irq_dispose_mapping(priv->ata_irq);
0818 
0819     return 0;
0820 }
0821 
0822 #ifdef CONFIG_PM_SLEEP
0823 static int
0824 mpc52xx_ata_suspend(struct platform_device *op, pm_message_t state)
0825 {
0826     struct ata_host *host = platform_get_drvdata(op);
0827 
0828     ata_host_suspend(host, state);
0829     return 0;
0830 }
0831 
0832 static int
0833 mpc52xx_ata_resume(struct platform_device *op)
0834 {
0835     struct ata_host *host = platform_get_drvdata(op);
0836     struct mpc52xx_ata_priv *priv = host->private_data;
0837     int rv;
0838 
0839     rv = mpc52xx_ata_hw_init(priv);
0840     if (rv) {
0841         dev_err(host->dev, "error initializing hardware\n");
0842         return rv;
0843     }
0844 
0845     ata_host_resume(host);
0846 
0847     return 0;
0848 }
0849 #endif
0850 
0851 static const struct of_device_id mpc52xx_ata_of_match[] = {
0852     { .compatible = "fsl,mpc5200-ata", },
0853     { .compatible = "mpc5200-ata", },
0854     { /* sentinel */ }
0855 };
0856 
0857 
0858 static struct platform_driver mpc52xx_ata_of_platform_driver = {
0859     .probe      = mpc52xx_ata_probe,
0860     .remove     = mpc52xx_ata_remove,
0861 #ifdef CONFIG_PM_SLEEP
0862     .suspend    = mpc52xx_ata_suspend,
0863     .resume     = mpc52xx_ata_resume,
0864 #endif
0865     .driver     = {
0866         .name   = DRV_NAME,
0867         .of_match_table = mpc52xx_ata_of_match,
0868     },
0869 };
0870 
0871 module_platform_driver(mpc52xx_ata_of_platform_driver);
0872 
0873 MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
0874 MODULE_DESCRIPTION("Freescale MPC52xx IDE/ATA libata driver");
0875 MODULE_LICENSE("GPL");
0876 MODULE_DEVICE_TABLE(of, mpc52xx_ata_of_match);
0877
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