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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Libata based driver for Apple "macio" family of PATA controllers
0004  *
0005  * Copyright 2008/2009 Benjamin Herrenschmidt, IBM Corp
0006  *                     <benh@kernel.crashing.org>
0007  *
0008  * Some bits and pieces from drivers/ide/ppc/pmac.c
0009  *
0010  */
0011 
0012 #undef DEBUG
0013 #undef DEBUG_DMA
0014 
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/init.h>
0018 #include <linux/blkdev.h>
0019 #include <linux/ata.h>
0020 #include <linux/libata.h>
0021 #include <linux/adb.h>
0022 #include <linux/pmu.h>
0023 #include <linux/scatterlist.h>
0024 #include <linux/of.h>
0025 #include <linux/gfp.h>
0026 #include <linux/pci.h>
0027 
0028 #include <scsi/scsi.h>
0029 #include <scsi/scsi_host.h>
0030 #include <scsi/scsi_device.h>
0031 
0032 #include <asm/macio.h>
0033 #include <asm/io.h>
0034 #include <asm/dbdma.h>
0035 #include <asm/machdep.h>
0036 #include <asm/pmac_feature.h>
0037 #include <asm/mediabay.h>
0038 
0039 #ifdef DEBUG_DMA
0040 #define dev_dbgdma(dev, format, arg...)     \
0041     dev_printk(KERN_DEBUG , dev , format , ## arg)
0042 #else
0043 #define dev_dbgdma(dev, format, arg...)     \
0044     ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
0045 #endif
0046 
0047 #define DRV_NAME    "pata_macio"
0048 #define DRV_VERSION "0.9"
0049 
0050 /* Models of macio ATA controller */
0051 enum {
0052     controller_ohare,   /* OHare based */
0053     controller_heathrow,    /* Heathrow/Paddington */
0054     controller_kl_ata3, /* KeyLargo ATA-3 */
0055     controller_kl_ata4, /* KeyLargo ATA-4 */
0056     controller_un_ata6, /* UniNorth2 ATA-6 */
0057     controller_k2_ata6, /* K2 ATA-6 */
0058     controller_sh_ata6, /* Shasta ATA-6 */
0059 };
0060 
0061 static const char* macio_ata_names[] = {
0062     "OHare ATA",        /* OHare based */
0063     "Heathrow ATA",     /* Heathrow/Paddington */
0064     "KeyLargo ATA-3",   /* KeyLargo ATA-3 (MDMA only) */
0065     "KeyLargo ATA-4",   /* KeyLargo ATA-4 (UDMA/66) */
0066     "UniNorth ATA-6",   /* UniNorth2 ATA-6 (UDMA/100) */
0067     "K2 ATA-6",     /* K2 ATA-6 (UDMA/100) */
0068     "Shasta ATA-6",     /* Shasta ATA-6 (UDMA/133) */
0069 };
0070 
0071 /*
0072  * Extra registers, both 32-bit little-endian
0073  */
0074 #define IDE_TIMING_CONFIG   0x200
0075 #define IDE_INTERRUPT       0x300
0076 
0077 /* Kauai (U2) ATA has different register setup */
0078 #define IDE_KAUAI_PIO_CONFIG    0x200
0079 #define IDE_KAUAI_ULTRA_CONFIG  0x210
0080 #define IDE_KAUAI_POLL_CONFIG   0x220
0081 
0082 /*
0083  * Timing configuration register definitions
0084  */
0085 
0086 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
0087 #define SYSCLK_TICKS(t)     (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
0088 #define SYSCLK_TICKS_66(t)  (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
0089 #define IDE_SYSCLK_NS       30  /* 33Mhz cell */
0090 #define IDE_SYSCLK_66_NS    15  /* 66Mhz cell */
0091 
0092 /* 133Mhz cell, found in shasta.
0093  * See comments about 100 Mhz Uninorth 2...
0094  * Note that PIO_MASK and MDMA_MASK seem to overlap, that's just
0095  * weird and I don't now why .. at this stage
0096  */
0097 #define TR_133_PIOREG_PIO_MASK      0xff000fff
0098 #define TR_133_PIOREG_MDMA_MASK     0x00fff800
0099 #define TR_133_UDMAREG_UDMA_MASK    0x0003ffff
0100 #define TR_133_UDMAREG_UDMA_EN      0x00000001
0101 
0102 /* 100Mhz cell, found in Uninorth 2 and K2. It appears as a pci device
0103  * (106b/0033) on uninorth or K2 internal PCI bus and it's clock is
0104  * controlled like gem or fw. It appears to be an evolution of keylargo
0105  * ATA4 with a timing register extended to 2x32bits registers (one
0106  * for PIO & MWDMA and one for UDMA, and a similar DBDMA channel.
0107  * It has it's own local feature control register as well.
0108  *
0109  * After scratching my mind over the timing values, at least for PIO
0110  * and MDMA, I think I've figured the format of the timing register,
0111  * though I use pre-calculated tables for UDMA as usual...
0112  */
0113 #define TR_100_PIO_ADDRSETUP_MASK   0xff000000 /* Size of field unknown */
0114 #define TR_100_PIO_ADDRSETUP_SHIFT  24
0115 #define TR_100_MDMA_MASK        0x00fff000
0116 #define TR_100_MDMA_RECOVERY_MASK   0x00fc0000
0117 #define TR_100_MDMA_RECOVERY_SHIFT  18
0118 #define TR_100_MDMA_ACCESS_MASK     0x0003f000
0119 #define TR_100_MDMA_ACCESS_SHIFT    12
0120 #define TR_100_PIO_MASK         0xff000fff
0121 #define TR_100_PIO_RECOVERY_MASK    0x00000fc0
0122 #define TR_100_PIO_RECOVERY_SHIFT   6
0123 #define TR_100_PIO_ACCESS_MASK      0x0000003f
0124 #define TR_100_PIO_ACCESS_SHIFT     0
0125 
0126 #define TR_100_UDMAREG_UDMA_MASK    0x0000ffff
0127 #define TR_100_UDMAREG_UDMA_EN      0x00000001
0128 
0129 
0130 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
0131  * 40 connector cable and to 4 on 80 connector one.
0132  * Clock unit is 15ns (66Mhz)
0133  *
0134  * 3 Values can be programmed:
0135  *  - Write data setup, which appears to match the cycle time. They
0136  *    also call it DIOW setup.
0137  *  - Ready to pause time (from spec)
0138  *  - Address setup. That one is weird. I don't see where exactly
0139  *    it fits in UDMA cycles, I got it's name from an obscure piece
0140  *    of commented out code in Darwin. They leave it to 0, we do as
0141  *    well, despite a comment that would lead to think it has a
0142  *    min value of 45ns.
0143  * Apple also add 60ns to the write data setup (or cycle time ?) on
0144  * reads.
0145  */
0146 #define TR_66_UDMA_MASK         0xfff00000
0147 #define TR_66_UDMA_EN           0x00100000 /* Enable Ultra mode for DMA */
0148 #define TR_66_PIO_ADDRSETUP_MASK    0xe0000000 /* Address setup */
0149 #define TR_66_PIO_ADDRSETUP_SHIFT   29
0150 #define TR_66_UDMA_RDY2PAUS_MASK    0x1e000000 /* Ready 2 pause time */
0151 #define TR_66_UDMA_RDY2PAUS_SHIFT   25
0152 #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
0153 #define TR_66_UDMA_WRDATASETUP_SHIFT    21
0154 #define TR_66_MDMA_MASK         0x000ffc00
0155 #define TR_66_MDMA_RECOVERY_MASK    0x000f8000
0156 #define TR_66_MDMA_RECOVERY_SHIFT   15
0157 #define TR_66_MDMA_ACCESS_MASK      0x00007c00
0158 #define TR_66_MDMA_ACCESS_SHIFT     10
0159 #define TR_66_PIO_MASK          0xe00003ff
0160 #define TR_66_PIO_RECOVERY_MASK     0x000003e0
0161 #define TR_66_PIO_RECOVERY_SHIFT    5
0162 #define TR_66_PIO_ACCESS_MASK       0x0000001f
0163 #define TR_66_PIO_ACCESS_SHIFT      0
0164 
0165 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
0166  * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
0167  *
0168  * The access time and recovery time can be programmed. Some older
0169  * Darwin code base limit OHare to 150ns cycle time. I decided to do
0170  * the same here fore safety against broken old hardware ;)
0171  * The HalfTick bit, when set, adds half a clock (15ns) to the access
0172  * time and removes one from recovery. It's not supported on KeyLargo
0173  * implementation afaik. The E bit appears to be set for PIO mode 0 and
0174  * is used to reach long timings used in this mode.
0175  */
0176 #define TR_33_MDMA_MASK         0x003ff800
0177 #define TR_33_MDMA_RECOVERY_MASK    0x001f0000
0178 #define TR_33_MDMA_RECOVERY_SHIFT   16
0179 #define TR_33_MDMA_ACCESS_MASK      0x0000f800
0180 #define TR_33_MDMA_ACCESS_SHIFT     11
0181 #define TR_33_MDMA_HALFTICK     0x00200000
0182 #define TR_33_PIO_MASK          0x000007ff
0183 #define TR_33_PIO_E         0x00000400
0184 #define TR_33_PIO_RECOVERY_MASK     0x000003e0
0185 #define TR_33_PIO_RECOVERY_SHIFT    5
0186 #define TR_33_PIO_ACCESS_MASK       0x0000001f
0187 #define TR_33_PIO_ACCESS_SHIFT      0
0188 
0189 /*
0190  * Interrupt register definitions. Only present on newer cells
0191  * (Keylargo and later afaik) so we don't use it.
0192  */
0193 #define IDE_INTR_DMA            0x80000000
0194 #define IDE_INTR_DEVICE         0x40000000
0195 
0196 /*
0197  * FCR Register on Kauai. Not sure what bit 0x4 is  ...
0198  */
0199 #define KAUAI_FCR_UATA_MAGIC        0x00000004
0200 #define KAUAI_FCR_UATA_RESET_N      0x00000002
0201 #define KAUAI_FCR_UATA_ENABLE       0x00000001
0202 
0203 
0204 /* Allow up to 256 DBDMA commands per xfer */
0205 #define MAX_DCMDS       256
0206 
0207 /* Don't let a DMA segment go all the way to 64K */
0208 #define MAX_DBDMA_SEG       0xff00
0209 
0210 
0211 /*
0212  * Wait 1s for disk to answer on IDE bus after a hard reset
0213  * of the device (via GPIO/FCR).
0214  *
0215  * Some devices seem to "pollute" the bus even after dropping
0216  * the BSY bit (typically some combo drives slave on the UDMA
0217  * bus) after a hard reset. Since we hard reset all drives on
0218  * KeyLargo ATA66, we have to keep that delay around. I may end
0219  * up not hard resetting anymore on these and keep the delay only
0220  * for older interfaces instead (we have to reset when coming
0221  * from MacOS...) --BenH.
0222  */
0223 #define IDE_WAKEUP_DELAY_MS 1000
0224 
0225 struct pata_macio_timing;
0226 
0227 struct pata_macio_priv {
0228     int             kind;
0229     int             aapl_bus_id;
0230     int             mediabay : 1;
0231     struct device_node      *node;
0232     struct macio_dev        *mdev;
0233     struct pci_dev          *pdev;
0234     struct device           *dev;
0235     int             irq;
0236     u32             treg[2][2];
0237     void __iomem            *tfregs;
0238     void __iomem            *kauai_fcr;
0239     struct dbdma_cmd *      dma_table_cpu;
0240     dma_addr_t          dma_table_dma;
0241     struct ata_host         *host;
0242     const struct pata_macio_timing  *timings;
0243 };
0244 
0245 /* Previous variants of this driver used to calculate timings
0246  * for various variants of the chip and use tables for others.
0247  *
0248  * Not only was this confusing, but in addition, it isn't clear
0249  * whether our calculation code was correct. It didn't entirely
0250  * match the darwin code and whatever documentation I could find
0251  * on these cells
0252  *
0253  * I decided to entirely rely on a table instead for this version
0254  * of the driver. Also, because I don't really care about derated
0255  * modes and really old HW other than making it work, I'm not going
0256  * to calculate / snoop timing values for something else than the
0257  * standard modes.
0258  */
0259 struct pata_macio_timing {
0260     int mode;
0261     u32 reg1;   /* Bits to set in first timing reg */
0262     u32 reg2;   /* Bits to set in second timing reg */
0263 };
0264 
0265 static const struct pata_macio_timing pata_macio_ohare_timings[] = {
0266     { XFER_PIO_0,       0x00000526, 0, },
0267     { XFER_PIO_1,       0x00000085, 0, },
0268     { XFER_PIO_2,       0x00000025, 0, },
0269     { XFER_PIO_3,       0x00000025, 0, },
0270     { XFER_PIO_4,       0x00000025, 0, },
0271     { XFER_MW_DMA_0,    0x00074000, 0, },
0272     { XFER_MW_DMA_1,    0x00221000, 0, },
0273     { XFER_MW_DMA_2,    0x00211000, 0, },
0274     { -1, 0, 0 }
0275 };
0276 
0277 static const struct pata_macio_timing pata_macio_heathrow_timings[] = {
0278     { XFER_PIO_0,       0x00000526, 0, },
0279     { XFER_PIO_1,       0x00000085, 0, },
0280     { XFER_PIO_2,       0x00000025, 0, },
0281     { XFER_PIO_3,       0x00000025, 0, },
0282     { XFER_PIO_4,       0x00000025, 0, },
0283     { XFER_MW_DMA_0,    0x00074000, 0, },
0284     { XFER_MW_DMA_1,    0x00221000, 0, },
0285     { XFER_MW_DMA_2,    0x00211000, 0, },
0286     { -1, 0, 0 }
0287 };
0288 
0289 static const struct pata_macio_timing pata_macio_kl33_timings[] = {
0290     { XFER_PIO_0,       0x00000526, 0, },
0291     { XFER_PIO_1,       0x00000085, 0, },
0292     { XFER_PIO_2,       0x00000025, 0, },
0293     { XFER_PIO_3,       0x00000025, 0, },
0294     { XFER_PIO_4,       0x00000025, 0, },
0295     { XFER_MW_DMA_0,    0x00084000, 0, },
0296     { XFER_MW_DMA_1,    0x00021800, 0, },
0297     { XFER_MW_DMA_2,    0x00011800, 0, },
0298     { -1, 0, 0 }
0299 };
0300 
0301 static const struct pata_macio_timing pata_macio_kl66_timings[] = {
0302     { XFER_PIO_0,       0x0000038c, 0, },
0303     { XFER_PIO_1,       0x0000020a, 0, },
0304     { XFER_PIO_2,       0x00000127, 0, },
0305     { XFER_PIO_3,       0x000000c6, 0, },
0306     { XFER_PIO_4,       0x00000065, 0, },
0307     { XFER_MW_DMA_0,    0x00084000, 0, },
0308     { XFER_MW_DMA_1,    0x00029800, 0, },
0309     { XFER_MW_DMA_2,    0x00019400, 0, },
0310     { XFER_UDMA_0,      0x19100000, 0, },
0311     { XFER_UDMA_1,      0x14d00000, 0, },
0312     { XFER_UDMA_2,      0x10900000, 0, },
0313     { XFER_UDMA_3,      0x0c700000, 0, },
0314     { XFER_UDMA_4,      0x0c500000, 0, },
0315     { -1, 0, 0 }
0316 };
0317 
0318 static const struct pata_macio_timing pata_macio_kauai_timings[] = {
0319     { XFER_PIO_0,       0x08000a92, 0, },
0320     { XFER_PIO_1,       0x0800060f, 0, },
0321     { XFER_PIO_2,       0x0800038b, 0, },
0322     { XFER_PIO_3,       0x05000249, 0, },
0323     { XFER_PIO_4,       0x04000148, 0, },
0324     { XFER_MW_DMA_0,    0x00618000, 0, },
0325     { XFER_MW_DMA_1,    0x00209000, 0, },
0326     { XFER_MW_DMA_2,    0x00148000, 0, },
0327     { XFER_UDMA_0,               0, 0x000070c1, },
0328     { XFER_UDMA_1,               0, 0x00005d81, },
0329     { XFER_UDMA_2,               0, 0x00004a61, },
0330     { XFER_UDMA_3,               0, 0x00003a51, },
0331     { XFER_UDMA_4,               0, 0x00002a31, },
0332     { XFER_UDMA_5,               0, 0x00002921, },
0333     { -1, 0, 0 }
0334 };
0335 
0336 static const struct pata_macio_timing pata_macio_shasta_timings[] = {
0337     { XFER_PIO_0,       0x0a000c97, 0, },
0338     { XFER_PIO_1,       0x07000712, 0, },
0339     { XFER_PIO_2,       0x040003cd, 0, },
0340     { XFER_PIO_3,       0x0500028b, 0, },
0341     { XFER_PIO_4,       0x0400010a, 0, },
0342     { XFER_MW_DMA_0,    0x00820800, 0, },
0343     { XFER_MW_DMA_1,    0x0028b000, 0, },
0344     { XFER_MW_DMA_2,    0x001ca000, 0, },
0345     { XFER_UDMA_0,               0, 0x00035901, },
0346     { XFER_UDMA_1,               0, 0x000348b1, },
0347     { XFER_UDMA_2,               0, 0x00033881, },
0348     { XFER_UDMA_3,               0, 0x00033861, },
0349     { XFER_UDMA_4,               0, 0x00033841, },
0350     { XFER_UDMA_5,               0, 0x00033031, },
0351     { XFER_UDMA_6,               0, 0x00033021, },
0352     { -1, 0, 0 }
0353 };
0354 
0355 static const struct pata_macio_timing *pata_macio_find_timing(
0356                         struct pata_macio_priv *priv,
0357                         int mode)
0358 {
0359     int i;
0360 
0361     for (i = 0; priv->timings[i].mode > 0; i++) {
0362         if (priv->timings[i].mode == mode)
0363             return &priv->timings[i];
0364     }
0365     return NULL;
0366 }
0367 
0368 
0369 static void pata_macio_apply_timings(struct ata_port *ap, unsigned int device)
0370 {
0371     struct pata_macio_priv *priv = ap->private_data;
0372     void __iomem *rbase = ap->ioaddr.cmd_addr;
0373 
0374     if (priv->kind == controller_sh_ata6 ||
0375         priv->kind == controller_un_ata6 ||
0376         priv->kind == controller_k2_ata6) {
0377         writel(priv->treg[device][0], rbase + IDE_KAUAI_PIO_CONFIG);
0378         writel(priv->treg[device][1], rbase + IDE_KAUAI_ULTRA_CONFIG);
0379     } else
0380         writel(priv->treg[device][0], rbase + IDE_TIMING_CONFIG);
0381 }
0382 
0383 static void pata_macio_dev_select(struct ata_port *ap, unsigned int device)
0384 {
0385     ata_sff_dev_select(ap, device);
0386 
0387     /* Apply timings */
0388     pata_macio_apply_timings(ap, device);
0389 }
0390 
0391 static void pata_macio_set_timings(struct ata_port *ap,
0392                    struct ata_device *adev)
0393 {
0394     struct pata_macio_priv *priv = ap->private_data;
0395     const struct pata_macio_timing *t;
0396 
0397     dev_dbg(priv->dev, "Set timings: DEV=%d,PIO=0x%x (%s),DMA=0x%x (%s)\n",
0398         adev->devno,
0399         adev->pio_mode,
0400         ata_mode_string(ata_xfer_mode2mask(adev->pio_mode)),
0401         adev->dma_mode,
0402         ata_mode_string(ata_xfer_mode2mask(adev->dma_mode)));
0403 
0404     /* First clear timings */
0405     priv->treg[adev->devno][0] = priv->treg[adev->devno][1] = 0;
0406 
0407     /* Now get the PIO timings */
0408     t = pata_macio_find_timing(priv, adev->pio_mode);
0409     if (t == NULL) {
0410         dev_warn(priv->dev, "Invalid PIO timing requested: 0x%x\n",
0411              adev->pio_mode);
0412         t = pata_macio_find_timing(priv, XFER_PIO_0);
0413     }
0414     BUG_ON(t == NULL);
0415 
0416     /* PIO timings only ever use the first treg */
0417     priv->treg[adev->devno][0] |= t->reg1;
0418 
0419     /* Now get DMA timings */
0420     t = pata_macio_find_timing(priv, adev->dma_mode);
0421     if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) {
0422         dev_dbg(priv->dev, "DMA timing not set yet, using MW_DMA_0\n");
0423         t = pata_macio_find_timing(priv, XFER_MW_DMA_0);
0424     }
0425     BUG_ON(t == NULL);
0426 
0427     /* DMA timings can use both tregs */
0428     priv->treg[adev->devno][0] |= t->reg1;
0429     priv->treg[adev->devno][1] |= t->reg2;
0430 
0431     dev_dbg(priv->dev, " -> %08x %08x\n",
0432         priv->treg[adev->devno][0],
0433         priv->treg[adev->devno][1]);
0434 
0435     /* Apply to hardware */
0436     pata_macio_apply_timings(ap, adev->devno);
0437 }
0438 
0439 /*
0440  * Blast some well known "safe" values to the timing registers at init or
0441  * wakeup from sleep time, before we do real calculation
0442  */
0443 static void pata_macio_default_timings(struct pata_macio_priv *priv)
0444 {
0445     unsigned int value, value2 = 0;
0446 
0447     switch(priv->kind) {
0448         case controller_sh_ata6:
0449             value = 0x0a820c97;
0450             value2 = 0x00033031;
0451             break;
0452         case controller_un_ata6:
0453         case controller_k2_ata6:
0454             value = 0x08618a92;
0455             value2 = 0x00002921;
0456             break;
0457         case controller_kl_ata4:
0458             value = 0x0008438c;
0459             break;
0460         case controller_kl_ata3:
0461             value = 0x00084526;
0462             break;
0463         case controller_heathrow:
0464         case controller_ohare:
0465         default:
0466             value = 0x00074526;
0467             break;
0468     }
0469     priv->treg[0][0] = priv->treg[1][0] = value;
0470     priv->treg[0][1] = priv->treg[1][1] = value2;
0471 }
0472 
0473 static int pata_macio_cable_detect(struct ata_port *ap)
0474 {
0475     struct pata_macio_priv *priv = ap->private_data;
0476 
0477     /* Get cable type from device-tree */
0478     if (priv->kind == controller_kl_ata4 ||
0479         priv->kind == controller_un_ata6 ||
0480         priv->kind == controller_k2_ata6 ||
0481         priv->kind == controller_sh_ata6) {
0482         const char* cable = of_get_property(priv->node, "cable-type",
0483                             NULL);
0484         struct device_node *root = of_find_node_by_path("/");
0485         const char *model = of_get_property(root, "model", NULL);
0486 
0487         of_node_put(root);
0488 
0489         if (cable && !strncmp(cable, "80-", 3)) {
0490             /* Some drives fail to detect 80c cable in PowerBook
0491              * These machine use proprietary short IDE cable
0492              * anyway
0493              */
0494             if (!strncmp(model, "PowerBook", 9))
0495                 return ATA_CBL_PATA40_SHORT;
0496             else
0497                 return ATA_CBL_PATA80;
0498         }
0499     }
0500 
0501     /* G5's seem to have incorrect cable type in device-tree.
0502      * Let's assume they always have a 80 conductor cable, this seem to
0503      * be always the case unless the user mucked around
0504      */
0505     if (of_device_is_compatible(priv->node, "K2-UATA") ||
0506         of_device_is_compatible(priv->node, "shasta-ata"))
0507         return ATA_CBL_PATA80;
0508 
0509     /* Anything else is 40 connectors */
0510     return ATA_CBL_PATA40;
0511 }
0512 
0513 static enum ata_completion_errors pata_macio_qc_prep(struct ata_queued_cmd *qc)
0514 {
0515     unsigned int write = (qc->tf.flags & ATA_TFLAG_WRITE);
0516     struct ata_port *ap = qc->ap;
0517     struct pata_macio_priv *priv = ap->private_data;
0518     struct scatterlist *sg;
0519     struct dbdma_cmd *table;
0520     unsigned int si, pi;
0521 
0522     dev_dbgdma(priv->dev, "%s: qc %p flags %lx, write %d dev %d\n",
0523            __func__, qc, qc->flags, write, qc->dev->devno);
0524 
0525     if (!(qc->flags & ATA_QCFLAG_DMAMAP))
0526         return AC_ERR_OK;
0527 
0528     table = (struct dbdma_cmd *) priv->dma_table_cpu;
0529 
0530     pi = 0;
0531     for_each_sg(qc->sg, sg, qc->n_elem, si) {
0532         u32 addr, sg_len, len;
0533 
0534         /* determine if physical DMA addr spans 64K boundary.
0535          * Note h/w doesn't support 64-bit, so we unconditionally
0536          * truncate dma_addr_t to u32.
0537          */
0538         addr = (u32) sg_dma_address(sg);
0539         sg_len = sg_dma_len(sg);
0540 
0541         while (sg_len) {
0542             /* table overflow should never happen */
0543             BUG_ON (pi++ >= MAX_DCMDS);
0544 
0545             len = (sg_len < MAX_DBDMA_SEG) ? sg_len : MAX_DBDMA_SEG;
0546             table->command = cpu_to_le16(write ? OUTPUT_MORE: INPUT_MORE);
0547             table->req_count = cpu_to_le16(len);
0548             table->phy_addr = cpu_to_le32(addr);
0549             table->cmd_dep = 0;
0550             table->xfer_status = 0;
0551             table->res_count = 0;
0552             addr += len;
0553             sg_len -= len;
0554             ++table;
0555         }
0556     }
0557 
0558     /* Should never happen according to Tejun */
0559     BUG_ON(!pi);
0560 
0561     /* Convert the last command to an input/output */
0562     table--;
0563     table->command = cpu_to_le16(write ? OUTPUT_LAST: INPUT_LAST);
0564     table++;
0565 
0566     /* Add the stop command to the end of the list */
0567     memset(table, 0, sizeof(struct dbdma_cmd));
0568     table->command = cpu_to_le16(DBDMA_STOP);
0569 
0570     dev_dbgdma(priv->dev, "%s: %d DMA list entries\n", __func__, pi);
0571 
0572     return AC_ERR_OK;
0573 }
0574 
0575 
0576 static void pata_macio_freeze(struct ata_port *ap)
0577 {
0578     struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
0579 
0580     if (dma_regs) {
0581         unsigned int timeout = 1000000;
0582 
0583         /* Make sure DMA controller is stopped */
0584         writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma_regs->control);
0585         while (--timeout && (readl(&dma_regs->status) & RUN))
0586             udelay(1);
0587     }
0588 
0589     ata_sff_freeze(ap);
0590 }
0591 
0592 
0593 static void pata_macio_bmdma_setup(struct ata_queued_cmd *qc)
0594 {
0595     struct ata_port *ap = qc->ap;
0596     struct pata_macio_priv *priv = ap->private_data;
0597     struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
0598     int dev = qc->dev->devno;
0599 
0600     dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
0601 
0602     /* Make sure DMA commands updates are visible */
0603     writel(priv->dma_table_dma, &dma_regs->cmdptr);
0604 
0605     /* On KeyLargo 66Mhz cell, we need to add 60ns to wrDataSetup on
0606      * UDMA reads
0607      */
0608     if (priv->kind == controller_kl_ata4 &&
0609         (priv->treg[dev][0] & TR_66_UDMA_EN)) {
0610         void __iomem *rbase = ap->ioaddr.cmd_addr;
0611         u32 reg = priv->treg[dev][0];
0612 
0613         if (!(qc->tf.flags & ATA_TFLAG_WRITE))
0614             reg += 0x00800000;
0615         writel(reg, rbase + IDE_TIMING_CONFIG);
0616     }
0617 
0618     /* issue r/w command */
0619     ap->ops->sff_exec_command(ap, &qc->tf);
0620 }
0621 
0622 static void pata_macio_bmdma_start(struct ata_queued_cmd *qc)
0623 {
0624     struct ata_port *ap = qc->ap;
0625     struct pata_macio_priv *priv = ap->private_data;
0626     struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
0627 
0628     dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
0629 
0630     writel((RUN << 16) | RUN, &dma_regs->control);
0631     /* Make sure it gets to the controller right now */
0632     (void)readl(&dma_regs->control);
0633 }
0634 
0635 static void pata_macio_bmdma_stop(struct ata_queued_cmd *qc)
0636 {
0637     struct ata_port *ap = qc->ap;
0638     struct pata_macio_priv *priv = ap->private_data;
0639     struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
0640     unsigned int timeout = 1000000;
0641 
0642     dev_dbgdma(priv->dev, "%s: qc %p\n", __func__, qc);
0643 
0644     /* Stop the DMA engine and wait for it to full halt */
0645     writel (((RUN|WAKE|DEAD) << 16), &dma_regs->control);
0646     while (--timeout && (readl(&dma_regs->status) & RUN))
0647         udelay(1);
0648 }
0649 
0650 static u8 pata_macio_bmdma_status(struct ata_port *ap)
0651 {
0652     struct pata_macio_priv *priv = ap->private_data;
0653     struct dbdma_regs __iomem *dma_regs = ap->ioaddr.bmdma_addr;
0654     u32 dstat, rstat = ATA_DMA_INTR;
0655     unsigned long timeout = 0;
0656 
0657     dstat = readl(&dma_regs->status);
0658 
0659     dev_dbgdma(priv->dev, "%s: dstat=%x\n", __func__, dstat);
0660 
0661     /* We have two things to deal with here:
0662      *
0663      * - The dbdma won't stop if the command was started
0664      * but completed with an error without transferring all
0665      * datas. This happens when bad blocks are met during
0666      * a multi-block transfer.
0667      *
0668      * - The dbdma fifo hasn't yet finished flushing to
0669      * to system memory when the disk interrupt occurs.
0670      *
0671      */
0672 
0673     /* First check for errors */
0674     if ((dstat & (RUN|DEAD)) != RUN)
0675         rstat |= ATA_DMA_ERR;
0676 
0677     /* If ACTIVE is cleared, the STOP command has been hit and
0678      * the transfer is complete. If not, we have to flush the
0679      * channel.
0680      */
0681     if ((dstat & ACTIVE) == 0)
0682         return rstat;
0683 
0684     dev_dbgdma(priv->dev, "%s: DMA still active, flushing...\n", __func__);
0685 
0686     /* If dbdma didn't execute the STOP command yet, the
0687      * active bit is still set. We consider that we aren't
0688      * sharing interrupts (which is hopefully the case with
0689      * those controllers) and so we just try to flush the
0690      * channel for pending data in the fifo
0691      */
0692     udelay(1);
0693     writel((FLUSH << 16) | FLUSH, &dma_regs->control);
0694     for (;;) {
0695         udelay(1);
0696         dstat = readl(&dma_regs->status);
0697         if ((dstat & FLUSH) == 0)
0698             break;
0699         if (++timeout > 1000) {
0700             dev_warn(priv->dev, "timeout flushing DMA\n");
0701             rstat |= ATA_DMA_ERR;
0702             break;
0703         }
0704     }
0705     return rstat;
0706 }
0707 
0708 /* port_start is when we allocate the DMA command list */
0709 static int pata_macio_port_start(struct ata_port *ap)
0710 {
0711     struct pata_macio_priv *priv = ap->private_data;
0712 
0713     if (ap->ioaddr.bmdma_addr == NULL)
0714         return 0;
0715 
0716     /* Allocate space for the DBDMA commands.
0717      *
0718      * The +2 is +1 for the stop command and +1 to allow for
0719      * aligning the start address to a multiple of 16 bytes.
0720      */
0721     priv->dma_table_cpu =
0722         dmam_alloc_coherent(priv->dev,
0723                     (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
0724                     &priv->dma_table_dma, GFP_KERNEL);
0725     if (priv->dma_table_cpu == NULL) {
0726         dev_err(priv->dev, "Unable to allocate DMA command list\n");
0727         ap->ioaddr.bmdma_addr = NULL;
0728         ap->mwdma_mask = 0;
0729         ap->udma_mask = 0;
0730     }
0731     return 0;
0732 }
0733 
0734 static void pata_macio_irq_clear(struct ata_port *ap)
0735 {
0736     struct pata_macio_priv *priv = ap->private_data;
0737 
0738     /* Nothing to do here */
0739 
0740     dev_dbgdma(priv->dev, "%s\n", __func__);
0741 }
0742 
0743 static void pata_macio_reset_hw(struct pata_macio_priv *priv, int resume)
0744 {
0745     dev_dbg(priv->dev, "Enabling & resetting... \n");
0746 
0747     if (priv->mediabay)
0748         return;
0749 
0750     if (priv->kind == controller_ohare && !resume) {
0751         /* The code below is having trouble on some ohare machines
0752          * (timing related ?). Until I can put my hand on one of these
0753          * units, I keep the old way
0754          */
0755         ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node, 0, 1);
0756     } else {
0757         int rc;
0758 
0759         /* Reset and enable controller */
0760         rc = ppc_md.feature_call(PMAC_FTR_IDE_RESET,
0761                      priv->node, priv->aapl_bus_id, 1);
0762         ppc_md.feature_call(PMAC_FTR_IDE_ENABLE,
0763                     priv->node, priv->aapl_bus_id, 1);
0764         msleep(10);
0765         /* Only bother waiting if there's a reset control */
0766         if (rc == 0) {
0767             ppc_md.feature_call(PMAC_FTR_IDE_RESET,
0768                         priv->node, priv->aapl_bus_id, 0);
0769             msleep(IDE_WAKEUP_DELAY_MS);
0770         }
0771     }
0772 
0773     /* If resuming a PCI device, restore the config space here */
0774     if (priv->pdev && resume) {
0775         int rc;
0776 
0777         pci_restore_state(priv->pdev);
0778         rc = pcim_enable_device(priv->pdev);
0779         if (rc)
0780             dev_err(&priv->pdev->dev,
0781                 "Failed to enable device after resume (%d)\n",
0782                 rc);
0783         else
0784             pci_set_master(priv->pdev);
0785     }
0786 
0787     /* On Kauai, initialize the FCR. We don't perform a reset, doesn't really
0788      * seem necessary and speeds up the boot process
0789      */
0790     if (priv->kauai_fcr)
0791         writel(KAUAI_FCR_UATA_MAGIC |
0792                KAUAI_FCR_UATA_RESET_N |
0793                KAUAI_FCR_UATA_ENABLE, priv->kauai_fcr);
0794 }
0795 
0796 /* Hook the standard slave config to fixup some HW related alignment
0797  * restrictions
0798  */
0799 static int pata_macio_slave_config(struct scsi_device *sdev)
0800 {
0801     struct ata_port *ap = ata_shost_to_port(sdev->host);
0802     struct pata_macio_priv *priv = ap->private_data;
0803     struct ata_device *dev;
0804     u16 cmd;
0805     int rc;
0806 
0807     /* First call original */
0808     rc = ata_scsi_slave_config(sdev);
0809     if (rc)
0810         return rc;
0811 
0812     /* This is lifted from sata_nv */
0813     dev = &ap->link.device[sdev->id];
0814 
0815     /* OHare has issues with non cache aligned DMA on some chipsets */
0816     if (priv->kind == controller_ohare) {
0817         blk_queue_update_dma_alignment(sdev->request_queue, 31);
0818         blk_queue_update_dma_pad(sdev->request_queue, 31);
0819 
0820         /* Tell the world about it */
0821         ata_dev_info(dev, "OHare alignment limits applied\n");
0822         return 0;
0823     }
0824 
0825     /* We only have issues with ATAPI */
0826     if (dev->class != ATA_DEV_ATAPI)
0827         return 0;
0828 
0829     /* Shasta and K2 seem to have "issues" with reads ... */
0830     if (priv->kind == controller_sh_ata6 || priv->kind == controller_k2_ata6) {
0831         /* Allright these are bad, apply restrictions */
0832         blk_queue_update_dma_alignment(sdev->request_queue, 15);
0833         blk_queue_update_dma_pad(sdev->request_queue, 15);
0834 
0835         /* We enable MWI and hack cache line size directly here, this
0836          * is specific to this chipset and not normal values, we happen
0837          * to somewhat know what we are doing here (which is basically
0838          * to do the same Apple does and pray they did not get it wrong :-)
0839          */
0840         BUG_ON(!priv->pdev);
0841         pci_write_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, 0x08);
0842         pci_read_config_word(priv->pdev, PCI_COMMAND, &cmd);
0843         pci_write_config_word(priv->pdev, PCI_COMMAND,
0844                       cmd | PCI_COMMAND_INVALIDATE);
0845 
0846         /* Tell the world about it */
0847         ata_dev_info(dev, "K2/Shasta alignment limits applied\n");
0848     }
0849 
0850     return 0;
0851 }
0852 
0853 #ifdef CONFIG_PM_SLEEP
0854 static int pata_macio_do_suspend(struct pata_macio_priv *priv, pm_message_t mesg)
0855 {
0856     /* First, core libata suspend to do most of the work */
0857     ata_host_suspend(priv->host, mesg);
0858 
0859     /* Restore to default timings */
0860     pata_macio_default_timings(priv);
0861 
0862     /* Mask interrupt. Not strictly necessary but old driver did
0863      * it and I'd rather not change that here */
0864     disable_irq(priv->irq);
0865 
0866     /* The media bay will handle itself just fine */
0867     if (priv->mediabay)
0868         return 0;
0869 
0870     /* Kauai has bus control FCRs directly here */
0871     if (priv->kauai_fcr) {
0872         u32 fcr = readl(priv->kauai_fcr);
0873         fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
0874         writel(fcr, priv->kauai_fcr);
0875     }
0876 
0877     /* For PCI, save state and disable DMA. No need to call
0878      * pci_set_power_state(), the HW doesn't do D states that
0879      * way, the platform code will take care of suspending the
0880      * ASIC properly
0881      */
0882     if (priv->pdev) {
0883         pci_save_state(priv->pdev);
0884         pci_disable_device(priv->pdev);
0885     }
0886 
0887     /* Disable the bus on older machines and the cell on kauai */
0888     ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, priv->node,
0889                 priv->aapl_bus_id, 0);
0890 
0891     return 0;
0892 }
0893 
0894 static int pata_macio_do_resume(struct pata_macio_priv *priv)
0895 {
0896     /* Reset and re-enable the HW */
0897     pata_macio_reset_hw(priv, 1);
0898 
0899     /* Sanitize drive timings */
0900     pata_macio_apply_timings(priv->host->ports[0], 0);
0901 
0902     /* We want our IRQ back ! */
0903     enable_irq(priv->irq);
0904 
0905     /* Let the libata core take it from there */
0906     ata_host_resume(priv->host);
0907 
0908     return 0;
0909 }
0910 #endif /* CONFIG_PM_SLEEP */
0911 
0912 static struct scsi_host_template pata_macio_sht = {
0913     __ATA_BASE_SHT(DRV_NAME),
0914     .sg_tablesize       = MAX_DCMDS,
0915     /* We may not need that strict one */
0916     .dma_boundary       = ATA_DMA_BOUNDARY,
0917     /* Not sure what the real max is but we know it's less than 64K, let's
0918      * use 64K minus 256
0919      */
0920     .max_segment_size   = MAX_DBDMA_SEG,
0921     .slave_configure    = pata_macio_slave_config,
0922     .sdev_groups        = ata_common_sdev_groups,
0923     .can_queue      = ATA_DEF_QUEUE,
0924     .tag_alloc_policy   = BLK_TAG_ALLOC_RR,
0925 };
0926 
0927 static struct ata_port_operations pata_macio_ops = {
0928     .inherits       = &ata_bmdma_port_ops,
0929 
0930     .freeze         = pata_macio_freeze,
0931     .set_piomode        = pata_macio_set_timings,
0932     .set_dmamode        = pata_macio_set_timings,
0933     .cable_detect       = pata_macio_cable_detect,
0934     .sff_dev_select     = pata_macio_dev_select,
0935     .qc_prep        = pata_macio_qc_prep,
0936     .bmdma_setup        = pata_macio_bmdma_setup,
0937     .bmdma_start        = pata_macio_bmdma_start,
0938     .bmdma_stop     = pata_macio_bmdma_stop,
0939     .bmdma_status       = pata_macio_bmdma_status,
0940     .port_start     = pata_macio_port_start,
0941     .sff_irq_clear      = pata_macio_irq_clear,
0942 };
0943 
0944 static void pata_macio_invariants(struct pata_macio_priv *priv)
0945 {
0946     const int *bidp;
0947 
0948     /* Identify the type of controller */
0949     if (of_device_is_compatible(priv->node, "shasta-ata")) {
0950         priv->kind = controller_sh_ata6;
0951             priv->timings = pata_macio_shasta_timings;
0952     } else if (of_device_is_compatible(priv->node, "kauai-ata")) {
0953         priv->kind = controller_un_ata6;
0954             priv->timings = pata_macio_kauai_timings;
0955     } else if (of_device_is_compatible(priv->node, "K2-UATA")) {
0956         priv->kind = controller_k2_ata6;
0957             priv->timings = pata_macio_kauai_timings;
0958     } else if (of_device_is_compatible(priv->node, "keylargo-ata")) {
0959         if (of_node_name_eq(priv->node, "ata-4")) {
0960             priv->kind = controller_kl_ata4;
0961             priv->timings = pata_macio_kl66_timings;
0962         } else {
0963             priv->kind = controller_kl_ata3;
0964             priv->timings = pata_macio_kl33_timings;
0965         }
0966     } else if (of_device_is_compatible(priv->node, "heathrow-ata")) {
0967         priv->kind = controller_heathrow;
0968         priv->timings = pata_macio_heathrow_timings;
0969     } else {
0970         priv->kind = controller_ohare;
0971         priv->timings = pata_macio_ohare_timings;
0972     }
0973 
0974     /* XXX FIXME --- setup priv->mediabay here */
0975 
0976     /* Get Apple bus ID (for clock and ASIC control) */
0977     bidp = of_get_property(priv->node, "AAPL,bus-id", NULL);
0978     priv->aapl_bus_id =  bidp ? *bidp : 0;
0979 
0980     /* Fixup missing Apple bus ID in case of media-bay */
0981     if (priv->mediabay && !bidp)
0982         priv->aapl_bus_id = 1;
0983 }
0984 
0985 static void pata_macio_setup_ios(struct ata_ioports *ioaddr,
0986                  void __iomem * base, void __iomem * dma)
0987 {
0988     /* cmd_addr is the base of regs for that port */
0989     ioaddr->cmd_addr    = base;
0990 
0991     /* taskfile registers */
0992     ioaddr->data_addr   = base + (ATA_REG_DATA    << 4);
0993     ioaddr->error_addr  = base + (ATA_REG_ERR     << 4);
0994     ioaddr->feature_addr    = base + (ATA_REG_FEATURE << 4);
0995     ioaddr->nsect_addr  = base + (ATA_REG_NSECT   << 4);
0996     ioaddr->lbal_addr   = base + (ATA_REG_LBAL    << 4);
0997     ioaddr->lbam_addr   = base + (ATA_REG_LBAM    << 4);
0998     ioaddr->lbah_addr   = base + (ATA_REG_LBAH    << 4);
0999     ioaddr->device_addr = base + (ATA_REG_DEVICE  << 4);
1000     ioaddr->status_addr = base + (ATA_REG_STATUS  << 4);
1001     ioaddr->command_addr    = base + (ATA_REG_CMD     << 4);
1002     ioaddr->altstatus_addr  = base + 0x160;
1003     ioaddr->ctl_addr    = base + 0x160;
1004     ioaddr->bmdma_addr  = dma;
1005 }
1006 
1007 static void pmac_macio_calc_timing_masks(struct pata_macio_priv *priv,
1008                      struct ata_port_info *pinfo)
1009 {
1010     int i = 0;
1011 
1012     pinfo->pio_mask     = 0;
1013     pinfo->mwdma_mask   = 0;
1014     pinfo->udma_mask    = 0;
1015 
1016     while (priv->timings[i].mode > 0) {
1017         unsigned int mask = 1U << (priv->timings[i].mode & 0x0f);
1018         switch(priv->timings[i].mode & 0xf0) {
1019         case 0x00: /* PIO */
1020             pinfo->pio_mask |= (mask >> 8);
1021             break;
1022         case 0x20: /* MWDMA */
1023             pinfo->mwdma_mask |= mask;
1024             break;
1025         case 0x40: /* UDMA */
1026             pinfo->udma_mask |= mask;
1027             break;
1028         }
1029         i++;
1030     }
1031     dev_dbg(priv->dev, "Supported masks: PIO=%x, MWDMA=%x, UDMA=%x\n",
1032         pinfo->pio_mask, pinfo->mwdma_mask, pinfo->udma_mask);
1033 }
1034 
1035 static int pata_macio_common_init(struct pata_macio_priv *priv,
1036                   resource_size_t tfregs,
1037                   resource_size_t dmaregs,
1038                   resource_size_t fcregs,
1039                   unsigned long irq)
1040 {
1041     struct ata_port_info        pinfo;
1042     const struct ata_port_info  *ppi[] = { &pinfo, NULL };
1043     void __iomem            *dma_regs = NULL;
1044 
1045     /* Fill up privates with various invariants collected from the
1046      * device-tree
1047      */
1048     pata_macio_invariants(priv);
1049 
1050     /* Make sure we have sane initial timings in the cache */
1051     pata_macio_default_timings(priv);
1052 
1053     /* Allocate libata host for 1 port */
1054     memset(&pinfo, 0, sizeof(struct ata_port_info));
1055     pmac_macio_calc_timing_masks(priv, &pinfo);
1056     pinfo.flags     = ATA_FLAG_SLAVE_POSS;
1057     pinfo.port_ops      = &pata_macio_ops;
1058     pinfo.private_data  = priv;
1059 
1060     priv->host = ata_host_alloc_pinfo(priv->dev, ppi, 1);
1061     if (priv->host == NULL) {
1062         dev_err(priv->dev, "Failed to allocate ATA port structure\n");
1063         return -ENOMEM;
1064     }
1065 
1066     /* Setup the private data in host too */
1067     priv->host->private_data = priv;
1068 
1069     /* Map base registers */
1070     priv->tfregs = devm_ioremap(priv->dev, tfregs, 0x100);
1071     if (priv->tfregs == NULL) {
1072         dev_err(priv->dev, "Failed to map ATA ports\n");
1073         return -ENOMEM;
1074     }
1075     priv->host->iomap = &priv->tfregs;
1076 
1077     /* Map DMA regs */
1078     if (dmaregs != 0) {
1079         dma_regs = devm_ioremap(priv->dev, dmaregs,
1080                     sizeof(struct dbdma_regs));
1081         if (dma_regs == NULL)
1082             dev_warn(priv->dev, "Failed to map ATA DMA registers\n");
1083     }
1084 
1085     /* If chip has local feature control, map those regs too */
1086     if (fcregs != 0) {
1087         priv->kauai_fcr = devm_ioremap(priv->dev, fcregs, 4);
1088         if (priv->kauai_fcr == NULL) {
1089             dev_err(priv->dev, "Failed to map ATA FCR register\n");
1090             return -ENOMEM;
1091         }
1092     }
1093 
1094     /* Setup port data structure */
1095     pata_macio_setup_ios(&priv->host->ports[0]->ioaddr,
1096                  priv->tfregs, dma_regs);
1097     priv->host->ports[0]->private_data = priv;
1098 
1099     /* hard-reset the controller */
1100     pata_macio_reset_hw(priv, 0);
1101     pata_macio_apply_timings(priv->host->ports[0], 0);
1102 
1103     /* Enable bus master if necessary */
1104     if (priv->pdev && dma_regs)
1105         pci_set_master(priv->pdev);
1106 
1107     dev_info(priv->dev, "Activating pata-macio chipset %s, Apple bus ID %d\n",
1108          macio_ata_names[priv->kind], priv->aapl_bus_id);
1109 
1110     /* Start it up */
1111     priv->irq = irq;
1112     return ata_host_activate(priv->host, irq, ata_bmdma_interrupt, 0,
1113                  &pata_macio_sht);
1114 }
1115 
1116 static int pata_macio_attach(struct macio_dev *mdev,
1117                  const struct of_device_id *match)
1118 {
1119     struct pata_macio_priv  *priv;
1120     resource_size_t     tfregs, dmaregs = 0;
1121     unsigned long       irq;
1122     int         rc;
1123 
1124     /* Check for broken device-trees */
1125     if (macio_resource_count(mdev) == 0) {
1126         dev_err(&mdev->ofdev.dev,
1127             "No addresses for controller\n");
1128         return -ENXIO;
1129     }
1130 
1131     /* Enable managed resources */
1132     macio_enable_devres(mdev);
1133 
1134     /* Allocate and init private data structure */
1135     priv = devm_kzalloc(&mdev->ofdev.dev,
1136                 sizeof(struct pata_macio_priv), GFP_KERNEL);
1137     if (!priv)
1138         return -ENOMEM;
1139 
1140     priv->node = of_node_get(mdev->ofdev.dev.of_node);
1141     priv->mdev = mdev;
1142     priv->dev = &mdev->ofdev.dev;
1143 
1144     /* Request memory resource for taskfile registers */
1145     if (macio_request_resource(mdev, 0, "pata-macio")) {
1146         dev_err(&mdev->ofdev.dev,
1147             "Cannot obtain taskfile resource\n");
1148         return -EBUSY;
1149     }
1150     tfregs = macio_resource_start(mdev, 0);
1151 
1152     /* Request resources for DMA registers if any */
1153     if (macio_resource_count(mdev) >= 2) {
1154         if (macio_request_resource(mdev, 1, "pata-macio-dma"))
1155             dev_err(&mdev->ofdev.dev,
1156                 "Cannot obtain DMA resource\n");
1157         else
1158             dmaregs = macio_resource_start(mdev, 1);
1159     }
1160 
1161     /*
1162      * Fixup missing IRQ for some old implementations with broken
1163      * device-trees.
1164      *
1165      * This is a bit bogus, it should be fixed in the device-tree itself,
1166      * via the existing macio fixups, based on the type of interrupt
1167      * controller in the machine. However, I have no test HW for this case,
1168      * and this trick works well enough on those old machines...
1169      */
1170     if (macio_irq_count(mdev) == 0) {
1171         dev_warn(&mdev->ofdev.dev,
1172              "No interrupts for controller, using 13\n");
1173         irq = irq_create_mapping(NULL, 13);
1174     } else
1175         irq = macio_irq(mdev, 0);
1176 
1177     /* Prevvent media bay callbacks until fully registered */
1178     lock_media_bay(priv->mdev->media_bay);
1179 
1180     /* Get register addresses and call common initialization */
1181     rc = pata_macio_common_init(priv,
1182                     tfregs,     /* Taskfile regs */
1183                     dmaregs,        /* DBDMA regs */
1184                     0,          /* Feature control */
1185                     irq);
1186     unlock_media_bay(priv->mdev->media_bay);
1187 
1188     return rc;
1189 }
1190 
1191 static int pata_macio_detach(struct macio_dev *mdev)
1192 {
1193     struct ata_host *host = macio_get_drvdata(mdev);
1194     struct pata_macio_priv *priv = host->private_data;
1195 
1196     lock_media_bay(priv->mdev->media_bay);
1197 
1198     /* Make sure the mediabay callback doesn't try to access
1199      * dead stuff
1200      */
1201     priv->host->private_data = NULL;
1202 
1203     ata_host_detach(host);
1204 
1205     unlock_media_bay(priv->mdev->media_bay);
1206 
1207     return 0;
1208 }
1209 
1210 #ifdef CONFIG_PM_SLEEP
1211 static int pata_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1212 {
1213     struct ata_host *host = macio_get_drvdata(mdev);
1214 
1215     return pata_macio_do_suspend(host->private_data, mesg);
1216 }
1217 
1218 static int pata_macio_resume(struct macio_dev *mdev)
1219 {
1220     struct ata_host *host = macio_get_drvdata(mdev);
1221 
1222     return pata_macio_do_resume(host->private_data);
1223 }
1224 #endif /* CONFIG_PM_SLEEP */
1225 
1226 #ifdef CONFIG_PMAC_MEDIABAY
1227 static void pata_macio_mb_event(struct macio_dev* mdev, int mb_state)
1228 {
1229     struct ata_host *host = macio_get_drvdata(mdev);
1230     struct ata_port *ap;
1231     struct ata_eh_info *ehi;
1232     struct ata_device *dev;
1233     unsigned long flags;
1234 
1235     if (!host || !host->private_data)
1236         return;
1237     ap = host->ports[0];
1238     spin_lock_irqsave(ap->lock, flags);
1239     ehi = &ap->link.eh_info;
1240     if (mb_state == MB_CD) {
1241         ata_ehi_push_desc(ehi, "mediabay plug");
1242         ata_ehi_hotplugged(ehi);
1243         ata_port_freeze(ap);
1244     } else {
1245         ata_ehi_push_desc(ehi, "mediabay unplug");
1246         ata_for_each_dev(dev, &ap->link, ALL)
1247             dev->flags |= ATA_DFLAG_DETACH;
1248         ata_port_abort(ap);
1249     }
1250     spin_unlock_irqrestore(ap->lock, flags);
1251 
1252 }
1253 #endif /* CONFIG_PMAC_MEDIABAY */
1254 
1255 
1256 static int pata_macio_pci_attach(struct pci_dev *pdev,
1257                  const struct pci_device_id *id)
1258 {
1259     struct pata_macio_priv  *priv;
1260     struct device_node  *np;
1261     resource_size_t     rbase;
1262 
1263     /* We cannot use a MacIO controller without its OF device node */
1264     np = pci_device_to_OF_node(pdev);
1265     if (np == NULL) {
1266         dev_err(&pdev->dev,
1267             "Cannot find OF device node for controller\n");
1268         return -ENODEV;
1269     }
1270 
1271     /* Check that it can be enabled */
1272     if (pcim_enable_device(pdev)) {
1273         dev_err(&pdev->dev,
1274             "Cannot enable controller PCI device\n");
1275         return -ENXIO;
1276     }
1277 
1278     /* Allocate and init private data structure */
1279     priv = devm_kzalloc(&pdev->dev,
1280                 sizeof(struct pata_macio_priv), GFP_KERNEL);
1281     if (!priv)
1282         return -ENOMEM;
1283 
1284     priv->node = of_node_get(np);
1285     priv->pdev = pdev;
1286     priv->dev = &pdev->dev;
1287 
1288     /* Get MMIO regions */
1289     if (pci_request_regions(pdev, "pata-macio")) {
1290         dev_err(&pdev->dev,
1291             "Cannot obtain PCI resources\n");
1292         return -EBUSY;
1293     }
1294 
1295     /* Get register addresses and call common initialization */
1296     rbase = pci_resource_start(pdev, 0);
1297     if (pata_macio_common_init(priv,
1298                    rbase + 0x2000,  /* Taskfile regs */
1299                    rbase + 0x1000,  /* DBDMA regs */
1300                    rbase,       /* Feature control */
1301                    pdev->irq))
1302         return -ENXIO;
1303 
1304     return 0;
1305 }
1306 
1307 static void pata_macio_pci_detach(struct pci_dev *pdev)
1308 {
1309     struct ata_host *host = pci_get_drvdata(pdev);
1310 
1311     ata_host_detach(host);
1312 }
1313 
1314 #ifdef CONFIG_PM_SLEEP
1315 static int pata_macio_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1316 {
1317     struct ata_host *host = pci_get_drvdata(pdev);
1318 
1319     return pata_macio_do_suspend(host->private_data, mesg);
1320 }
1321 
1322 static int pata_macio_pci_resume(struct pci_dev *pdev)
1323 {
1324     struct ata_host *host = pci_get_drvdata(pdev);
1325 
1326     return pata_macio_do_resume(host->private_data);
1327 }
1328 #endif /* CONFIG_PM_SLEEP */
1329 
1330 static const struct of_device_id pata_macio_match[] =
1331 {
1332     { .name = "IDE", },
1333     { .name = "ATA", },
1334     { .type = "ide", },
1335     { .type = "ata", },
1336     { /* sentinel */ }
1337 };
1338 MODULE_DEVICE_TABLE(of, pata_macio_match);
1339 
1340 static struct macio_driver pata_macio_driver =
1341 {
1342     .driver = {
1343         .name       = "pata-macio",
1344         .owner      = THIS_MODULE,
1345         .of_match_table = pata_macio_match,
1346     },
1347     .probe      = pata_macio_attach,
1348     .remove     = pata_macio_detach,
1349 #ifdef CONFIG_PM_SLEEP
1350     .suspend    = pata_macio_suspend,
1351     .resume     = pata_macio_resume,
1352 #endif
1353 #ifdef CONFIG_PMAC_MEDIABAY
1354     .mediabay_event = pata_macio_mb_event,
1355 #endif
1356 };
1357 
1358 static const struct pci_device_id pata_macio_pci_match[] = {
1359     { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA),    0 },
1360     { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100),  0 },
1361     { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100),    0 },
1362     { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA),   0 },
1363     { PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA),    0 },
1364     {},
1365 };
1366 
1367 static struct pci_driver pata_macio_pci_driver = {
1368     .name       = "pata-pci-macio",
1369     .id_table   = pata_macio_pci_match,
1370     .probe      = pata_macio_pci_attach,
1371     .remove     = pata_macio_pci_detach,
1372 #ifdef CONFIG_PM_SLEEP
1373     .suspend    = pata_macio_pci_suspend,
1374     .resume     = pata_macio_pci_resume,
1375 #endif
1376     .driver = {
1377         .owner      = THIS_MODULE,
1378     },
1379 };
1380 MODULE_DEVICE_TABLE(pci, pata_macio_pci_match);
1381 
1382 
1383 static int __init pata_macio_init(void)
1384 {
1385     int rc;
1386 
1387     if (!machine_is(powermac))
1388         return -ENODEV;
1389 
1390     rc = pci_register_driver(&pata_macio_pci_driver);
1391     if (rc)
1392         return rc;
1393     rc = macio_register_driver(&pata_macio_driver);
1394     if (rc) {
1395         pci_unregister_driver(&pata_macio_pci_driver);
1396         return rc;
1397     }
1398     return 0;
1399 }
1400 
1401 static void __exit pata_macio_exit(void)
1402 {
1403     macio_unregister_driver(&pata_macio_driver);
1404     pci_unregister_driver(&pata_macio_pci_driver);
1405 }
1406 
1407 module_init(pata_macio_init);
1408 module_exit(pata_macio_exit);
1409 
1410 MODULE_AUTHOR("Benjamin Herrenschmidt");
1411 MODULE_DESCRIPTION("Apple MacIO PATA driver");
1412 MODULE_LICENSE("GPL");
1413 MODULE_VERSION(DRV_VERSION);
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