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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *   pata-legacy.c - Legacy port PATA/SATA controller driver.
0004  *   Copyright 2005/2006 Red Hat, all rights reserved.
0005  *
0006  *   An ATA driver for the legacy ATA ports.
0007  *
0008  *   Data Sources:
0009  *  Opti 82C465/82C611 support: Data sheets at opti-inc.com
0010  *  HT6560 series:
0011  *  Promise 20230/20620:
0012  *      http://www.ryston.cz/petr/vlb/pdc20230b.html
0013  *      http://www.ryston.cz/petr/vlb/pdc20230c.html
0014  *      http://www.ryston.cz/petr/vlb/pdc20630.html
0015  *  QDI65x0:
0016  *      http://www.ryston.cz/petr/vlb/qd6500.html
0017  *      http://www.ryston.cz/petr/vlb/qd6580.html
0018  *
0019  *  QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c
0020  *  Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by
0021  *  Samuel Thibault <samuel.thibault@ens-lyon.org>
0022  *
0023  *  Unsupported but docs exist:
0024  *  Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
0025  *
0026  *  This driver handles legacy (that is "ISA/VLB side") IDE ports found
0027  *  on PC class systems. There are three hybrid devices that are exceptions
0028  *  The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
0029  *  the MPIIX where the tuning is PCI side but the IDE is "ISA side".
0030  *
0031  *  Specific support is included for the ht6560a/ht6560b/opti82c611a/
0032  *  opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A
0033  *
0034  *  Support for the Winbond 83759A when operating in advanced mode.
0035  *  Multichip mode is not currently supported.
0036  *
0037  *  Use the autospeed and pio_mask options with:
0038  *  Appian ADI/2 aka CLPD7220 or AIC25VL01.
0039  *  Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
0040  *  Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
0041  *  Winbond W83759A, Promise PDC20230-B
0042  *
0043  *  For now use autospeed and pio_mask as above with the W83759A. This may
0044  *  change.
0045  */
0046 
0047 #include <linux/async.h>
0048 #include <linux/kernel.h>
0049 #include <linux/module.h>
0050 #include <linux/pci.h>
0051 #include <linux/init.h>
0052 #include <linux/blkdev.h>
0053 #include <linux/delay.h>
0054 #include <scsi/scsi_host.h>
0055 #include <linux/ata.h>
0056 #include <linux/libata.h>
0057 #include <linux/platform_device.h>
0058 
0059 #define DRV_NAME "pata_legacy"
0060 #define DRV_VERSION "0.6.5"
0061 
0062 #define NR_HOST 6
0063 
0064 static int all;
0065 module_param(all, int, 0444);
0066 MODULE_PARM_DESC(all,
0067          "Set to probe unclaimed pri/sec ISA port ranges even if PCI");
0068 
0069 static int probe_all;
0070 module_param(probe_all, int, 0);
0071 MODULE_PARM_DESC(probe_all,
0072          "Set to probe tertiary+ ISA port ranges even if PCI");
0073 
0074 static int probe_mask = ~0;
0075 module_param(probe_mask, int, 0);
0076 MODULE_PARM_DESC(probe_mask, "Probe mask for legacy ISA PATA ports");
0077 
0078 static int autospeed;
0079 module_param(autospeed, int, 0);
0080 MODULE_PARM_DESC(autospeed, "Chip present that snoops speed changes");
0081 
0082 static int pio_mask = ATA_PIO4;
0083 module_param(pio_mask, int, 0);
0084 MODULE_PARM_DESC(pio_mask, "PIO range for autospeed devices");
0085 
0086 static int iordy_mask = 0xFFFFFFFF;
0087 module_param(iordy_mask, int, 0);
0088 MODULE_PARM_DESC(iordy_mask, "Use IORDY if available");
0089 
0090 static int ht6560a;
0091 module_param(ht6560a, int, 0);
0092 MODULE_PARM_DESC(ht6560a, "HT 6560A on primary 1, second 2, both 3");
0093 
0094 static int ht6560b;
0095 module_param(ht6560b, int, 0);
0096 MODULE_PARM_DESC(ht6560b, "HT 6560B on primary 1, secondary 2, both 3");
0097 
0098 static int opti82c611a;
0099 module_param(opti82c611a, int, 0);
0100 MODULE_PARM_DESC(opti82c611a,
0101          "Opti 82c611A on primary 1, secondary 2, both 3");
0102 
0103 static int opti82c46x;
0104 module_param(opti82c46x, int, 0);
0105 MODULE_PARM_DESC(opti82c46x,
0106          "Opti 82c465MV on primary 1, secondary 2, both 3");
0107 
0108 #ifdef CONFIG_PATA_QDI_MODULE
0109 static int qdi = 1;
0110 #else
0111 static int qdi;
0112 #endif
0113 module_param(qdi, int, 0);
0114 MODULE_PARM_DESC(qdi, "Set to probe QDI controllers");
0115 
0116 #ifdef CONFIG_PATA_WINBOND_VLB_MODULE
0117 static int winbond = 1;
0118 #else
0119 static int winbond;
0120 #endif
0121 module_param(winbond, int, 0);
0122 MODULE_PARM_DESC(winbond,
0123          "Set to probe Winbond controllers, "
0124          "give I/O port if non standard");
0125 
0126 
0127 enum controller {
0128     BIOS = 0,
0129     SNOOP = 1,
0130     PDC20230 = 2,
0131     HT6560A = 3,
0132     HT6560B = 4,
0133     OPTI611A = 5,
0134     OPTI46X = 6,
0135     QDI6500 = 7,
0136     QDI6580 = 8,
0137     QDI6580DP = 9,      /* Dual channel mode is different */
0138     W83759A = 10,
0139 
0140     UNKNOWN = -1
0141 };
0142 
0143 struct legacy_data {
0144     unsigned long timing;
0145     u8 clock[2];
0146     u8 last;
0147     int fast;
0148     enum controller type;
0149     struct platform_device *platform_dev;
0150 };
0151 
0152 struct legacy_probe {
0153     unsigned char *name;
0154     unsigned long port;
0155     unsigned int irq;
0156     unsigned int slot;
0157     enum controller type;
0158     unsigned long private;
0159 };
0160 
0161 struct legacy_controller {
0162     const char *name;
0163     struct ata_port_operations *ops;
0164     unsigned int pio_mask;
0165     unsigned int flags;
0166     unsigned int pflags;
0167     int (*setup)(struct platform_device *, struct legacy_probe *probe,
0168         struct legacy_data *data);
0169 };
0170 
0171 static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
0172 
0173 static struct legacy_probe probe_list[NR_HOST];
0174 static struct legacy_data legacy_data[NR_HOST];
0175 static struct ata_host *legacy_host[NR_HOST];
0176 static int nr_legacy_host;
0177 
0178 
0179 /**
0180  *  legacy_probe_add    -   Add interface to probe list
0181  *  @port: Controller port
0182  *  @irq: IRQ number
0183  *  @type: Controller type
0184  *  @private: Controller specific info
0185  *
0186  *  Add an entry into the probe list for ATA controllers. This is used
0187  *  to add the default ISA slots and then to build up the table
0188  *  further according to other ISA/VLB/Weird device scans
0189  *
0190  *  An I/O port list is used to keep ordering stable and sane, as we
0191  *  don't have any good way to talk about ordering otherwise
0192  */
0193 
0194 static int legacy_probe_add(unsigned long port, unsigned int irq,
0195                 enum controller type, unsigned long private)
0196 {
0197     struct legacy_probe *lp = &probe_list[0];
0198     int i;
0199     struct legacy_probe *free = NULL;
0200 
0201     for (i = 0; i < NR_HOST; i++) {
0202         if (lp->port == 0 && free == NULL)
0203             free = lp;
0204         /* Matching port, or the correct slot for ordering */
0205         if (lp->port == port || legacy_port[i] == port) {
0206             if (!(probe_mask & 1 << i))
0207                 return -1;
0208             free = lp;
0209             break;
0210         }
0211         lp++;
0212     }
0213     if (free == NULL) {
0214         printk(KERN_ERR "pata_legacy: Too many interfaces.\n");
0215         return -1;
0216     }
0217     /* Fill in the entry for later probing */
0218     free->port = port;
0219     free->irq = irq;
0220     free->type = type;
0221     free->private = private;
0222     return 0;
0223 }
0224 
0225 
0226 /**
0227  *  legacy_set_mode     -   mode setting
0228  *  @link: IDE link
0229  *  @unused: Device that failed when error is returned
0230  *
0231  *  Use a non standard set_mode function. We don't want to be tuned.
0232  *
0233  *  The BIOS configured everything. Our job is not to fiddle. Just use
0234  *  whatever PIO the hardware is using and leave it at that. When we
0235  *  get some kind of nice user driven API for control then we can
0236  *  expand on this as per hdparm in the base kernel.
0237  */
0238 
0239 static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
0240 {
0241     struct ata_device *dev;
0242 
0243     ata_for_each_dev(dev, link, ENABLED) {
0244         ata_dev_info(dev, "configured for PIO\n");
0245         dev->pio_mode = XFER_PIO_0;
0246         dev->xfer_mode = XFER_PIO_0;
0247         dev->xfer_shift = ATA_SHIFT_PIO;
0248         dev->flags |= ATA_DFLAG_PIO;
0249     }
0250     return 0;
0251 }
0252 
0253 static struct scsi_host_template legacy_sht = {
0254     ATA_PIO_SHT(DRV_NAME),
0255 };
0256 
0257 static const struct ata_port_operations legacy_base_port_ops = {
0258     .inherits   = &ata_sff_port_ops,
0259     .cable_detect   = ata_cable_40wire,
0260 };
0261 
0262 /*
0263  *  These ops are used if the user indicates the hardware
0264  *  snoops the commands to decide on the mode and handles the
0265  *  mode selection "magically" itself. Several legacy controllers
0266  *  do this. The mode range can be set if it is not 0x1F by setting
0267  *  pio_mask as well.
0268  */
0269 
0270 static struct ata_port_operations simple_port_ops = {
0271     .inherits   = &legacy_base_port_ops,
0272     .sff_data_xfer  = ata_sff_data_xfer32,
0273 };
0274 
0275 static struct ata_port_operations legacy_port_ops = {
0276     .inherits   = &legacy_base_port_ops,
0277     .sff_data_xfer  = ata_sff_data_xfer32,
0278     .set_mode   = legacy_set_mode,
0279 };
0280 
0281 /*
0282  *  Promise 20230C and 20620 support
0283  *
0284  *  This controller supports PIO0 to PIO2. We set PIO timings
0285  *  conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA
0286  *  support is weird being DMA to controller and PIO'd to the host
0287  *  and not supported.
0288  */
0289 
0290 static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
0291 {
0292     int tries = 5;
0293     int pio = adev->pio_mode - XFER_PIO_0;
0294     u8 rt;
0295     unsigned long flags;
0296 
0297     /* Safe as UP only. Force I/Os to occur together */
0298 
0299     local_irq_save(flags);
0300 
0301     /* Unlock the control interface */
0302     do {
0303         inb(0x1F5);
0304         outb(inb(0x1F2) | 0x80, 0x1F2);
0305         inb(0x1F2);
0306         inb(0x3F6);
0307         inb(0x3F6);
0308         inb(0x1F2);
0309         inb(0x1F2);
0310     }
0311     while ((inb(0x1F2) & 0x80) && --tries);
0312 
0313     local_irq_restore(flags);
0314 
0315     outb(inb(0x1F4) & 0x07, 0x1F4);
0316 
0317     rt = inb(0x1F3);
0318     rt &= 0x07 << (3 * adev->devno);
0319     if (pio)
0320         rt |= (1 + 3 * pio) << (3 * adev->devno);
0321 
0322     udelay(100);
0323     outb(inb(0x1F2) | 0x01, 0x1F2);
0324     udelay(100);
0325     inb(0x1F5);
0326 
0327 }
0328 
0329 static unsigned int pdc_data_xfer_vlb(struct ata_queued_cmd *qc,
0330             unsigned char *buf, unsigned int buflen, int rw)
0331 {
0332     struct ata_device *dev = qc->dev;
0333     struct ata_port *ap = dev->link->ap;
0334     int slop = buflen & 3;
0335 
0336     /* 32bit I/O capable *and* we need to write a whole number of dwords */
0337     if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3)
0338                     && (ap->pflags & ATA_PFLAG_PIO32)) {
0339         unsigned long flags;
0340 
0341         local_irq_save(flags);
0342 
0343         /* Perform the 32bit I/O synchronization sequence */
0344         ioread8(ap->ioaddr.nsect_addr);
0345         ioread8(ap->ioaddr.nsect_addr);
0346         ioread8(ap->ioaddr.nsect_addr);
0347 
0348         /* Now the data */
0349         if (rw == READ)
0350             ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
0351         else
0352             iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
0353 
0354         if (unlikely(slop)) {
0355             __le32 pad = 0;
0356 
0357             if (rw == READ) {
0358                 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
0359                 memcpy(buf + buflen - slop, &pad, slop);
0360             } else {
0361                 memcpy(&pad, buf + buflen - slop, slop);
0362                 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
0363             }
0364             buflen += 4 - slop;
0365         }
0366         local_irq_restore(flags);
0367     } else
0368         buflen = ata_sff_data_xfer32(qc, buf, buflen, rw);
0369 
0370     return buflen;
0371 }
0372 
0373 static struct ata_port_operations pdc20230_port_ops = {
0374     .inherits   = &legacy_base_port_ops,
0375     .set_piomode    = pdc20230_set_piomode,
0376     .sff_data_xfer  = pdc_data_xfer_vlb,
0377 };
0378 
0379 /*
0380  *  Holtek 6560A support
0381  *
0382  *  This controller supports PIO0 to PIO2 (no IORDY even though higher
0383  *  timings can be loaded).
0384  */
0385 
0386 static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
0387 {
0388     u8 active, recover;
0389     struct ata_timing t;
0390 
0391     /* Get the timing data in cycles. For now play safe at 50Mhz */
0392     ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
0393 
0394     active = clamp_val(t.active, 2, 15);
0395     recover = clamp_val(t.recover, 4, 15);
0396 
0397     inb(0x3E6);
0398     inb(0x3E6);
0399     inb(0x3E6);
0400     inb(0x3E6);
0401 
0402     iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
0403     ioread8(ap->ioaddr.status_addr);
0404 }
0405 
0406 static struct ata_port_operations ht6560a_port_ops = {
0407     .inherits   = &legacy_base_port_ops,
0408     .set_piomode    = ht6560a_set_piomode,
0409 };
0410 
0411 /*
0412  *  Holtek 6560B support
0413  *
0414  *  This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO
0415  *  setting unless we see an ATAPI device in which case we force it off.
0416  *
0417  *  FIXME: need to implement 2nd channel support.
0418  */
0419 
0420 static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
0421 {
0422     u8 active, recover;
0423     struct ata_timing t;
0424 
0425     /* Get the timing data in cycles. For now play safe at 50Mhz */
0426     ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
0427 
0428     active = clamp_val(t.active, 2, 15);
0429     recover = clamp_val(t.recover, 2, 16) & 0x0F;
0430 
0431     inb(0x3E6);
0432     inb(0x3E6);
0433     inb(0x3E6);
0434     inb(0x3E6);
0435 
0436     iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
0437 
0438     if (adev->class != ATA_DEV_ATA) {
0439         u8 rconf = inb(0x3E6);
0440         if (rconf & 0x24) {
0441             rconf &= ~0x24;
0442             outb(rconf, 0x3E6);
0443         }
0444     }
0445     ioread8(ap->ioaddr.status_addr);
0446 }
0447 
0448 static struct ata_port_operations ht6560b_port_ops = {
0449     .inherits   = &legacy_base_port_ops,
0450     .set_piomode    = ht6560b_set_piomode,
0451 };
0452 
0453 /*
0454  *  Opti core chipset helpers
0455  */
0456 
0457 /**
0458  *  opti_syscfg -   read OPTI chipset configuration
0459  *  @reg: Configuration register to read
0460  *
0461  *  Returns the value of an OPTI system board configuration register.
0462  */
0463 
0464 static u8 opti_syscfg(u8 reg)
0465 {
0466     unsigned long flags;
0467     u8 r;
0468 
0469     /* Uniprocessor chipset and must force cycles adjancent */
0470     local_irq_save(flags);
0471     outb(reg, 0x22);
0472     r = inb(0x24);
0473     local_irq_restore(flags);
0474     return r;
0475 }
0476 
0477 /*
0478  *  Opti 82C611A
0479  *
0480  *  This controller supports PIO0 to PIO3.
0481  */
0482 
0483 static void opti82c611a_set_piomode(struct ata_port *ap,
0484                         struct ata_device *adev)
0485 {
0486     u8 active, recover, setup;
0487     struct ata_timing t;
0488     struct ata_device *pair = ata_dev_pair(adev);
0489     int clock;
0490     int khz[4] = { 50000, 40000, 33000, 25000 };
0491     u8 rc;
0492 
0493     /* Enter configuration mode */
0494     ioread16(ap->ioaddr.error_addr);
0495     ioread16(ap->ioaddr.error_addr);
0496     iowrite8(3, ap->ioaddr.nsect_addr);
0497 
0498     /* Read VLB clock strapping */
0499     clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
0500 
0501     /* Get the timing data in cycles */
0502     ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
0503 
0504     /* Setup timing is shared */
0505     if (pair) {
0506         struct ata_timing tp;
0507         ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
0508 
0509         ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
0510     }
0511 
0512     active = clamp_val(t.active, 2, 17) - 2;
0513     recover = clamp_val(t.recover, 1, 16) - 1;
0514     setup = clamp_val(t.setup, 1, 4) - 1;
0515 
0516     /* Select the right timing bank for write timing */
0517     rc = ioread8(ap->ioaddr.lbal_addr);
0518     rc &= 0x7F;
0519     rc |= (adev->devno << 7);
0520     iowrite8(rc, ap->ioaddr.lbal_addr);
0521 
0522     /* Write the timings */
0523     iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
0524 
0525     /* Select the right bank for read timings, also
0526        load the shared timings for address */
0527     rc = ioread8(ap->ioaddr.device_addr);
0528     rc &= 0xC0;
0529     rc |= adev->devno;  /* Index select */
0530     rc |= (setup << 4) | 0x04;
0531     iowrite8(rc, ap->ioaddr.device_addr);
0532 
0533     /* Load the read timings */
0534     iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
0535 
0536     /* Ensure the timing register mode is right */
0537     rc = ioread8(ap->ioaddr.lbal_addr);
0538     rc &= 0x73;
0539     rc |= 0x84;
0540     iowrite8(rc, ap->ioaddr.lbal_addr);
0541 
0542     /* Exit command mode */
0543     iowrite8(0x83,  ap->ioaddr.nsect_addr);
0544 }
0545 
0546 
0547 static struct ata_port_operations opti82c611a_port_ops = {
0548     .inherits   = &legacy_base_port_ops,
0549     .set_piomode    = opti82c611a_set_piomode,
0550 };
0551 
0552 /*
0553  *  Opti 82C465MV
0554  *
0555  *  This controller supports PIO0 to PIO3. Unlike the 611A the MVB
0556  *  version is dual channel but doesn't have a lot of unique registers.
0557  */
0558 
0559 static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
0560 {
0561     u8 active, recover, setup;
0562     struct ata_timing t;
0563     struct ata_device *pair = ata_dev_pair(adev);
0564     int clock;
0565     int khz[4] = { 50000, 40000, 33000, 25000 };
0566     u8 rc;
0567     u8 sysclk;
0568 
0569     /* Get the clock */
0570     sysclk = (opti_syscfg(0xAC) & 0xC0) >> 6;   /* BIOS set */
0571 
0572     /* Enter configuration mode */
0573     ioread16(ap->ioaddr.error_addr);
0574     ioread16(ap->ioaddr.error_addr);
0575     iowrite8(3, ap->ioaddr.nsect_addr);
0576 
0577     /* Read VLB clock strapping */
0578     clock = 1000000000 / khz[sysclk];
0579 
0580     /* Get the timing data in cycles */
0581     ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
0582 
0583     /* Setup timing is shared */
0584     if (pair) {
0585         struct ata_timing tp;
0586         ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
0587 
0588         ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
0589     }
0590 
0591     active = clamp_val(t.active, 2, 17) - 2;
0592     recover = clamp_val(t.recover, 1, 16) - 1;
0593     setup = clamp_val(t.setup, 1, 4) - 1;
0594 
0595     /* Select the right timing bank for write timing */
0596     rc = ioread8(ap->ioaddr.lbal_addr);
0597     rc &= 0x7F;
0598     rc |= (adev->devno << 7);
0599     iowrite8(rc, ap->ioaddr.lbal_addr);
0600 
0601     /* Write the timings */
0602     iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
0603 
0604     /* Select the right bank for read timings, also
0605        load the shared timings for address */
0606     rc = ioread8(ap->ioaddr.device_addr);
0607     rc &= 0xC0;
0608     rc |= adev->devno;  /* Index select */
0609     rc |= (setup << 4) | 0x04;
0610     iowrite8(rc, ap->ioaddr.device_addr);
0611 
0612     /* Load the read timings */
0613     iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
0614 
0615     /* Ensure the timing register mode is right */
0616     rc = ioread8(ap->ioaddr.lbal_addr);
0617     rc &= 0x73;
0618     rc |= 0x84;
0619     iowrite8(rc, ap->ioaddr.lbal_addr);
0620 
0621     /* Exit command mode */
0622     iowrite8(0x83,  ap->ioaddr.nsect_addr);
0623 
0624     /* We need to know this for quad device on the MVB */
0625     ap->host->private_data = ap;
0626 }
0627 
0628 /**
0629  *  opti82c46x_qc_issue     -   command issue
0630  *  @qc: command pending
0631  *
0632  *  Called when the libata layer is about to issue a command. We wrap
0633  *  this interface so that we can load the correct ATA timings. The
0634  *  MVB has a single set of timing registers and these are shared
0635  *  across channels. As there are two registers we really ought to
0636  *  track the last two used values as a sort of register window. For
0637  *  now we just reload on a channel switch. On the single channel
0638  *  setup this condition never fires so we do nothing extra.
0639  *
0640  *  FIXME: dual channel needs ->serialize support
0641  */
0642 
0643 static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc)
0644 {
0645     struct ata_port *ap = qc->ap;
0646     struct ata_device *adev = qc->dev;
0647 
0648     /* If timings are set and for the wrong channel (2nd test is
0649        due to a libata shortcoming and will eventually go I hope) */
0650     if (ap->host->private_data != ap->host
0651         && ap->host->private_data != NULL)
0652         opti82c46x_set_piomode(ap, adev);
0653 
0654     return ata_sff_qc_issue(qc);
0655 }
0656 
0657 static struct ata_port_operations opti82c46x_port_ops = {
0658     .inherits   = &legacy_base_port_ops,
0659     .set_piomode    = opti82c46x_set_piomode,
0660     .qc_issue   = opti82c46x_qc_issue,
0661 };
0662 
0663 /**
0664  *  qdi65x0_set_piomode     -   PIO setup for QDI65x0
0665  *  @ap: Port
0666  *  @adev: Device
0667  *
0668  *  In single channel mode the 6580 has one clock per device and we can
0669  *  avoid the requirement to clock switch. We also have to load the timing
0670  *  into the right clock according to whether we are master or slave.
0671  *
0672  *  In dual channel mode the 6580 has one clock per channel and we have
0673  *  to software clockswitch in qc_issue.
0674  */
0675 
0676 static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev)
0677 {
0678     struct ata_timing t;
0679     struct legacy_data *ld_qdi = ap->host->private_data;
0680     int active, recovery;
0681     u8 timing;
0682 
0683     /* Get the timing data in cycles */
0684     ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
0685 
0686     if (ld_qdi->fast) {
0687         active = 8 - clamp_val(t.active, 1, 8);
0688         recovery = 18 - clamp_val(t.recover, 3, 18);
0689     } else {
0690         active = 9 - clamp_val(t.active, 2, 9);
0691         recovery = 15 - clamp_val(t.recover, 0, 15);
0692     }
0693     timing = (recovery << 4) | active | 0x08;
0694     ld_qdi->clock[adev->devno] = timing;
0695 
0696     if (ld_qdi->type == QDI6580)
0697         outb(timing, ld_qdi->timing + 2 * adev->devno);
0698     else
0699         outb(timing, ld_qdi->timing + 2 * ap->port_no);
0700 
0701     /* Clear the FIFO */
0702     if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA)
0703         outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);
0704 }
0705 
0706 /**
0707  *  qdi_qc_issue        -   command issue
0708  *  @qc: command pending
0709  *
0710  *  Called when the libata layer is about to issue a command. We wrap
0711  *  this interface so that we can load the correct ATA timings.
0712  */
0713 
0714 static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc)
0715 {
0716     struct ata_port *ap = qc->ap;
0717     struct ata_device *adev = qc->dev;
0718     struct legacy_data *ld_qdi = ap->host->private_data;
0719 
0720     if (ld_qdi->clock[adev->devno] != ld_qdi->last) {
0721         if (adev->pio_mode) {
0722             ld_qdi->last = ld_qdi->clock[adev->devno];
0723             outb(ld_qdi->clock[adev->devno], ld_qdi->timing +
0724                             2 * ap->port_no);
0725         }
0726     }
0727     return ata_sff_qc_issue(qc);
0728 }
0729 
0730 static unsigned int vlb32_data_xfer(struct ata_queued_cmd *qc,
0731                     unsigned char *buf,
0732                     unsigned int buflen, int rw)
0733 {
0734     struct ata_device *adev = qc->dev;
0735     struct ata_port *ap = adev->link->ap;
0736     int slop = buflen & 3;
0737 
0738     if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3)
0739                     && (ap->pflags & ATA_PFLAG_PIO32)) {
0740         if (rw == WRITE)
0741             iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
0742         else
0743             ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
0744 
0745         if (unlikely(slop)) {
0746             __le32 pad = 0;
0747 
0748             if (rw == WRITE) {
0749                 memcpy(&pad, buf + buflen - slop, slop);
0750                 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
0751             } else {
0752                 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
0753                 memcpy(buf + buflen - slop, &pad, slop);
0754             }
0755         }
0756         return (buflen + 3) & ~3;
0757     } else
0758         return ata_sff_data_xfer(qc, buf, buflen, rw);
0759 }
0760 
0761 static int qdi_port(struct platform_device *dev,
0762             struct legacy_probe *lp, struct legacy_data *ld)
0763 {
0764     if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL)
0765         return -EBUSY;
0766     ld->timing = lp->private;
0767     return 0;
0768 }
0769 
0770 static struct ata_port_operations qdi6500_port_ops = {
0771     .inherits   = &legacy_base_port_ops,
0772     .set_piomode    = qdi65x0_set_piomode,
0773     .qc_issue   = qdi_qc_issue,
0774     .sff_data_xfer  = vlb32_data_xfer,
0775 };
0776 
0777 static struct ata_port_operations qdi6580_port_ops = {
0778     .inherits   = &legacy_base_port_ops,
0779     .set_piomode    = qdi65x0_set_piomode,
0780     .sff_data_xfer  = vlb32_data_xfer,
0781 };
0782 
0783 static struct ata_port_operations qdi6580dp_port_ops = {
0784     .inherits   = &legacy_base_port_ops,
0785     .set_piomode    = qdi65x0_set_piomode,
0786     .qc_issue   = qdi_qc_issue,
0787     .sff_data_xfer  = vlb32_data_xfer,
0788 };
0789 
0790 static DEFINE_SPINLOCK(winbond_lock);
0791 
0792 static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
0793 {
0794     unsigned long flags;
0795     spin_lock_irqsave(&winbond_lock, flags);
0796     outb(reg, port + 0x01);
0797     outb(val, port + 0x02);
0798     spin_unlock_irqrestore(&winbond_lock, flags);
0799 }
0800 
0801 static u8 winbond_readcfg(unsigned long port, u8 reg)
0802 {
0803     u8 val;
0804 
0805     unsigned long flags;
0806     spin_lock_irqsave(&winbond_lock, flags);
0807     outb(reg, port + 0x01);
0808     val = inb(port + 0x02);
0809     spin_unlock_irqrestore(&winbond_lock, flags);
0810 
0811     return val;
0812 }
0813 
0814 static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
0815 {
0816     struct ata_timing t;
0817     struct legacy_data *ld_winbond = ap->host->private_data;
0818     int active, recovery;
0819     u8 reg;
0820     int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
0821 
0822     reg = winbond_readcfg(ld_winbond->timing, 0x81);
0823 
0824     /* Get the timing data in cycles */
0825     if (reg & 0x40)     /* Fast VLB bus, assume 50MHz */
0826         ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
0827     else
0828         ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
0829 
0830     active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;
0831     recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;
0832     timing = (active << 4) | recovery;
0833     winbond_writecfg(ld_winbond->timing, timing, reg);
0834 
0835     /* Load the setup timing */
0836 
0837     reg = 0x35;
0838     if (adev->class != ATA_DEV_ATA)
0839         reg |= 0x08;    /* FIFO off */
0840     if (!ata_pio_need_iordy(adev))
0841         reg |= 0x02;    /* IORDY off */
0842     reg |= (clamp_val(t.setup, 0, 3) << 6);
0843     winbond_writecfg(ld_winbond->timing, timing + 1, reg);
0844 }
0845 
0846 static int winbond_port(struct platform_device *dev,
0847             struct legacy_probe *lp, struct legacy_data *ld)
0848 {
0849     if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL)
0850         return -EBUSY;
0851     ld->timing = lp->private;
0852     return 0;
0853 }
0854 
0855 static struct ata_port_operations winbond_port_ops = {
0856     .inherits   = &legacy_base_port_ops,
0857     .set_piomode    = winbond_set_piomode,
0858     .sff_data_xfer  = vlb32_data_xfer,
0859 };
0860 
0861 static struct legacy_controller controllers[] = {
0862     {"BIOS",    &legacy_port_ops,   ATA_PIO4,
0863             ATA_FLAG_NO_IORDY,  0,          NULL },
0864     {"Snooping",    &simple_port_ops,   ATA_PIO4,
0865             0,          0,          NULL },
0866     {"PDC20230",    &pdc20230_port_ops, ATA_PIO2,
0867             ATA_FLAG_NO_IORDY,
0868             ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,    NULL },
0869     {"HT6560A", &ht6560a_port_ops,  ATA_PIO2,
0870             ATA_FLAG_NO_IORDY,  0,          NULL },
0871     {"HT6560B", &ht6560b_port_ops,  ATA_PIO4,
0872             ATA_FLAG_NO_IORDY,  0,          NULL },
0873     {"OPTI82C611A", &opti82c611a_port_ops,  ATA_PIO3,
0874             0,          0,          NULL },
0875     {"OPTI82C46X",  &opti82c46x_port_ops,   ATA_PIO3,
0876             0,          0,          NULL },
0877     {"QDI6500", &qdi6500_port_ops,  ATA_PIO2,
0878             ATA_FLAG_NO_IORDY,
0879             ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,    qdi_port },
0880     {"QDI6580", &qdi6580_port_ops,  ATA_PIO4,
0881             0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
0882     {"QDI6580DP",   &qdi6580dp_port_ops,    ATA_PIO4,
0883             0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
0884     {"W83759A", &winbond_port_ops,  ATA_PIO4,
0885             0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,
0886                                 winbond_port }
0887 };
0888 
0889 /**
0890  *  probe_chip_type     -   Discover controller
0891  *  @probe: Probe entry to check
0892  *
0893  *  Probe an ATA port and identify the type of controller. We don't
0894  *  check if the controller appears to be driveless at this point.
0895  */
0896 
0897 static __init int probe_chip_type(struct legacy_probe *probe)
0898 {
0899     int mask = 1 << probe->slot;
0900 
0901     if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) {
0902         u8 reg = winbond_readcfg(winbond, 0x81);
0903         reg |= 0x80;    /* jumpered mode off */
0904         winbond_writecfg(winbond, 0x81, reg);
0905         reg = winbond_readcfg(winbond, 0x83);
0906         reg |= 0xF0;    /* local control */
0907         winbond_writecfg(winbond, 0x83, reg);
0908         reg = winbond_readcfg(winbond, 0x85);
0909         reg |= 0xF0;    /* programmable timing */
0910         winbond_writecfg(winbond, 0x85, reg);
0911 
0912         reg = winbond_readcfg(winbond, 0x81);
0913 
0914         if (reg & mask)
0915             return W83759A;
0916     }
0917     if (probe->port == 0x1F0) {
0918         unsigned long flags;
0919         local_irq_save(flags);
0920         /* Probes */
0921         outb(inb(0x1F2) | 0x80, 0x1F2);
0922         inb(0x1F5);
0923         inb(0x1F2);
0924         inb(0x3F6);
0925         inb(0x3F6);
0926         inb(0x1F2);
0927         inb(0x1F2);
0928 
0929         if ((inb(0x1F2) & 0x80) == 0) {
0930             /* PDC20230c or 20630 ? */
0931             printk(KERN_INFO  "PDC20230-C/20630 VLB ATA controller"
0932                             " detected.\n");
0933             udelay(100);
0934             inb(0x1F5);
0935             local_irq_restore(flags);
0936             return PDC20230;
0937         } else {
0938             outb(0x55, 0x1F2);
0939             inb(0x1F2);
0940             inb(0x1F2);
0941             if (inb(0x1F2) == 0x00)
0942                 printk(KERN_INFO "PDC20230-B VLB ATA "
0943                              "controller detected.\n");
0944             local_irq_restore(flags);
0945             return BIOS;
0946         }
0947     }
0948 
0949     if (ht6560a & mask)
0950         return HT6560A;
0951     if (ht6560b & mask)
0952         return HT6560B;
0953     if (opti82c611a & mask)
0954         return OPTI611A;
0955     if (opti82c46x & mask)
0956         return OPTI46X;
0957     if (autospeed & mask)
0958         return SNOOP;
0959     return BIOS;
0960 }
0961 
0962 
0963 /**
0964  *  legacy_init_one     -   attach a legacy interface
0965  *  @probe: probe record
0966  *
0967  *  Register an ISA bus IDE interface. Such interfaces are PIO and we
0968  *  assume do not support IRQ sharing.
0969  */
0970 
0971 static __init int legacy_init_one(struct legacy_probe *probe)
0972 {
0973     struct legacy_controller *controller = &controllers[probe->type];
0974     int pio_modes = controller->pio_mask;
0975     unsigned long io = probe->port;
0976     u32 mask = (1 << probe->slot);
0977     struct ata_port_operations *ops = controller->ops;
0978     struct legacy_data *ld = &legacy_data[probe->slot];
0979     struct ata_host *host = NULL;
0980     struct ata_port *ap;
0981     struct platform_device *pdev;
0982     struct ata_device *dev;
0983     void __iomem *io_addr, *ctrl_addr;
0984     u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
0985     int ret;
0986 
0987     iordy |= controller->flags;
0988 
0989     pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);
0990     if (IS_ERR(pdev))
0991         return PTR_ERR(pdev);
0992 
0993     ret = -EBUSY;
0994     if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
0995         devm_request_region(&pdev->dev, io + 0x0206, 1,
0996                             "pata_legacy") == NULL)
0997         goto fail;
0998 
0999     ret = -ENOMEM;
1000     io_addr = devm_ioport_map(&pdev->dev, io, 8);
1001     ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);
1002     if (!io_addr || !ctrl_addr)
1003         goto fail;
1004     ld->type = probe->type;
1005     if (controller->setup)
1006         if (controller->setup(pdev, probe, ld) < 0)
1007             goto fail;
1008     host = ata_host_alloc(&pdev->dev, 1);
1009     if (!host)
1010         goto fail;
1011     ap = host->ports[0];
1012 
1013     ap->ops = ops;
1014     ap->pio_mask = pio_modes;
1015     ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
1016     ap->pflags |= controller->pflags;
1017     ap->ioaddr.cmd_addr = io_addr;
1018     ap->ioaddr.altstatus_addr = ctrl_addr;
1019     ap->ioaddr.ctl_addr = ctrl_addr;
1020     ata_sff_std_ports(&ap->ioaddr);
1021     ap->host->private_data = ld;
1022 
1023     ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);
1024 
1025     ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0,
1026                 &legacy_sht);
1027     if (ret)
1028         goto fail;
1029     async_synchronize_full();
1030     ld->platform_dev = pdev;
1031 
1032     /* Nothing found means we drop the port as its probably not there */
1033 
1034     ret = -ENODEV;
1035     ata_for_each_dev(dev, &ap->link, ALL) {
1036         if (!ata_dev_absent(dev)) {
1037             legacy_host[probe->slot] = host;
1038             ld->platform_dev = pdev;
1039             return 0;
1040         }
1041     }
1042     ata_host_detach(host);
1043 fail:
1044     platform_device_unregister(pdev);
1045     return ret;
1046 }
1047 
1048 /**
1049  *  legacy_check_special_cases  -   ATA special cases
1050  *  @p: PCI device to check
1051  *  @primary: set this if we find an ATA master
1052  *  @secondary: set this if we find an ATA secondary
1053  *
1054  *  A small number of vendors implemented early PCI ATA interfaces
1055  *  on bridge logic without the ATA interface being PCI visible.
1056  *  Where we have a matching PCI driver we must skip the relevant
1057  *  device here. If we don't know about it then the legacy driver
1058  *  is the right driver anyway.
1059  */
1060 
1061 static void __init legacy_check_special_cases(struct pci_dev *p, int *primary,
1062                                 int *secondary)
1063 {
1064     /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
1065     if (p->vendor == 0x1078 && p->device == 0x0000) {
1066         *primary = *secondary = 1;
1067         return;
1068     }
1069     /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
1070     if (p->vendor == 0x1078 && p->device == 0x0002) {
1071         *primary = *secondary = 1;
1072         return;
1073     }
1074     /* Intel MPIIX - PIO ATA on non PCI side of bridge */
1075     if (p->vendor == 0x8086 && p->device == 0x1234) {
1076         u16 r;
1077         pci_read_config_word(p, 0x6C, &r);
1078         if (r & 0x8000) {
1079             /* ATA port enabled */
1080             if (r & 0x4000)
1081                 *secondary = 1;
1082             else
1083                 *primary = 1;
1084         }
1085         return;
1086     }
1087 }
1088 
1089 static __init void probe_opti_vlb(void)
1090 {
1091     /* If an OPTI 82C46X is present find out where the channels are */
1092     static const char *optis[4] = {
1093         "3/463MV", "5MV",
1094         "5MVA", "5MVB"
1095     };
1096     u8 chans = 1;
1097     u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
1098 
1099     opti82c46x = 3; /* Assume master and slave first */
1100     printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",
1101                                 optis[ctrl]);
1102     if (ctrl == 3)
1103         chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
1104     ctrl = opti_syscfg(0xAC);
1105     /* Check enabled and this port is the 465MV port. On the
1106        MVB we may have two channels */
1107     if (ctrl & 8) {
1108         if (chans == 2) {
1109             legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1110             legacy_probe_add(0x170, 15, OPTI46X, 0);
1111         }
1112         if (ctrl & 4)
1113             legacy_probe_add(0x170, 15, OPTI46X, 0);
1114         else
1115             legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1116     } else
1117         legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1118 }
1119 
1120 static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)
1121 {
1122     static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
1123     /* Check card type */
1124     if ((r & 0xF0) == 0xC0) {
1125         /* QD6500: single channel */
1126         if (r & 8)
1127             /* Disabled ? */
1128             return;
1129         legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1130                                 QDI6500, port);
1131     }
1132     if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
1133         /* QD6580: dual channel */
1134         if (!request_region(port + 2 , 2, "pata_qdi")) {
1135             release_region(port, 2);
1136             return;
1137         }
1138         res = inb(port + 3);
1139         /* Single channel mode ? */
1140         if (res & 1)
1141             legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1142                                 QDI6580, port);
1143         else { /* Dual channel mode */
1144             legacy_probe_add(0x1F0, 14, QDI6580DP, port);
1145             /* port + 0x02, r & 0x04 */
1146             legacy_probe_add(0x170, 15, QDI6580DP, port + 2);
1147         }
1148         release_region(port + 2, 2);
1149     }
1150 }
1151 
1152 static __init void probe_qdi_vlb(void)
1153 {
1154     unsigned long flags;
1155     static const unsigned long qd_port[2] = { 0x30, 0xB0 };
1156     int i;
1157 
1158     /*
1159      *  Check each possible QD65xx base address
1160      */
1161 
1162     for (i = 0; i < 2; i++) {
1163         unsigned long port = qd_port[i];
1164         u8 r, res;
1165 
1166 
1167         if (request_region(port, 2, "pata_qdi")) {
1168             /* Check for a card */
1169             local_irq_save(flags);
1170             /* I have no h/w that needs this delay but it
1171                is present in the historic code */
1172             r = inb(port);
1173             udelay(1);
1174             outb(0x19, port);
1175             udelay(1);
1176             res = inb(port);
1177             udelay(1);
1178             outb(r, port);
1179             udelay(1);
1180             local_irq_restore(flags);
1181 
1182             /* Fail */
1183             if (res == 0x19) {
1184                 release_region(port, 2);
1185                 continue;
1186             }
1187             /* Passes the presence test */
1188             r = inb(port + 1);
1189             udelay(1);
1190             /* Check port agrees with port set */
1191             if ((r & 2) >> 1 == i)
1192                 qdi65_identify_port(r, res, port);
1193             release_region(port, 2);
1194         }
1195     }
1196 }
1197 
1198 /**
1199  *  legacy_init     -   attach legacy interfaces
1200  *
1201  *  Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
1202  *  Right now we do not scan the ide0 and ide1 address but should do so
1203  *  for non PCI systems or systems with no PCI IDE legacy mode devices.
1204  *  If you fix that note there are special cases to consider like VLB
1205  *  drivers and CS5510/20.
1206  */
1207 
1208 static __init int legacy_init(void)
1209 {
1210     int i;
1211     int ct = 0;
1212     int primary = 0;
1213     int secondary = 0;
1214     int pci_present = 0;
1215     struct legacy_probe *pl = &probe_list[0];
1216     int slot = 0;
1217 
1218     struct pci_dev *p = NULL;
1219 
1220     for_each_pci_dev(p) {
1221         int r;
1222         /* Check for any overlap of the system ATA mappings. Native
1223            mode controllers stuck on these addresses or some devices
1224            in 'raid' mode won't be found by the storage class test */
1225         for (r = 0; r < 6; r++) {
1226             if (pci_resource_start(p, r) == 0x1f0)
1227                 primary = 1;
1228             if (pci_resource_start(p, r) == 0x170)
1229                 secondary = 1;
1230         }
1231         /* Check for special cases */
1232         legacy_check_special_cases(p, &primary, &secondary);
1233 
1234         /* If PCI bus is present then don't probe for tertiary
1235            legacy ports */
1236         pci_present = 1;
1237     }
1238 
1239     if (winbond == 1)
1240         winbond = 0x130;    /* Default port, alt is 1B0 */
1241 
1242     if (primary == 0 || all)
1243         legacy_probe_add(0x1F0, 14, UNKNOWN, 0);
1244     if (secondary == 0 || all)
1245         legacy_probe_add(0x170, 15, UNKNOWN, 0);
1246 
1247     if (probe_all || !pci_present) {
1248         /* ISA/VLB extra ports */
1249         legacy_probe_add(0x1E8, 11, UNKNOWN, 0);
1250         legacy_probe_add(0x168, 10, UNKNOWN, 0);
1251         legacy_probe_add(0x1E0, 8, UNKNOWN, 0);
1252         legacy_probe_add(0x160, 12, UNKNOWN, 0);
1253     }
1254 
1255     if (opti82c46x)
1256         probe_opti_vlb();
1257     if (qdi)
1258         probe_qdi_vlb();
1259 
1260     for (i = 0; i < NR_HOST; i++, pl++) {
1261         if (pl->port == 0)
1262             continue;
1263         if (pl->type == UNKNOWN)
1264             pl->type = probe_chip_type(pl);
1265         pl->slot = slot++;
1266         if (legacy_init_one(pl) == 0)
1267             ct++;
1268     }
1269     if (ct != 0)
1270         return 0;
1271     return -ENODEV;
1272 }
1273 
1274 static __exit void legacy_exit(void)
1275 {
1276     int i;
1277 
1278     for (i = 0; i < nr_legacy_host; i++) {
1279         struct legacy_data *ld = &legacy_data[i];
1280         ata_host_detach(legacy_host[i]);
1281         platform_device_unregister(ld->platform_dev);
1282     }
1283 }
1284 
1285 MODULE_AUTHOR("Alan Cox");
1286 MODULE_DESCRIPTION("low-level driver for legacy ATA");
1287 MODULE_LICENSE("GPL");
1288 MODULE_VERSION(DRV_VERSION);
1289 MODULE_ALIAS("pata_qdi");
1290 MODULE_ALIAS("pata_winbond");
1291 
1292 module_init(legacy_init);
1293 module_exit(legacy_exit);
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