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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * ixp4xx PATA/Compact Flash driver
0004  * Copyright (C) 2006-07 Tower Technologies
0005  * Author: Alessandro Zummo <a.zummo@towertech.it>
0006  *
0007  * An ATA driver to handle a Compact Flash connected
0008  * to the ixp4xx expansion bus in TrueIDE mode. The CF
0009  * must have it chip selects connected to two CS lines
0010  * on the ixp4xx. In the irq is not available, you might
0011  * want to modify both this driver and libata to run in
0012  * polling mode.
0013  */
0014 
0015 #include <linux/kernel.h>
0016 #include <linux/mfd/syscon.h>
0017 #include <linux/module.h>
0018 #include <linux/libata.h>
0019 #include <linux/irq.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/regmap.h>
0022 #include <scsi/scsi_host.h>
0023 
0024 #define DRV_NAME    "pata_ixp4xx_cf"
0025 #define DRV_VERSION "1.0"
0026 
0027 struct ixp4xx_pata {
0028     struct ata_host *host;
0029     struct regmap *rmap;
0030     u32 cmd_csreg;
0031     void __iomem *cmd;
0032     void __iomem *ctl;
0033 };
0034 
0035 #define IXP4XX_EXP_TIMING_STRIDE    0x04
0036 /* The timings for the chipselect is in bits 29..16 */
0037 #define IXP4XX_EXP_T1_T5_MASK   GENMASK(29, 16)
0038 #define IXP4XX_EXP_PIO_0_8  0x0a470000
0039 #define IXP4XX_EXP_PIO_1_8  0x06430000
0040 #define IXP4XX_EXP_PIO_2_8  0x02410000
0041 #define IXP4XX_EXP_PIO_3_8  0x00820000
0042 #define IXP4XX_EXP_PIO_4_8  0x00400000
0043 #define IXP4XX_EXP_PIO_0_16 0x29640000
0044 #define IXP4XX_EXP_PIO_1_16 0x05030000
0045 #define IXP4XX_EXP_PIO_2_16 0x00b20000
0046 #define IXP4XX_EXP_PIO_3_16 0x00820000
0047 #define IXP4XX_EXP_PIO_4_16 0x00400000
0048 #define IXP4XX_EXP_BW_MASK  (BIT(6)|BIT(0))
0049 #define IXP4XX_EXP_BYTE_RD16    BIT(6) /* Byte reads on half-word devices */
0050 #define IXP4XX_EXP_BYTE_EN  BIT(0) /* Use 8bit data bus if set */
0051 
0052 static void ixp4xx_set_8bit_timing(struct ixp4xx_pata *ixpp, u8 pio_mode)
0053 {
0054     switch (pio_mode) {
0055     case XFER_PIO_0:
0056         regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
0057                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_0_8);
0058         break;
0059     case XFER_PIO_1:
0060         regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
0061                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_1_8);
0062         break;
0063     case XFER_PIO_2:
0064         regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
0065                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_2_8);
0066         break;
0067     case XFER_PIO_3:
0068         regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
0069                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_3_8);
0070         break;
0071     case XFER_PIO_4:
0072         regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
0073                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_4_8);
0074         break;
0075     default:
0076         break;
0077     }
0078     regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
0079                IXP4XX_EXP_BW_MASK, IXP4XX_EXP_BYTE_RD16|IXP4XX_EXP_BYTE_EN);
0080 }
0081 
0082 static void ixp4xx_set_16bit_timing(struct ixp4xx_pata *ixpp, u8 pio_mode)
0083 {
0084     switch (pio_mode){
0085     case XFER_PIO_0:
0086         regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
0087                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_0_16);
0088         break;
0089     case XFER_PIO_1:
0090         regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
0091                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_1_16);
0092         break;
0093     case XFER_PIO_2:
0094         regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
0095                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_2_16);
0096         break;
0097     case XFER_PIO_3:
0098         regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
0099                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_3_16);
0100         break;
0101     case XFER_PIO_4:
0102         regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
0103                    IXP4XX_EXP_T1_T5_MASK, IXP4XX_EXP_PIO_4_16);
0104         break;
0105     default:
0106         break;
0107     }
0108     regmap_update_bits(ixpp->rmap, ixpp->cmd_csreg,
0109                IXP4XX_EXP_BW_MASK, IXP4XX_EXP_BYTE_RD16);
0110 }
0111 
0112 /* This sets up the timing on the chipselect CMD accordingly */
0113 static void ixp4xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
0114 {
0115     struct ixp4xx_pata *ixpp = ap->host->private_data;
0116 
0117     ata_dev_info(adev, "configured for PIO%d 8bit\n",
0118                adev->pio_mode - XFER_PIO_0);
0119     ixp4xx_set_8bit_timing(ixpp, adev->pio_mode);
0120 }
0121 
0122 
0123 static unsigned int ixp4xx_mmio_data_xfer(struct ata_queued_cmd *qc,
0124                       unsigned char *buf, unsigned int buflen, int rw)
0125 {
0126     unsigned int i;
0127     unsigned int words = buflen >> 1;
0128     u16 *buf16 = (u16 *) buf;
0129     struct ata_device *adev = qc->dev;
0130     struct ata_port *ap = qc->dev->link->ap;
0131     void __iomem *mmio = ap->ioaddr.data_addr;
0132     struct ixp4xx_pata *ixpp = ap->host->private_data;
0133     unsigned long flags;
0134 
0135     ata_dev_dbg(adev, "%s %d bytes\n", (rw == READ) ? "READ" : "WRITE",
0136             buflen);
0137     spin_lock_irqsave(ap->lock, flags);
0138 
0139     /* set the expansion bus in 16bit mode and restore
0140      * 8 bit mode after the transaction.
0141      */
0142     ixp4xx_set_16bit_timing(ixpp, adev->pio_mode);
0143     udelay(5);
0144 
0145     /* Transfer multiple of 2 bytes */
0146     if (rw == READ)
0147         for (i = 0; i < words; i++)
0148             buf16[i] = readw(mmio);
0149     else
0150         for (i = 0; i < words; i++)
0151             writew(buf16[i], mmio);
0152 
0153     /* Transfer trailing 1 byte, if any. */
0154     if (unlikely(buflen & 0x01)) {
0155         u16 align_buf[1] = { 0 };
0156         unsigned char *trailing_buf = buf + buflen - 1;
0157 
0158         if (rw == READ) {
0159             align_buf[0] = readw(mmio);
0160             memcpy(trailing_buf, align_buf, 1);
0161         } else {
0162             memcpy(align_buf, trailing_buf, 1);
0163             writew(align_buf[0], mmio);
0164         }
0165         words++;
0166     }
0167 
0168     ixp4xx_set_8bit_timing(ixpp, adev->pio_mode);
0169     udelay(5);
0170 
0171     spin_unlock_irqrestore(ap->lock, flags);
0172 
0173     return words << 1;
0174 }
0175 
0176 static struct scsi_host_template ixp4xx_sht = {
0177     ATA_PIO_SHT(DRV_NAME),
0178 };
0179 
0180 static struct ata_port_operations ixp4xx_port_ops = {
0181     .inherits       = &ata_sff_port_ops,
0182     .sff_data_xfer      = ixp4xx_mmio_data_xfer,
0183     .cable_detect       = ata_cable_40wire,
0184     .set_piomode        = ixp4xx_set_piomode,
0185 };
0186 
0187 static struct ata_port_info ixp4xx_port_info = {
0188     .flags      = ATA_FLAG_NO_ATAPI,
0189     .pio_mask   = ATA_PIO4,
0190     .port_ops   = &ixp4xx_port_ops,
0191 };
0192 
0193 static void ixp4xx_setup_port(struct ata_port *ap,
0194                   struct ixp4xx_pata *ixpp,
0195                   unsigned long raw_cmd, unsigned long raw_ctl)
0196 {
0197     struct ata_ioports *ioaddr = &ap->ioaddr;
0198 
0199     raw_ctl += 0x06;
0200     ioaddr->cmd_addr    = ixpp->cmd;
0201     ioaddr->altstatus_addr  = ixpp->ctl + 0x06;
0202     ioaddr->ctl_addr    = ixpp->ctl + 0x06;
0203 
0204     ata_sff_std_ports(ioaddr);
0205 
0206     if (!IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) {
0207         /* adjust the addresses to handle the address swizzling of the
0208          * ixp4xx in little endian mode.
0209          */
0210 
0211         *(unsigned long *)&ioaddr->data_addr        ^= 0x02;
0212         *(unsigned long *)&ioaddr->cmd_addr     ^= 0x03;
0213         *(unsigned long *)&ioaddr->altstatus_addr   ^= 0x03;
0214         *(unsigned long *)&ioaddr->ctl_addr     ^= 0x03;
0215         *(unsigned long *)&ioaddr->error_addr       ^= 0x03;
0216         *(unsigned long *)&ioaddr->feature_addr     ^= 0x03;
0217         *(unsigned long *)&ioaddr->nsect_addr       ^= 0x03;
0218         *(unsigned long *)&ioaddr->lbal_addr        ^= 0x03;
0219         *(unsigned long *)&ioaddr->lbam_addr        ^= 0x03;
0220         *(unsigned long *)&ioaddr->lbah_addr        ^= 0x03;
0221         *(unsigned long *)&ioaddr->device_addr      ^= 0x03;
0222         *(unsigned long *)&ioaddr->status_addr      ^= 0x03;
0223         *(unsigned long *)&ioaddr->command_addr     ^= 0x03;
0224 
0225         raw_cmd ^= 0x03;
0226         raw_ctl ^= 0x03;
0227     }
0228 
0229     ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", raw_cmd, raw_ctl);
0230 }
0231 
0232 static int ixp4xx_pata_probe(struct platform_device *pdev)
0233 {
0234     struct resource *cmd, *ctl;
0235     struct ata_port_info pi = ixp4xx_port_info;
0236     const struct ata_port_info *ppi[] = { &pi, NULL };
0237     struct device *dev = &pdev->dev;
0238     struct device_node *np = dev->of_node;
0239     struct ixp4xx_pata *ixpp;
0240     u32 csindex;
0241     int ret;
0242     int irq;
0243 
0244     cmd = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0245     ctl = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0246 
0247     if (!cmd || !ctl)
0248         return -EINVAL;
0249 
0250     ixpp = devm_kzalloc(dev, sizeof(*ixpp), GFP_KERNEL);
0251     if (!ixpp)
0252         return -ENOMEM;
0253 
0254     ixpp->rmap = syscon_node_to_regmap(np->parent);
0255     if (IS_ERR(ixpp->rmap))
0256         return dev_err_probe(dev, PTR_ERR(ixpp->rmap), "no regmap\n");
0257     /* Inspect our address to figure out what chipselect the CMD is on */
0258     ret = of_property_read_u32_index(np, "reg", 0, &csindex);
0259     if (ret)
0260         return dev_err_probe(dev, ret, "can't inspect CMD address\n");
0261     dev_info(dev, "using CS%d for PIO timing configuration\n", csindex);
0262     ixpp->cmd_csreg = csindex * IXP4XX_EXP_TIMING_STRIDE;
0263 
0264     ixpp->host = ata_host_alloc_pinfo(dev, ppi, 1);
0265     if (!ixpp->host)
0266         return -ENOMEM;
0267     ixpp->host->private_data = ixpp;
0268 
0269     ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
0270     if (ret)
0271         return ret;
0272 
0273     ixpp->cmd = devm_ioremap_resource(dev, cmd);
0274     ixpp->ctl = devm_ioremap_resource(dev, ctl);
0275     if (IS_ERR(ixpp->cmd) || IS_ERR(ixpp->ctl))
0276         return -ENOMEM;
0277 
0278     irq = platform_get_irq(pdev, 0);
0279     if (irq > 0)
0280         irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
0281     else if (irq < 0)
0282         return irq;
0283     else
0284         return -EINVAL;
0285 
0286     /* Just one port to set up */
0287     ixp4xx_setup_port(ixpp->host->ports[0], ixpp, cmd->start, ctl->start);
0288 
0289     ata_print_version_once(dev, DRV_VERSION);
0290 
0291     return ata_host_activate(ixpp->host, irq, ata_sff_interrupt, 0, &ixp4xx_sht);
0292 }
0293 
0294 static const struct of_device_id ixp4xx_pata_of_match[] = {
0295     { .compatible = "intel,ixp4xx-compact-flash", },
0296     { /* sentinel */ }
0297 };
0298 
0299 static struct platform_driver ixp4xx_pata_platform_driver = {
0300     .driver  = {
0301         .name   = DRV_NAME,
0302         .of_match_table = ixp4xx_pata_of_match,
0303     },
0304     .probe      = ixp4xx_pata_probe,
0305     .remove     = ata_platform_remove_one,
0306 };
0307 
0308 module_platform_driver(ixp4xx_pata_platform_driver);
0309 
0310 MODULE_AUTHOR("Alessandro Zummo <a.zummo@towertech.it>");
0311 MODULE_DESCRIPTION("low-level driver for ixp4xx Compact Flash PATA");
0312 MODULE_LICENSE("GPL");
0313 MODULE_VERSION(DRV_VERSION);
0314 MODULE_ALIAS("platform:" DRV_NAME);
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