drivers/ata/pata_it8213.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *    pata_it8213.c - iTE Tech. Inc.  IT8213 PATA driver
0004  *
0005  *    The IT8213 is a very Intel ICH like device for timing purposes, having
0006  *    a similar register layout and the same split clock arrangement. Cable
0007  *    detection is different, and it does not have slave channels or all the
0008  *    clutter of later ICH/SATA setups.
0009  */
0010
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/pci.h>
0014 #include <linux/blkdev.h>
0015 #include <linux/delay.h>
0016 #include <linux/device.h>
0017 #include <scsi/scsi_host.h>
0018 #include <linux/libata.h>
0019 #include <linux/ata.h>
0020
0021 #define DRV_NAME    "pata_it8213"
0022 #define DRV_VERSION "0.0.3"
0023
0024 /**
0025  *  it8213_pre_reset    -   probe begin
0026  *  @link: link
0027  *  @deadline: deadline jiffies for the operation
0028  *
0029  *  Filter out ports by the enable bits before doing the normal reset
0030  *  and probe.
0031  */
0032
0033 static int it8213_pre_reset(struct ata_link *link, unsigned long deadline)
0034 {
0035     static const struct pci_bits it8213_enable_bits[] = {
0036         { 0x41U, 1U, 0x80UL, 0x80UL },  /* port 0 */
0037     };
0038     struct ata_port *ap = link->ap;
0039     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0040     if (!pci_test_config_bits(pdev, &it8213_enable_bits[ap->port_no]))
0041         return -ENOENT;
0042
0043     return ata_sff_prereset(link, deadline);
0044 }
0045
0046 /**
0047  *  it8213_cable_detect -   check for 40/80 pin
0048  *  @ap: Port
0049  *
0050  *  Perform cable detection for the 8213 ATA interface. This is
0051  *  different to the PIIX arrangement
0052  */
0053
0054 static int it8213_cable_detect(struct ata_port *ap)
0055 {
0056     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0057     u8 tmp;
0058     pci_read_config_byte(pdev, 0x42, &tmp);
0059     if (tmp & 2)    /* The initial docs are incorrect */
0060         return ATA_CBL_PATA40;
0061     return ATA_CBL_PATA80;
0062 }
0063
0064 /**
0065  *  it8213_set_piomode - Initialize host controller PATA PIO timings
0066  *  @ap: Port whose timings we are configuring
0067  *  @adev: Device whose timings we are configuring
0068  *
0069  *  Set PIO mode for device, in host controller PCI config space.
0070  *
0071  *  LOCKING:
0072  *  None (inherited from caller).
0073  */
0074
0075 static void it8213_set_piomode (struct ata_port *ap, struct ata_device *adev)
0076 {
0077     unsigned int pio    = adev->pio_mode - XFER_PIO_0;
0078     struct pci_dev *dev = to_pci_dev(ap->host->dev);
0079     unsigned int master_port = ap->port_no ? 0x42 : 0x40;
0080     u16 master_data;
0081     int control = 0;
0082
0083     /*
0084      *  See Intel Document 298600-004 for the timing programing rules
0085      *  for PIIX/ICH. The 8213 is a clone so very similar
0086      */
0087
0088     static const     /* ISP  RTC */
0089     u8 timings[][2] = { { 0, 0 },
0090                 { 0, 0 },
0091                 { 1, 0 },
0092                 { 2, 1 },
0093                 { 2, 3 }, };
0094
0095     if (pio > 1)
0096         control |= 1;   /* TIME */
0097     if (ata_pio_need_iordy(adev))   /* PIO 3/4 require IORDY */
0098         control |= 2;   /* IE */
0099     /* Bit 2 is set for ATAPI on the IT8213 - reverse of ICH/PIIX */
0100     if (adev->class != ATA_DEV_ATA)
0101         control |= 4;   /* PPE */
0102
0103     pci_read_config_word(dev, master_port, &master_data);
0104
0105     /* Set PPE, IE, and TIME as appropriate */
0106     if (adev->devno == 0) {
0107         master_data &= 0xCCF0;
0108         master_data |= control;
0109         master_data |= (timings[pio][0] << 12) |
0110             (timings[pio][1] << 8);
0111     } else {
0112         u8 slave_data;
0113
0114         master_data &= 0xFF0F;
0115         master_data |= (control << 4);
0116
0117         /* Slave timing in separate register */
0118         pci_read_config_byte(dev, 0x44, &slave_data);
0119         slave_data &= 0xF0;
0120         slave_data |= (timings[pio][0] << 2) | timings[pio][1];
0121         pci_write_config_byte(dev, 0x44, slave_data);
0122     }
0123
0124     master_data |= 0x4000;  /* Ensure SITRE is set */
0125     pci_write_config_word(dev, master_port, master_data);
0126 }
0127
0128 /**
0129  *  it8213_set_dmamode - Initialize host controller PATA DMA timings
0130  *  @ap: Port whose timings we are configuring
0131  *  @adev: Device to program
0132  *
0133  *  Set UDMA/MWDMA mode for device, in host controller PCI config space.
0134  *  This device is basically an ICH alike.
0135  *
0136  *  LOCKING:
0137  *  None (inherited from caller).
0138  */
0139
0140 static void it8213_set_dmamode (struct ata_port *ap, struct ata_device *adev)
0141 {
0142     struct pci_dev *dev = to_pci_dev(ap->host->dev);
0143     u16 master_data;
0144     u8 speed        = adev->dma_mode;
0145     int devid       = adev->devno;
0146     u8 udma_enable;
0147
0148     static const     /* ISP  RTC */
0149     u8 timings[][2] = { { 0, 0 },
0150                 { 0, 0 },
0151                 { 1, 0 },
0152                 { 2, 1 },
0153                 { 2, 3 }, };
0154
0155     pci_read_config_word(dev, 0x40, &master_data);
0156     pci_read_config_byte(dev, 0x48, &udma_enable);
0157
0158     if (speed >= XFER_UDMA_0) {
0159         unsigned int udma = adev->dma_mode - XFER_UDMA_0;
0160         u16 udma_timing;
0161         u16 ideconf;
0162         int u_clock, u_speed;
0163
0164         /* Clocks follow the PIIX style */
0165         u_speed = min(2 - (udma & 1), udma);
0166         if (udma > 4)
0167             u_clock = 0x1000;   /* 100Mhz */
0168         else if (udma > 2)
0169             u_clock = 1;        /* 66Mhz */
0170         else
0171             u_clock = 0;        /* 33Mhz */
0172
0173         udma_enable |= (1 << devid);
0174
0175         /* Load the UDMA cycle time */
0176         pci_read_config_word(dev, 0x4A, &udma_timing);
0177         udma_timing &= ~(3 << (4 * devid));
0178         udma_timing |= u_speed << (4 * devid);
0179         pci_write_config_word(dev, 0x4A, udma_timing);
0180
0181         /* Load the clock selection */
0182         pci_read_config_word(dev, 0x54, &ideconf);
0183         ideconf &= ~(0x1001 << devid);
0184         ideconf |= u_clock << devid;
0185         pci_write_config_word(dev, 0x54, ideconf);
0186     } else {
0187         /*
0188          * MWDMA is driven by the PIO timings. We must also enable
0189          * IORDY unconditionally along with TIME1. PPE has already
0190          * been set when the PIO timing was set.
0191          */
0192         unsigned int mwdma  = adev->dma_mode - XFER_MW_DMA_0;
0193         unsigned int control;
0194         u8 slave_data;
0195         static const unsigned int needed_pio[3] = {
0196             XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
0197         };
0198         int pio = needed_pio[mwdma] - XFER_PIO_0;
0199
0200         control = 3;    /* IORDY|TIME1 */
0201
0202         /* If the drive MWDMA is faster than it can do PIO then
0203            we must force PIO into PIO0 */
0204
0205         if (adev->pio_mode < needed_pio[mwdma])
0206             /* Enable DMA timing only */
0207             control |= 8;   /* PIO cycles in PIO0 */
0208
0209         if (devid) {    /* Slave */
0210             master_data &= 0xFF4F;  /* Mask out IORDY|TIME1|DMAONLY */
0211             master_data |= control << 4;
0212             pci_read_config_byte(dev, 0x44, &slave_data);
0213             slave_data &= 0xF0;
0214             /* Load the matching timing */
0215             slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
0216             pci_write_config_byte(dev, 0x44, slave_data);
0217         } else {    /* Master */
0218             master_data &= 0xCCF4;  /* Mask out IORDY|TIME1|DMAONLY
0219                            and master timing bits */
0220             master_data |= control;
0221             master_data |=
0222                 (timings[pio][0] << 12) |
0223                 (timings[pio][1] << 8);
0224         }
0225         udma_enable &= ~(1 << devid);
0226         pci_write_config_word(dev, 0x40, master_data);
0227     }
0228     pci_write_config_byte(dev, 0x48, udma_enable);
0229 }
0230
0231 static struct scsi_host_template it8213_sht = {
0232     ATA_BMDMA_SHT(DRV_NAME),
0233 };
0234
0235
0236 static struct ata_port_operations it8213_ops = {
0237     .inherits       = &ata_bmdma_port_ops,
0238     .cable_detect       = it8213_cable_detect,
0239     .set_piomode        = it8213_set_piomode,
0240     .set_dmamode        = it8213_set_dmamode,
0241     .prereset       = it8213_pre_reset,
0242 };
0243
0244
0245 /**
0246  *  it8213_init_one - Register 8213 ATA PCI device with kernel services
0247  *  @pdev: PCI device to register
0248  *  @ent: Entry in it8213_pci_tbl matching with @pdev
0249  *
0250  *  Called from kernel PCI layer.
0251  *
0252  *  LOCKING:
0253  *  Inherited from PCI layer (may sleep).
0254  *
0255  *  RETURNS:
0256  *  Zero on success, or -ERRNO value.
0257  */
0258
0259 static int it8213_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
0260 {
0261     static const struct ata_port_info info = {
0262         .flags      = ATA_FLAG_SLAVE_POSS,
0263         .pio_mask   = ATA_PIO4,
0264         .mwdma_mask = ATA_MWDMA12_ONLY,
0265         .udma_mask  = ATA_UDMA6,
0266         .port_ops   = &it8213_ops,
0267     };
0268     /* Current IT8213 stuff is single port */
0269     const struct ata_port_info *ppi[] = { &info, &ata_dummy_port_info };
0270
0271     ata_print_version_once(&pdev->dev, DRV_VERSION);
0272
0273     return ata_pci_bmdma_init_one(pdev, ppi, &it8213_sht, NULL, 0);
0274 }
0275
0276 static const struct pci_device_id it8213_pci_tbl[] = {
0277     { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8213), },
0278
0279     { } /* terminate list */
0280 };
0281
0282 static struct pci_driver it8213_pci_driver = {
0283     .name           = DRV_NAME,
0284     .id_table       = it8213_pci_tbl,
0285     .probe          = it8213_init_one,
0286     .remove         = ata_pci_remove_one,
0287 #ifdef CONFIG_PM_SLEEP
0288     .suspend        = ata_pci_device_suspend,
0289     .resume         = ata_pci_device_resume,
0290 #endif
0291 };
0292
0293 module_pci_driver(it8213_pci_driver);
0294
0295 MODULE_AUTHOR("Alan Cox");
0296 MODULE_DESCRIPTION("SCSI low-level driver for the ITE 8213");
0297 MODULE_LICENSE("GPL");
0298 MODULE_DEVICE_TABLE(pci, it8213_pci_tbl);
0299 MODULE_VERSION(DRV_VERSION);