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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 #include <linux/kernel.h>
0003 #include <linux/module.h>
0004 #include <linux/init.h>
0005 #include <linux/blkdev.h>
0006 #include <linux/gfp.h>
0007 #include <scsi/scsi_host.h>
0008 #include <linux/ata.h>
0009 #include <linux/libata.h>
0010 
0011 #include <asm/dma.h>
0012 #include <asm/ecard.h>
0013 
0014 #define DRV_NAME    "pata_icside"
0015 
0016 #define ICS_IDENT_OFFSET        0x2280
0017 
0018 #define ICS_ARCIN_V5_INTRSTAT       0x0000
0019 #define ICS_ARCIN_V5_INTROFFSET     0x0004
0020 
0021 #define ICS_ARCIN_V6_INTROFFSET_1   0x2200
0022 #define ICS_ARCIN_V6_INTRSTAT_1     0x2290
0023 #define ICS_ARCIN_V6_INTROFFSET_2   0x3200
0024 #define ICS_ARCIN_V6_INTRSTAT_2     0x3290
0025 
0026 struct portinfo {
0027     unsigned int dataoffset;
0028     unsigned int ctrloffset;
0029     unsigned int stepping;
0030 };
0031 
0032 static const struct portinfo pata_icside_portinfo_v5 = {
0033     .dataoffset = 0x2800,
0034     .ctrloffset = 0x2b80,
0035     .stepping   = 6,
0036 };
0037 
0038 static const struct portinfo pata_icside_portinfo_v6_1 = {
0039     .dataoffset = 0x2000,
0040     .ctrloffset = 0x2380,
0041     .stepping   = 6,
0042 };
0043 
0044 static const struct portinfo pata_icside_portinfo_v6_2 = {
0045     .dataoffset = 0x3000,
0046     .ctrloffset = 0x3380,
0047     .stepping   = 6,
0048 };
0049 
0050 struct pata_icside_state {
0051     void __iomem *irq_port;
0052     void __iomem *ioc_base;
0053     unsigned int type;
0054     unsigned int dma;
0055     struct {
0056         u8 port_sel;
0057         u8 disabled;
0058         unsigned int speed[ATA_MAX_DEVICES];
0059     } port[2];
0060 };
0061 
0062 struct pata_icside_info {
0063     struct pata_icside_state *state;
0064     struct expansion_card   *ec;
0065     void __iomem        *base;
0066     void __iomem        *irqaddr;
0067     unsigned int        irqmask;
0068     const expansioncard_ops_t *irqops;
0069     unsigned int        mwdma_mask;
0070     unsigned int        nr_ports;
0071     const struct portinfo   *port[2];
0072     unsigned long       raw_base;
0073     unsigned long       raw_ioc_base;
0074 };
0075 
0076 #define ICS_TYPE_A3IN   0
0077 #define ICS_TYPE_A3USER 1
0078 #define ICS_TYPE_V6 3
0079 #define ICS_TYPE_V5 15
0080 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
0081 
0082 /* ---------------- Version 5 PCB Support Functions --------------------- */
0083 /* Prototype: pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
0084  * Purpose  : enable interrupts from card
0085  */
0086 static void pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
0087 {
0088     struct pata_icside_state *state = ec->irq_data;
0089 
0090     writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
0091 }
0092 
0093 /* Prototype: pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
0094  * Purpose  : disable interrupts from card
0095  */
0096 static void pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
0097 {
0098     struct pata_icside_state *state = ec->irq_data;
0099 
0100     readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
0101 }
0102 
0103 static const expansioncard_ops_t pata_icside_ops_arcin_v5 = {
0104     .irqenable  = pata_icside_irqenable_arcin_v5,
0105     .irqdisable = pata_icside_irqdisable_arcin_v5,
0106 };
0107 
0108 
0109 /* ---------------- Version 6 PCB Support Functions --------------------- */
0110 /* Prototype: pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
0111  * Purpose  : enable interrupts from card
0112  */
0113 static void pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
0114 {
0115     struct pata_icside_state *state = ec->irq_data;
0116     void __iomem *base = state->irq_port;
0117 
0118     if (!state->port[0].disabled)
0119         writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
0120     if (!state->port[1].disabled)
0121         writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
0122 }
0123 
0124 /* Prototype: pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
0125  * Purpose  : disable interrupts from card
0126  */
0127 static void pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
0128 {
0129     struct pata_icside_state *state = ec->irq_data;
0130 
0131     readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
0132     readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
0133 }
0134 
0135 /* Prototype: pata_icside_irqprobe(struct expansion_card *ec)
0136  * Purpose  : detect an active interrupt from card
0137  */
0138 static int pata_icside_irqpending_arcin_v6(struct expansion_card *ec)
0139 {
0140     struct pata_icside_state *state = ec->irq_data;
0141 
0142     return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
0143            readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
0144 }
0145 
0146 static const expansioncard_ops_t pata_icside_ops_arcin_v6 = {
0147     .irqenable  = pata_icside_irqenable_arcin_v6,
0148     .irqdisable = pata_icside_irqdisable_arcin_v6,
0149     .irqpending = pata_icside_irqpending_arcin_v6,
0150 };
0151 
0152 
0153 /*
0154  * SG-DMA support.
0155  *
0156  * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
0157  * There is only one DMA controller per card, which means that only
0158  * one drive can be accessed at one time.  NOTE! We do not enforce that
0159  * here, but we rely on the main IDE driver spotting that both
0160  * interfaces use the same IRQ, which should guarantee this.
0161  */
0162 
0163 /*
0164  * Configure the IOMD to give the appropriate timings for the transfer
0165  * mode being requested.  We take the advice of the ATA standards, and
0166  * calculate the cycle time based on the transfer mode, and the EIDE
0167  * MW DMA specs that the drive provides in the IDENTIFY command.
0168  *
0169  * We have the following IOMD DMA modes to choose from:
0170  *
0171  *  Type    Active      Recovery    Cycle
0172  *  A   250 (250)   312 (550)   562 (800)
0173  *  B   187 (200)   250 (550)   437 (750)
0174  *  C   125 (125)   125 (375)   250 (500)
0175  *  D   62  (50)    125 (375)   187 (425)
0176  *
0177  * (figures in brackets are actual measured timings on DIOR/DIOW)
0178  *
0179  * However, we also need to take care of the read/write active and
0180  * recovery timings:
0181  *
0182  *          Read    Write
0183  *      Mode    Active  -- Recovery --  Cycle   IOMD type
0184  *  MW0 215 50  215 480 A
0185  *  MW1 80  50  50  150 C
0186  *  MW2 70  25  25  120 C
0187  */
0188 static void pata_icside_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0189 {
0190     struct pata_icside_state *state = ap->host->private_data;
0191     struct ata_timing t;
0192     unsigned int cycle;
0193     char iomd_type;
0194 
0195     /*
0196      * DMA is based on a 16MHz clock
0197      */
0198     if (ata_timing_compute(adev, adev->dma_mode, &t, 1000, 1))
0199         return;
0200 
0201     /*
0202      * Choose the IOMD cycle timing which ensure that the interface
0203      * satisfies the measured active, recovery and cycle times.
0204      */
0205     if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425) {
0206         iomd_type = 'D';
0207         cycle = 187;
0208     } else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500) {
0209         iomd_type = 'C';
0210         cycle = 250;
0211     } else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750) {
0212         iomd_type = 'B';
0213         cycle = 437;
0214     } else {
0215         iomd_type = 'A';
0216         cycle = 562;
0217     }
0218 
0219     ata_dev_info(adev, "timings: act %dns rec %dns cyc %dns (%c)\n",
0220              t.active, t.recover, t.cycle, iomd_type);
0221 
0222     state->port[ap->port_no].speed[adev->devno] = cycle;
0223 }
0224 
0225 static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc)
0226 {
0227     struct ata_port *ap = qc->ap;
0228     struct pata_icside_state *state = ap->host->private_data;
0229     unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE;
0230 
0231     /*
0232      * We are simplex; BUG if we try to fiddle with DMA
0233      * while it's active.
0234      */
0235     BUG_ON(dma_channel_active(state->dma));
0236 
0237     /*
0238      * Route the DMA signals to the correct interface
0239      */
0240     writeb(state->port[ap->port_no].port_sel, state->ioc_base);
0241 
0242     set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]);
0243     set_dma_sg(state->dma, qc->sg, qc->n_elem);
0244     set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ);
0245 
0246     /* issue r/w command */
0247     ap->ops->sff_exec_command(ap, &qc->tf);
0248 }
0249 
0250 static void pata_icside_bmdma_start(struct ata_queued_cmd *qc)
0251 {
0252     struct ata_port *ap = qc->ap;
0253     struct pata_icside_state *state = ap->host->private_data;
0254 
0255     BUG_ON(dma_channel_active(state->dma));
0256     enable_dma(state->dma);
0257 }
0258 
0259 static void pata_icside_bmdma_stop(struct ata_queued_cmd *qc)
0260 {
0261     struct ata_port *ap = qc->ap;
0262     struct pata_icside_state *state = ap->host->private_data;
0263 
0264     disable_dma(state->dma);
0265 
0266     /* see ata_bmdma_stop */
0267     ata_sff_dma_pause(ap);
0268 }
0269 
0270 static u8 pata_icside_bmdma_status(struct ata_port *ap)
0271 {
0272     struct pata_icside_state *state = ap->host->private_data;
0273     void __iomem *irq_port;
0274 
0275     irq_port = state->irq_port + (ap->port_no ? ICS_ARCIN_V6_INTRSTAT_2 :
0276                             ICS_ARCIN_V6_INTRSTAT_1);
0277 
0278     return readb(irq_port) & 1 ? ATA_DMA_INTR : 0;
0279 }
0280 
0281 static int icside_dma_init(struct pata_icside_info *info)
0282 {
0283     struct pata_icside_state *state = info->state;
0284     struct expansion_card *ec = info->ec;
0285     int i;
0286 
0287     for (i = 0; i < ATA_MAX_DEVICES; i++) {
0288         state->port[0].speed[i] = 480;
0289         state->port[1].speed[i] = 480;
0290     }
0291 
0292     if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
0293         state->dma = ec->dma;
0294         info->mwdma_mask = ATA_MWDMA2;
0295     }
0296 
0297     return 0;
0298 }
0299 
0300 
0301 static struct scsi_host_template pata_icside_sht = {
0302     ATA_BASE_SHT(DRV_NAME),
0303     .sg_tablesize       = SG_MAX_SEGMENTS,
0304     .dma_boundary       = IOMD_DMA_BOUNDARY,
0305 };
0306 
0307 static void pata_icside_postreset(struct ata_link *link, unsigned int *classes)
0308 {
0309     struct ata_port *ap = link->ap;
0310     struct pata_icside_state *state = ap->host->private_data;
0311 
0312     if (classes[0] != ATA_DEV_NONE || classes[1] != ATA_DEV_NONE)
0313         return ata_sff_postreset(link, classes);
0314 
0315     state->port[ap->port_no].disabled = 1;
0316 
0317     if (state->type == ICS_TYPE_V6) {
0318         /*
0319          * Disable interrupts from this port, otherwise we
0320          * receive spurious interrupts from the floating
0321          * interrupt line.
0322          */
0323         void __iomem *irq_port = state->irq_port +
0324                 (ap->port_no ? ICS_ARCIN_V6_INTROFFSET_2 : ICS_ARCIN_V6_INTROFFSET_1);
0325         readb(irq_port);
0326     }
0327 }
0328 
0329 static struct ata_port_operations pata_icside_port_ops = {
0330     .inherits       = &ata_bmdma_port_ops,
0331     /* no need to build any PRD tables for DMA */
0332     .qc_prep        = ata_noop_qc_prep,
0333     .sff_data_xfer      = ata_sff_data_xfer32,
0334     .bmdma_setup        = pata_icside_bmdma_setup,
0335     .bmdma_start        = pata_icside_bmdma_start,
0336     .bmdma_stop     = pata_icside_bmdma_stop,
0337     .bmdma_status       = pata_icside_bmdma_status,
0338 
0339     .cable_detect       = ata_cable_40wire,
0340     .set_dmamode        = pata_icside_set_dmamode,
0341     .postreset      = pata_icside_postreset,
0342 
0343     .port_start     = ATA_OP_NULL,  /* don't need PRD table */
0344 };
0345 
0346 static void pata_icside_setup_ioaddr(struct ata_port *ap, void __iomem *base,
0347                      struct pata_icside_info *info,
0348                      const struct portinfo *port)
0349 {
0350     struct ata_ioports *ioaddr = &ap->ioaddr;
0351     void __iomem *cmd = base + port->dataoffset;
0352 
0353     ioaddr->cmd_addr    = cmd;
0354     ioaddr->data_addr   = cmd + (ATA_REG_DATA    << port->stepping);
0355     ioaddr->error_addr  = cmd + (ATA_REG_ERR     << port->stepping);
0356     ioaddr->feature_addr    = cmd + (ATA_REG_FEATURE << port->stepping);
0357     ioaddr->nsect_addr  = cmd + (ATA_REG_NSECT   << port->stepping);
0358     ioaddr->lbal_addr   = cmd + (ATA_REG_LBAL    << port->stepping);
0359     ioaddr->lbam_addr   = cmd + (ATA_REG_LBAM    << port->stepping);
0360     ioaddr->lbah_addr   = cmd + (ATA_REG_LBAH    << port->stepping);
0361     ioaddr->device_addr = cmd + (ATA_REG_DEVICE  << port->stepping);
0362     ioaddr->status_addr = cmd + (ATA_REG_STATUS  << port->stepping);
0363     ioaddr->command_addr    = cmd + (ATA_REG_CMD     << port->stepping);
0364 
0365     ioaddr->ctl_addr    = base + port->ctrloffset;
0366     ioaddr->altstatus_addr  = ioaddr->ctl_addr;
0367 
0368     ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
0369               info->raw_base + port->dataoffset,
0370               info->raw_base + port->ctrloffset);
0371 
0372     if (info->raw_ioc_base)
0373         ata_port_desc(ap, "iocbase 0x%lx", info->raw_ioc_base);
0374 }
0375 
0376 static int pata_icside_register_v5(struct pata_icside_info *info)
0377 {
0378     struct pata_icside_state *state = info->state;
0379     void __iomem *base;
0380 
0381     base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0);
0382     if (!base)
0383         return -ENOMEM;
0384 
0385     state->irq_port = base;
0386 
0387     info->base = base;
0388     info->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
0389     info->irqmask = 1;
0390     info->irqops = &pata_icside_ops_arcin_v5;
0391     info->nr_ports = 1;
0392     info->port[0] = &pata_icside_portinfo_v5;
0393 
0394     info->raw_base = ecard_resource_start(info->ec, ECARD_RES_MEMC);
0395 
0396     return 0;
0397 }
0398 
0399 static int pata_icside_register_v6(struct pata_icside_info *info)
0400 {
0401     struct pata_icside_state *state = info->state;
0402     struct expansion_card *ec = info->ec;
0403     void __iomem *ioc_base, *easi_base;
0404     unsigned int sel = 0;
0405 
0406     ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
0407     if (!ioc_base)
0408         return -ENOMEM;
0409 
0410     easi_base = ioc_base;
0411 
0412     if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
0413         easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
0414         if (!easi_base)
0415             return -ENOMEM;
0416 
0417         /*
0418          * Enable access to the EASI region.
0419          */
0420         sel = 1 << 5;
0421     }
0422 
0423     writeb(sel, ioc_base);
0424 
0425     state->irq_port = easi_base;
0426     state->ioc_base = ioc_base;
0427     state->port[0].port_sel = sel;
0428     state->port[1].port_sel = sel | 1;
0429 
0430     info->base = easi_base;
0431     info->irqops = &pata_icside_ops_arcin_v6;
0432     info->nr_ports = 2;
0433     info->port[0] = &pata_icside_portinfo_v6_1;
0434     info->port[1] = &pata_icside_portinfo_v6_2;
0435 
0436     info->raw_base = ecard_resource_start(ec, ECARD_RES_EASI);
0437     info->raw_ioc_base = ecard_resource_start(ec, ECARD_RES_IOCFAST);
0438 
0439     return icside_dma_init(info);
0440 }
0441 
0442 static int pata_icside_add_ports(struct pata_icside_info *info)
0443 {
0444     struct expansion_card *ec = info->ec;
0445     struct ata_host *host;
0446     int i;
0447 
0448     if (info->irqaddr) {
0449         ec->irqaddr = info->irqaddr;
0450         ec->irqmask = info->irqmask;
0451     }
0452     if (info->irqops)
0453         ecard_setirq(ec, info->irqops, info->state);
0454 
0455     /*
0456      * Be on the safe side - disable interrupts
0457      */
0458     ec->ops->irqdisable(ec, ec->irq);
0459 
0460     host = ata_host_alloc(&ec->dev, info->nr_ports);
0461     if (!host)
0462         return -ENOMEM;
0463 
0464     host->private_data = info->state;
0465     host->flags = ATA_HOST_SIMPLEX;
0466 
0467     for (i = 0; i < info->nr_ports; i++) {
0468         struct ata_port *ap = host->ports[i];
0469 
0470         ap->pio_mask = ATA_PIO4;
0471         ap->mwdma_mask = info->mwdma_mask;
0472         ap->flags |= ATA_FLAG_SLAVE_POSS;
0473         ap->ops = &pata_icside_port_ops;
0474 
0475         pata_icside_setup_ioaddr(ap, info->base, info, info->port[i]);
0476     }
0477 
0478     return ata_host_activate(host, ec->irq, ata_bmdma_interrupt, 0,
0479                  &pata_icside_sht);
0480 }
0481 
0482 static int pata_icside_probe(struct expansion_card *ec,
0483                  const struct ecard_id *id)
0484 {
0485     struct pata_icside_state *state;
0486     struct pata_icside_info info;
0487     void __iomem *idmem;
0488     int ret;
0489 
0490     ret = ecard_request_resources(ec);
0491     if (ret)
0492         goto out;
0493 
0494     state = devm_kzalloc(&ec->dev, sizeof(*state), GFP_KERNEL);
0495     if (!state) {
0496         ret = -ENOMEM;
0497         goto release;
0498     }
0499 
0500     state->type = ICS_TYPE_NOTYPE;
0501     state->dma = NO_DMA;
0502 
0503     idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
0504     if (idmem) {
0505         unsigned int type;
0506 
0507         type = readb(idmem + ICS_IDENT_OFFSET) & 1;
0508         type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
0509         type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
0510         type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
0511         ecardm_iounmap(ec, idmem);
0512 
0513         state->type = type;
0514     }
0515 
0516     memset(&info, 0, sizeof(info));
0517     info.state = state;
0518     info.ec = ec;
0519 
0520     switch (state->type) {
0521     case ICS_TYPE_A3IN:
0522         dev_warn(&ec->dev, "A3IN unsupported\n");
0523         ret = -ENODEV;
0524         break;
0525 
0526     case ICS_TYPE_A3USER:
0527         dev_warn(&ec->dev, "A3USER unsupported\n");
0528         ret = -ENODEV;
0529         break;
0530 
0531     case ICS_TYPE_V5:
0532         ret = pata_icside_register_v5(&info);
0533         break;
0534 
0535     case ICS_TYPE_V6:
0536         ret = pata_icside_register_v6(&info);
0537         break;
0538 
0539     default:
0540         dev_warn(&ec->dev, "unknown interface type\n");
0541         ret = -ENODEV;
0542         break;
0543     }
0544 
0545     if (ret == 0)
0546         ret = pata_icside_add_ports(&info);
0547 
0548     if (ret == 0)
0549         goto out;
0550 
0551  release:
0552     ecard_release_resources(ec);
0553  out:
0554     return ret;
0555 }
0556 
0557 static void pata_icside_shutdown(struct expansion_card *ec)
0558 {
0559     struct ata_host *host = ecard_get_drvdata(ec);
0560     unsigned long flags;
0561 
0562     /*
0563      * Disable interrupts from this card.  We need to do
0564      * this before disabling EASI since we may be accessing
0565      * this register via that region.
0566      */
0567     local_irq_save(flags);
0568     ec->ops->irqdisable(ec, ec->irq);
0569     local_irq_restore(flags);
0570 
0571     /*
0572      * Reset the ROM pointer so that we can read the ROM
0573      * after a soft reboot.  This also disables access to
0574      * the IDE taskfile via the EASI region.
0575      */
0576     if (host) {
0577         struct pata_icside_state *state = host->private_data;
0578         if (state->ioc_base)
0579             writeb(0, state->ioc_base);
0580     }
0581 }
0582 
0583 static void pata_icside_remove(struct expansion_card *ec)
0584 {
0585     struct ata_host *host = ecard_get_drvdata(ec);
0586     struct pata_icside_state *state = host->private_data;
0587 
0588     ata_host_detach(host);
0589 
0590     pata_icside_shutdown(ec);
0591 
0592     /*
0593      * don't NULL out the drvdata - devres/libata wants it
0594      * to free the ata_host structure.
0595      */
0596     if (state->dma != NO_DMA)
0597         free_dma(state->dma);
0598 
0599     ecard_release_resources(ec);
0600 }
0601 
0602 static const struct ecard_id pata_icside_ids[] = {
0603     { MANU_ICS,  PROD_ICS_IDE  },
0604     { MANU_ICS2, PROD_ICS2_IDE },
0605     { 0xffff, 0xffff }
0606 };
0607 
0608 static struct ecard_driver pata_icside_driver = {
0609     .probe      = pata_icside_probe,
0610     .remove     = pata_icside_remove,
0611     .shutdown   = pata_icside_shutdown,
0612     .id_table   = pata_icside_ids,
0613     .drv = {
0614         .name   = DRV_NAME,
0615     },
0616 };
0617 
0618 static int __init pata_icside_init(void)
0619 {
0620     return ecard_register_driver(&pata_icside_driver);
0621 }
0622 
0623 static void __exit pata_icside_exit(void)
0624 {
0625     ecard_remove_driver(&pata_icside_driver);
0626 }
0627 
0628 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
0629 MODULE_LICENSE("GPL");
0630 MODULE_DESCRIPTION("ICS PATA driver");
0631 
0632 module_init(pata_icside_init);
0633 module_exit(pata_icside_exit);
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