drivers/ata/pata_hpt3x3.c

0001 /*
0002  *  pata_hpt3x3     -   HPT3x3 driver
0003  *  (c) Copyright 2005-2006 Red Hat
0004  *
0005  *  Was pata_hpt34x but the naming was confusing as it supported the
0006  *  343 and 363 so it has been renamed.
0007  *
0008  *  Based on:
0009  *  linux/drivers/ide/pci/hpt34x.c      Version 0.40    Sept 10, 2002
0010  *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
0011  *
0012  *  May be copied or modified under the terms of the GNU General Public
0013  *  License
0014  */
0015
0016 #include <linux/kernel.h>
0017 #include <linux/module.h>
0018 #include <linux/pci.h>
0019 #include <linux/blkdev.h>
0020 #include <linux/delay.h>
0021 #include <scsi/scsi_host.h>
0022 #include <linux/libata.h>
0023
0024 #define DRV_NAME    "pata_hpt3x3"
0025 #define DRV_VERSION "0.6.1"
0026
0027 /**
0028  *  hpt3x3_set_piomode      -   PIO setup
0029  *  @ap: ATA interface
0030  *  @adev: device on the interface
0031  *
0032  *  Set our PIO requirements. This is fairly simple on the HPT3x3 as
0033  *  all we have to do is clear the MWDMA and UDMA bits then load the
0034  *  mode number.
0035  */
0036
0037 static void hpt3x3_set_piomode(struct ata_port *ap, struct ata_device *adev)
0038 {
0039     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0040     u32 r1, r2;
0041     int dn = 2 * ap->port_no + adev->devno;
0042
0043     pci_read_config_dword(pdev, 0x44, &r1);
0044     pci_read_config_dword(pdev, 0x48, &r2);
0045     /* Load the PIO timing number */
0046     r1 &= ~(7 << (3 * dn));
0047     r1 |= (adev->pio_mode - XFER_PIO_0) << (3 * dn);
0048     r2 &= ~(0x11 << dn);    /* Clear MWDMA and UDMA bits */
0049
0050     pci_write_config_dword(pdev, 0x44, r1);
0051     pci_write_config_dword(pdev, 0x48, r2);
0052 }
0053
0054 #if defined(CONFIG_PATA_HPT3X3_DMA)
0055 /**
0056  *  hpt3x3_set_dmamode      -   DMA timing setup
0057  *  @ap: ATA interface
0058  *  @adev: Device being configured
0059  *
0060  *  Set up the channel for MWDMA or UDMA modes. Much the same as with
0061  *  PIO, load the mode number and then set MWDMA or UDMA flag.
0062  *
0063  *  0x44 : bit 0-2 master mode, 3-5 slave mode, etc
0064  *  0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
0065  */
0066
0067 static void hpt3x3_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0068 {
0069     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0070     u32 r1, r2;
0071     int dn = 2 * ap->port_no + adev->devno;
0072     int mode_num = adev->dma_mode & 0x0F;
0073
0074     pci_read_config_dword(pdev, 0x44, &r1);
0075     pci_read_config_dword(pdev, 0x48, &r2);
0076     /* Load the timing number */
0077     r1 &= ~(7 << (3 * dn));
0078     r1 |= (mode_num << (3 * dn));
0079     r2 &= ~(0x11 << dn);    /* Clear MWDMA and UDMA bits */
0080
0081     if (adev->dma_mode >= XFER_UDMA_0)
0082         r2 |= (0x01 << dn); /* Ultra mode */
0083     else
0084         r2 |= (0x10 << dn); /* MWDMA */
0085
0086     pci_write_config_dword(pdev, 0x44, r1);
0087     pci_write_config_dword(pdev, 0x48, r2);
0088 }
0089
0090 /**
0091  *  hpt3x3_freeze       -   DMA workaround
0092  *  @ap: port to freeze
0093  *
0094  *  When freezing an HPT3x3 we must stop any pending DMA before
0095  *  writing to the control register or the chip will hang
0096  */
0097
0098 static void hpt3x3_freeze(struct ata_port *ap)
0099 {
0100     void __iomem *mmio = ap->ioaddr.bmdma_addr;
0101
0102     iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ ATA_DMA_START,
0103             mmio + ATA_DMA_CMD);
0104     ata_sff_dma_pause(ap);
0105     ata_sff_freeze(ap);
0106 }
0107
0108 /**
0109  *  hpt3x3_bmdma_setup  -   DMA workaround
0110  *  @qc: Queued command
0111  *
0112  *  When issuing BMDMA we must clean up the error/active bits in
0113  *  software on this device
0114  */
0115
0116 static void hpt3x3_bmdma_setup(struct ata_queued_cmd *qc)
0117 {
0118     struct ata_port *ap = qc->ap;
0119     u8 r = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
0120     r |= ATA_DMA_INTR | ATA_DMA_ERR;
0121     iowrite8(r, ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
0122     return ata_bmdma_setup(qc);
0123 }
0124
0125 /**
0126  *  hpt3x3_atapi_dma    -   ATAPI DMA check
0127  *  @qc: Queued command
0128  *
0129  *  Just say no - we don't do ATAPI DMA
0130  */
0131
0132 static int hpt3x3_atapi_dma(struct ata_queued_cmd *qc)
0133 {
0134     return 1;
0135 }
0136
0137 #endif /* CONFIG_PATA_HPT3X3_DMA */
0138
0139 static struct scsi_host_template hpt3x3_sht = {
0140     ATA_BMDMA_SHT(DRV_NAME),
0141 };
0142
0143 static struct ata_port_operations hpt3x3_port_ops = {
0144     .inherits   = &ata_bmdma_port_ops,
0145     .cable_detect   = ata_cable_40wire,
0146     .set_piomode    = hpt3x3_set_piomode,
0147 #if defined(CONFIG_PATA_HPT3X3_DMA)
0148     .set_dmamode    = hpt3x3_set_dmamode,
0149     .bmdma_setup    = hpt3x3_bmdma_setup,
0150     .check_atapi_dma= hpt3x3_atapi_dma,
0151     .freeze     = hpt3x3_freeze,
0152 #endif
0153
0154 };
0155
0156 /**
0157  *  hpt3x3_init_chipset -   chip setup
0158  *  @dev: PCI device
0159  *
0160  *  Perform the setup required at boot and on resume.
0161  */
0162
0163 static void hpt3x3_init_chipset(struct pci_dev *dev)
0164 {
0165     u16 cmd;
0166     /* Initialize the board */
0167     pci_write_config_word(dev, 0x80, 0x00);
0168     /* Check if it is a 343 or a 363. 363 has COMMAND_MEMORY set */
0169     pci_read_config_word(dev, PCI_COMMAND, &cmd);
0170     if (cmd & PCI_COMMAND_MEMORY)
0171         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
0172     else
0173         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
0174 }
0175
0176 /**
0177  *  hpt3x3_init_one     -   Initialise an HPT343/363
0178  *  @pdev: PCI device
0179  *  @id: Entry in match table
0180  *
0181  *  Perform basic initialisation. We set the device up so we access all
0182  *  ports via BAR4. This is necessary to work around errata.
0183  */
0184
0185 static int hpt3x3_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
0186 {
0187     static const struct ata_port_info info = {
0188         .flags = ATA_FLAG_SLAVE_POSS,
0189         .pio_mask = ATA_PIO4,
0190 #if defined(CONFIG_PATA_HPT3X3_DMA)
0191         /* Further debug needed */
0192         .mwdma_mask = ATA_MWDMA2,
0193         .udma_mask = ATA_UDMA2,
0194 #endif
0195         .port_ops = &hpt3x3_port_ops
0196     };
0197     /* Register offsets of taskfiles in BAR4 area */
0198     static const u8 offset_cmd[2] = { 0x20, 0x28 };
0199     static const u8 offset_ctl[2] = { 0x36, 0x3E };
0200     const struct ata_port_info *ppi[] = { &info, NULL };
0201     struct ata_host *host;
0202     int i, rc;
0203     void __iomem *base;
0204
0205     hpt3x3_init_chipset(pdev);
0206
0207     ata_print_version_once(&pdev->dev, DRV_VERSION);
0208
0209     host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
0210     if (!host)
0211         return -ENOMEM;
0212     /* acquire resources and fill host */
0213     rc = pcim_enable_device(pdev);
0214     if (rc)
0215         return rc;
0216
0217     /* Everything is relative to BAR4 if we set up this way */
0218     rc = pcim_iomap_regions(pdev, 1 << 4, DRV_NAME);
0219     if (rc == -EBUSY)
0220         pcim_pin_device(pdev);
0221     if (rc)
0222         return rc;
0223     host->iomap = pcim_iomap_table(pdev);
0224     rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
0225     if (rc)
0226         return rc;
0227
0228     base = host->iomap[4];  /* Bus mastering base */
0229
0230     for (i = 0; i < host->n_ports; i++) {
0231         struct ata_port *ap = host->ports[i];
0232         struct ata_ioports *ioaddr = &ap->ioaddr;
0233
0234         ioaddr->cmd_addr = base + offset_cmd[i];
0235         ioaddr->altstatus_addr =
0236         ioaddr->ctl_addr = base + offset_ctl[i];
0237         ioaddr->scr_addr = NULL;
0238         ata_sff_std_ports(ioaddr);
0239         ioaddr->bmdma_addr = base + 8 * i;
0240
0241         ata_port_pbar_desc(ap, 4, -1, "ioport");
0242         ata_port_pbar_desc(ap, 4, offset_cmd[i], "cmd");
0243     }
0244     pci_set_master(pdev);
0245     return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
0246                  IRQF_SHARED, &hpt3x3_sht);
0247 }
0248
0249 #ifdef CONFIG_PM_SLEEP
0250 static int hpt3x3_reinit_one(struct pci_dev *dev)
0251 {
0252     struct ata_host *host = pci_get_drvdata(dev);
0253     int rc;
0254
0255     rc = ata_pci_device_do_resume(dev);
0256     if (rc)
0257         return rc;
0258
0259     hpt3x3_init_chipset(dev);
0260
0261     ata_host_resume(host);
0262     return 0;
0263 }
0264 #endif
0265
0266 static const struct pci_device_id hpt3x3[] = {
0267     { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), },
0268
0269     { },
0270 };
0271
0272 static struct pci_driver hpt3x3_pci_driver = {
0273     .name       = DRV_NAME,
0274     .id_table   = hpt3x3,
0275     .probe      = hpt3x3_init_one,
0276     .remove     = ata_pci_remove_one,
0277 #ifdef CONFIG_PM_SLEEP
0278     .suspend    = ata_pci_device_suspend,
0279     .resume     = hpt3x3_reinit_one,
0280 #endif
0281 };
0282
0283 module_pci_driver(hpt3x3_pci_driver);
0284
0285 MODULE_AUTHOR("Alan Cox");
0286 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT343/363");
0287 MODULE_LICENSE("GPL");
0288 MODULE_DEVICE_TABLE(pci, hpt3x3);
0289 MODULE_VERSION(DRV_VERSION);