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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Libata driver for the HighPoint 371N, 372N, and 302N UDMA66 ATA controllers.
0004  *
0005  * This driver is heavily based upon:
0006  *
0007  * linux/drivers/ide/pci/hpt366.c       Version 0.36    April 25, 2003
0008  *
0009  * Copyright (C) 1999-2003      Andre Hedrick <andre@linux-ide.org>
0010  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
0011  * Portions Copyright (C) 2003      Red Hat Inc
0012  * Portions Copyright (C) 2005-2010 MontaVista Software, Inc.
0013  *
0014  *
0015  * TODO
0016  *  Work out best PLL policy
0017  */
0018 #include <linux/kernel.h>
0019 #include <linux/module.h>
0020 #include <linux/pci.h>
0021 #include <linux/blkdev.h>
0022 #include <linux/delay.h>
0023 #include <scsi/scsi_host.h>
0024 #include <linux/libata.h>
0025 
0026 #define DRV_NAME    "pata_hpt3x2n"
0027 #define DRV_VERSION "0.3.19"
0028 
0029 enum {
0030     PCI66       =   (1 << 1),
0031     USE_DPLL    =   (1 << 0)
0032 };
0033 
0034 struct hpt_clock {
0035     u8  xfer_speed;
0036     u32 timing;
0037 };
0038 
0039 /* key for bus clock timings
0040  * bit
0041  * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
0042  *        cycles = value + 1
0043  * 4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
0044  *        cycles = value + 1
0045  * 9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
0046  *        register access.
0047  * 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file
0048  *        register access.
0049  * 18:20  udma_cycle_time. Clock cycles for UDMA xfer.
0050  * 21     CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
0051  * 22:24  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
0052  * 25:27  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
0053  *        register access.
0054  * 28     UDMA enable.
0055  * 29     DMA  enable.
0056  * 30     PIO_MST enable. If set, the chip is in bus master mode during
0057  *        PIO xfer.
0058  * 31     FIFO enable. Only for PIO.
0059  */
0060 
0061 /* 66MHz DPLL clocks */
0062 
0063 static struct hpt_clock hpt3x2n_clocks[] = {
0064     {   XFER_UDMA_7,    0x1c869c62  },
0065     {   XFER_UDMA_6,    0x1c869c62  },
0066     {   XFER_UDMA_5,    0x1c8a9c62  },
0067     {   XFER_UDMA_4,    0x1c8a9c62  },
0068     {   XFER_UDMA_3,    0x1c8e9c62  },
0069     {   XFER_UDMA_2,    0x1c929c62  },
0070     {   XFER_UDMA_1,    0x1c9a9c62  },
0071     {   XFER_UDMA_0,    0x1c829c62  },
0072 
0073     {   XFER_MW_DMA_2,  0x2c829c62  },
0074     {   XFER_MW_DMA_1,  0x2c829c66  },
0075     {   XFER_MW_DMA_0,  0x2c829d2e  },
0076 
0077     {   XFER_PIO_4, 0x0c829c62  },
0078     {   XFER_PIO_3, 0x0c829c84  },
0079     {   XFER_PIO_2, 0x0c829ca6  },
0080     {   XFER_PIO_1, 0x0d029d26  },
0081     {   XFER_PIO_0, 0x0d029d5e  },
0082 };
0083 
0084 /**
0085  *  hpt3x2n_find_mode   -   reset the hpt3x2n bus
0086  *  @ap: ATA port
0087  *  @speed: transfer mode
0088  *
0089  *  Return the 32bit register programming information for this channel
0090  *  that matches the speed provided. For the moment the clocks table
0091  *  is hard coded but easy to change. This will be needed if we use
0092  *  different DPLLs
0093  */
0094 
0095 static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
0096 {
0097     struct hpt_clock *clocks = hpt3x2n_clocks;
0098 
0099     while (clocks->xfer_speed) {
0100         if (clocks->xfer_speed == speed)
0101             return clocks->timing;
0102         clocks++;
0103     }
0104     BUG();
0105     return 0xffffffffU; /* silence compiler warning */
0106 }
0107 
0108 /**
0109  *  hpt372n_filter  -   mode selection filter
0110  *  @adev: ATA device
0111  *  @mask: mode mask
0112  *
0113  *  The Marvell bridge chips used on the HighPoint SATA cards do not seem
0114  *  to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
0115  */
0116 static unsigned int hpt372n_filter(struct ata_device *adev, unsigned int mask)
0117 {
0118     if (ata_id_is_sata(adev->id))
0119         mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
0120 
0121     return mask;
0122 }
0123 
0124 /**
0125  *  hpt3x2n_cable_detect    -   Detect the cable type
0126  *  @ap: ATA port to detect on
0127  *
0128  *  Return the cable type attached to this port
0129  */
0130 
0131 static int hpt3x2n_cable_detect(struct ata_port *ap)
0132 {
0133     u8 scr2, ata66;
0134     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0135 
0136     pci_read_config_byte(pdev, 0x5B, &scr2);
0137     pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
0138 
0139     udelay(10); /* debounce */
0140 
0141     /* Cable register now active */
0142     pci_read_config_byte(pdev, 0x5A, &ata66);
0143     /* Restore state */
0144     pci_write_config_byte(pdev, 0x5B, scr2);
0145 
0146     if (ata66 & (2 >> ap->port_no))
0147         return ATA_CBL_PATA40;
0148     else
0149         return ATA_CBL_PATA80;
0150 }
0151 
0152 /**
0153  *  hpt3x2n_pre_reset   -   reset the hpt3x2n bus
0154  *  @link: ATA link to reset
0155  *  @deadline: deadline jiffies for the operation
0156  *
0157  *  Perform the initial reset handling for the 3x2n series controllers.
0158  *  Reset the hardware and state machine,
0159  */
0160 
0161 static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
0162 {
0163     struct ata_port *ap = link->ap;
0164     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0165     static const struct pci_bits hpt3x2n_enable_bits[] = {
0166         { 0x50, 1, 0x04, 0x04 },
0167         { 0x54, 1, 0x04, 0x04 }
0168     };
0169     u8 mcr2;
0170 
0171     if (!pci_test_config_bits(pdev, &hpt3x2n_enable_bits[ap->port_no]))
0172         return -ENOENT;
0173 
0174     /* Reset the state machine */
0175     pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
0176     udelay(100);
0177 
0178     /* Fast interrupt prediction disable, hold off interrupt disable */
0179     pci_read_config_byte(pdev, 0x51 + 4 * ap->port_no, &mcr2);
0180     mcr2 &= ~0x07;
0181     pci_write_config_byte(pdev, 0x51 + 4 * ap->port_no, mcr2);
0182 
0183     return ata_sff_prereset(link, deadline);
0184 }
0185 
0186 static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev,
0187                  u8 mode)
0188 {
0189     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0190     int addr = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
0191     u32 reg, timing, mask;
0192 
0193     /* Determine timing mask and find matching mode entry */
0194     if (mode < XFER_MW_DMA_0)
0195         mask = 0xcfc3ffff;
0196     else if (mode < XFER_UDMA_0)
0197         mask = 0x31c001ff;
0198     else
0199         mask = 0x303c0000;
0200 
0201     timing = hpt3x2n_find_mode(ap, mode);
0202 
0203     pci_read_config_dword(pdev, addr, &reg);
0204     reg = (reg & ~mask) | (timing & mask);
0205     pci_write_config_dword(pdev, addr, reg);
0206 }
0207 
0208 /**
0209  *  hpt3x2n_set_piomode     -   PIO setup
0210  *  @ap: ATA interface
0211  *  @adev: device on the interface
0212  *
0213  *  Perform PIO mode setup.
0214  */
0215 
0216 static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
0217 {
0218     hpt3x2n_set_mode(ap, adev, adev->pio_mode);
0219 }
0220 
0221 /**
0222  *  hpt3x2n_set_dmamode     -   DMA timing setup
0223  *  @ap: ATA interface
0224  *  @adev: Device being configured
0225  *
0226  *  Set up the channel for MWDMA or UDMA modes.
0227  */
0228 
0229 static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0230 {
0231     hpt3x2n_set_mode(ap, adev, adev->dma_mode);
0232 }
0233 
0234 /**
0235  *  hpt3x2n_bmdma_stop      -   DMA engine stop
0236  *  @qc: ATA command
0237  *
0238  *  Clean up after the HPT3x2n and later DMA engine
0239  */
0240 
0241 static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
0242 {
0243     struct ata_port *ap = qc->ap;
0244     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0245     int mscreg = 0x50 + 4 * ap->port_no;
0246     u8 bwsr_stat, msc_stat;
0247 
0248     pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
0249     pci_read_config_byte(pdev, mscreg, &msc_stat);
0250     if (bwsr_stat & (1 << ap->port_no))
0251         pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
0252     ata_bmdma_stop(qc);
0253 }
0254 
0255 /**
0256  *  hpt3x2n_set_clock   -   clock control
0257  *  @ap: ATA port
0258  *  @source: 0x21 or 0x23 for PLL or PCI sourced clock
0259  *
0260  *  Switch the ATA bus clock between the PLL and PCI clock sources
0261  *  while correctly isolating the bus and resetting internal logic
0262  *
0263  *  We must use the DPLL for
0264  *  -   writing
0265  *  -   second channel UDMA7 (SATA ports) or higher
0266  *  -   66MHz PCI
0267  *
0268  *  or we will underclock the device and get reduced performance.
0269  */
0270 
0271 static void hpt3x2n_set_clock(struct ata_port *ap, int source)
0272 {
0273     void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8;
0274 
0275     /* Tristate the bus */
0276     iowrite8(0x80, bmdma+0x73);
0277     iowrite8(0x80, bmdma+0x77);
0278 
0279     /* Switch clock and reset channels */
0280     iowrite8(source, bmdma+0x7B);
0281     iowrite8(0xC0, bmdma+0x79);
0282 
0283     /* Reset state machines, avoid enabling the disabled channels */
0284     iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70);
0285     iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74);
0286 
0287     /* Complete reset */
0288     iowrite8(0x00, bmdma+0x79);
0289 
0290     /* Reconnect channels to bus */
0291     iowrite8(0x00, bmdma+0x73);
0292     iowrite8(0x00, bmdma+0x77);
0293 }
0294 
0295 static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
0296 {
0297     long flags = (long)ap->host->private_data;
0298 
0299     /* See if we should use the DPLL */
0300     if (writing)
0301         return USE_DPLL;    /* Needed for write */
0302     if (flags & PCI66)
0303         return USE_DPLL;    /* Needed at 66Mhz */
0304     return 0;
0305 }
0306 
0307 static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc)
0308 {
0309     struct ata_port *ap = qc->ap;
0310     struct ata_port *alt = ap->host->ports[ap->port_no ^ 1];
0311     int rc, flags = (long)ap->host->private_data;
0312     int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
0313 
0314     /* First apply the usual rules */
0315     rc = ata_std_qc_defer(qc);
0316     if (rc != 0)
0317         return rc;
0318 
0319     if ((flags & USE_DPLL) != dpll && alt->qc_active)
0320         return ATA_DEFER_PORT;
0321     return 0;
0322 }
0323 
0324 static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
0325 {
0326     struct ata_port *ap = qc->ap;
0327     int flags = (long)ap->host->private_data;
0328     int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
0329 
0330     if ((flags & USE_DPLL) != dpll) {
0331         flags &= ~USE_DPLL;
0332         flags |= dpll;
0333         ap->host->private_data = (void *)(long)flags;
0334 
0335         hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23);
0336     }
0337     return ata_bmdma_qc_issue(qc);
0338 }
0339 
0340 static struct scsi_host_template hpt3x2n_sht = {
0341     ATA_BMDMA_SHT(DRV_NAME),
0342 };
0343 
0344 /*
0345  *  Configuration for HPT302N/371N.
0346  */
0347 
0348 static struct ata_port_operations hpt3xxn_port_ops = {
0349     .inherits   = &ata_bmdma_port_ops,
0350 
0351     .bmdma_stop = hpt3x2n_bmdma_stop,
0352 
0353     .qc_defer   = hpt3x2n_qc_defer,
0354     .qc_issue   = hpt3x2n_qc_issue,
0355 
0356     .cable_detect   = hpt3x2n_cable_detect,
0357     .set_piomode    = hpt3x2n_set_piomode,
0358     .set_dmamode    = hpt3x2n_set_dmamode,
0359     .prereset   = hpt3x2n_pre_reset,
0360 };
0361 
0362 /*
0363  *  Configuration for HPT372N. Same as 302N/371N but we have a mode filter.
0364  */
0365 
0366 static struct ata_port_operations hpt372n_port_ops = {
0367     .inherits   = &hpt3xxn_port_ops,
0368     .mode_filter    = &hpt372n_filter,
0369 };
0370 
0371 /**
0372  *  hpt3xn_calibrate_dpll       -   Calibrate the DPLL loop
0373  *  @dev: PCI device
0374  *
0375  *  Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
0376  *  succeeds
0377  */
0378 
0379 static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
0380 {
0381     u8 reg5b;
0382     u32 reg5c;
0383     int tries;
0384 
0385     for (tries = 0; tries < 0x5000; tries++) {
0386         udelay(50);
0387         pci_read_config_byte(dev, 0x5b, &reg5b);
0388         if (reg5b & 0x80) {
0389             /* See if it stays set */
0390             for (tries = 0; tries < 0x1000; tries++) {
0391                 pci_read_config_byte(dev, 0x5b, &reg5b);
0392                 /* Failed ? */
0393                 if ((reg5b & 0x80) == 0)
0394                     return 0;
0395             }
0396             /* Turn off tuning, we have the DPLL set */
0397             pci_read_config_dword(dev, 0x5c, &reg5c);
0398             pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
0399             return 1;
0400         }
0401     }
0402     /* Never went stable */
0403     return 0;
0404 }
0405 
0406 static int hpt3x2n_pci_clock(struct pci_dev *pdev, unsigned int base)
0407 {
0408     unsigned int freq;
0409     u32 fcnt;
0410 
0411     /*
0412      * Some devices do not let this value be accessed via PCI space
0413      * according to the old driver.
0414      */
0415     fcnt = inl(pci_resource_start(pdev, 4) + 0x90);
0416     if ((fcnt >> 12) != 0xABCDE) {
0417         u32 total = 0;
0418         int i;
0419         u16 sr;
0420 
0421         dev_warn(&pdev->dev, "BIOS clock data not set\n");
0422 
0423         /* This is the process the HPT371 BIOS is reported to use */
0424         for (i = 0; i < 128; i++) {
0425             pci_read_config_word(pdev, 0x78, &sr);
0426             total += sr & 0x1FF;
0427             udelay(15);
0428         }
0429         fcnt = total / 128;
0430     }
0431     fcnt &= 0x1FF;
0432 
0433     freq = (fcnt * base) / 192; /* in MHz */
0434 
0435     /* Clamp to bands */
0436     if (freq < 40)
0437         return 33;
0438     if (freq < 45)
0439         return 40;
0440     if (freq < 55)
0441         return 50;
0442     return 66;
0443 }
0444 
0445 /**
0446  *  hpt3x2n_init_one        -   Initialise an HPT37X/302
0447  *  @dev: PCI device
0448  *  @id: Entry in match table
0449  *
0450  *  Initialise an HPT3x2n device. There are some interesting complications
0451  *  here. Firstly the chip may report 366 and be one of several variants.
0452  *  Secondly all the timings depend on the clock for the chip which we must
0453  *  detect and look up
0454  *
0455  *  This is the known chip mappings. It may be missing a couple of later
0456  *  releases.
0457  *
0458  *  Chip version        PCI     Rev Notes
0459  *  HPT372          4 (HPT366)  5   Other driver
0460  *  HPT372N         4 (HPT366)  6   UDMA133
0461  *  HPT372          5 (HPT372)  1   Other driver
0462  *  HPT372N         5 (HPT372)  2   UDMA133
0463  *  HPT302          6 (HPT302)  *   Other driver
0464  *  HPT302N         6 (HPT302)  > 1 UDMA133
0465  *  HPT371          7 (HPT371)  *   Other driver
0466  *  HPT371N         7 (HPT371)  > 1 UDMA133
0467  *  HPT374          8 (HPT374)  *   Other driver
0468  *  HPT372N         9 (HPT372N) *   UDMA133
0469  *
0470  *  (1) UDMA133 support depends on the bus clock
0471  */
0472 
0473 static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
0474 {
0475     /* HPT372N - UDMA133 */
0476     static const struct ata_port_info info_hpt372n = {
0477         .flags = ATA_FLAG_SLAVE_POSS,
0478         .pio_mask = ATA_PIO4,
0479         .mwdma_mask = ATA_MWDMA2,
0480         .udma_mask = ATA_UDMA6,
0481         .port_ops = &hpt372n_port_ops
0482     };
0483     /* HPT302N and HPT371N - UDMA133 */
0484     static const struct ata_port_info info_hpt3xxn = {
0485         .flags = ATA_FLAG_SLAVE_POSS,
0486         .pio_mask = ATA_PIO4,
0487         .mwdma_mask = ATA_MWDMA2,
0488         .udma_mask = ATA_UDMA6,
0489         .port_ops = &hpt3xxn_port_ops
0490     };
0491     const struct ata_port_info *ppi[] = { &info_hpt3xxn, NULL };
0492     u8 rev = dev->revision;
0493     u8 irqmask;
0494     unsigned int pci_mhz;
0495     unsigned int f_low, f_high;
0496     int adjust;
0497     unsigned long iobase = pci_resource_start(dev, 4);
0498     void *hpriv = (void *)USE_DPLL;
0499     int rc;
0500 
0501     rc = pcim_enable_device(dev);
0502     if (rc)
0503         return rc;
0504 
0505     switch (dev->device) {
0506     case PCI_DEVICE_ID_TTI_HPT366:
0507         /* 372N if rev >= 6 */
0508         if (rev < 6)
0509             return -ENODEV;
0510         goto hpt372n;
0511     case PCI_DEVICE_ID_TTI_HPT371:
0512         /* 371N if rev >= 2 */
0513         if (rev < 2)
0514             return -ENODEV;
0515         break;
0516     case PCI_DEVICE_ID_TTI_HPT372:
0517         /* 372N if rev >= 2 */
0518         if (rev < 2)
0519             return -ENODEV;
0520         goto hpt372n;
0521     case PCI_DEVICE_ID_TTI_HPT302:
0522         /* 302N if rev >= 2 */
0523         if (rev < 2)
0524             return -ENODEV;
0525         break;
0526     case PCI_DEVICE_ID_TTI_HPT372N:
0527 hpt372n:
0528         ppi[0] = &info_hpt372n;
0529         break;
0530     default:
0531         dev_err(&dev->dev,"PCI table is bogus, please report (%d)\n",
0532             dev->device);
0533         return -ENODEV;
0534     }
0535 
0536     /* Ok so this is a chip we support */
0537 
0538     pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
0539     pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
0540     pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
0541     pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
0542 
0543     pci_read_config_byte(dev, 0x5A, &irqmask);
0544     irqmask &= ~0x10;
0545     pci_write_config_byte(dev, 0x5a, irqmask);
0546 
0547     /*
0548      * HPT371 chips physically have only one channel, the secondary one,
0549      * but the primary channel registers do exist!  Go figure...
0550      * So,  we manually disable the non-existing channel here
0551      * (if the BIOS hasn't done this already).
0552      */
0553     if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
0554         u8 mcr1;
0555         pci_read_config_byte(dev, 0x50, &mcr1);
0556         mcr1 &= ~0x04;
0557         pci_write_config_byte(dev, 0x50, mcr1);
0558     }
0559 
0560     /*
0561      * Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
0562      * 50 for UDMA100. Right now we always use 66
0563      */
0564 
0565     pci_mhz = hpt3x2n_pci_clock(dev, 77);
0566 
0567     f_low = (pci_mhz * 48) / 66;    /* PCI Mhz for 66Mhz DPLL */
0568     f_high = f_low + 2;     /* Tolerance */
0569 
0570     pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
0571     /* PLL clock */
0572     pci_write_config_byte(dev, 0x5B, 0x21);
0573 
0574     /* Unlike the 37x we don't try jiggling the frequency */
0575     for (adjust = 0; adjust < 8; adjust++) {
0576         if (hpt3xn_calibrate_dpll(dev))
0577             break;
0578         pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
0579     }
0580     if (adjust == 8) {
0581         dev_err(&dev->dev, "DPLL did not stabilize!\n");
0582         return -ENODEV;
0583     }
0584 
0585     dev_info(&dev->dev, "bus clock %dMHz, using 66MHz DPLL\n", pci_mhz);
0586 
0587     /*
0588      * Set our private data up. We only need a few flags
0589      * so we use it directly.
0590      */
0591     if (pci_mhz > 60)
0592         hpriv = (void *)(PCI66 | USE_DPLL);
0593 
0594     /*
0595      * On  HPT371N, if ATA clock is 66 MHz we must set bit 2 in
0596      * the MISC. register to stretch the UltraDMA Tss timing.
0597      * NOTE: This register is only writeable via I/O space.
0598      */
0599     if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
0600         outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
0601 
0602     /* Now kick off ATA set up */
0603     return ata_pci_bmdma_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0);
0604 }
0605 
0606 static const struct pci_device_id hpt3x2n[] = {
0607     { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
0608     { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
0609     { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
0610     { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
0611     { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
0612 
0613     { },
0614 };
0615 
0616 static struct pci_driver hpt3x2n_pci_driver = {
0617     .name       = DRV_NAME,
0618     .id_table   = hpt3x2n,
0619     .probe      = hpt3x2n_init_one,
0620     .remove     = ata_pci_remove_one
0621 };
0622 
0623 module_pci_driver(hpt3x2n_pci_driver);
0624 
0625 MODULE_AUTHOR("Alan Cox");
0626 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3xxN");
0627 MODULE_LICENSE("GPL");
0628 MODULE_DEVICE_TABLE(pci, hpt3x2n);
0629 MODULE_VERSION(DRV_VERSION);
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