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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Libata driver for the highpoint 37x and 30x UDMA66 ATA controllers.
0004  *
0005  * This driver is heavily based upon:
0006  *
0007  * linux/drivers/ide/pci/hpt366.c       Version 0.36    April 25, 2003
0008  *
0009  * Copyright (C) 1999-2003      Andre Hedrick <andre@linux-ide.org>
0010  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
0011  * Portions Copyright (C) 2003      Red Hat Inc
0012  * Portions Copyright (C) 2005-2010 MontaVista Software, Inc.
0013  *
0014  * TODO
0015  *  Look into engine reset on timeout errors. Should not be required.
0016  */
0017 #include <linux/kernel.h>
0018 #include <linux/module.h>
0019 #include <linux/pci.h>
0020 #include <linux/blkdev.h>
0021 #include <linux/delay.h>
0022 #include <scsi/scsi_host.h>
0023 #include <linux/libata.h>
0024 
0025 #define DRV_NAME    "pata_hpt37x"
0026 #define DRV_VERSION "0.6.30"
0027 
0028 struct hpt_clock {
0029     u8  xfer_speed;
0030     u32 timing;
0031 };
0032 
0033 struct hpt_chip {
0034     const char *name;
0035     unsigned int base;
0036     struct hpt_clock const *clocks[4];
0037 };
0038 
0039 /* key for bus clock timings
0040  * bit
0041  * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
0042  *        cycles = value + 1
0043  * 4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
0044  *        cycles = value + 1
0045  * 9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
0046  *        register access.
0047  * 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file
0048  *        register access.
0049  * 18:20  udma_cycle_time. Clock cycles for UDMA xfer.
0050  * 21     CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
0051  * 22:24  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
0052  * 25:27  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
0053  *        register access.
0054  * 28     UDMA enable.
0055  * 29     DMA  enable.
0056  * 30     PIO_MST enable. If set, the chip is in bus master mode during
0057  *        PIO xfer.
0058  * 31     FIFO enable. Only for PIO.
0059  */
0060 
0061 static struct hpt_clock hpt37x_timings_33[] = {
0062     { XFER_UDMA_6,      0x12446231 },   /* 0x12646231 ?? */
0063     { XFER_UDMA_5,      0x12446231 },
0064     { XFER_UDMA_4,      0x12446231 },
0065     { XFER_UDMA_3,      0x126c6231 },
0066     { XFER_UDMA_2,      0x12486231 },
0067     { XFER_UDMA_1,      0x124c6233 },
0068     { XFER_UDMA_0,      0x12506297 },
0069 
0070     { XFER_MW_DMA_2,    0x22406c31 },
0071     { XFER_MW_DMA_1,    0x22406c33 },
0072     { XFER_MW_DMA_0,    0x22406c97 },
0073 
0074     { XFER_PIO_4,       0x06414e31 },
0075     { XFER_PIO_3,       0x06414e42 },
0076     { XFER_PIO_2,       0x06414e53 },
0077     { XFER_PIO_1,       0x06814e93 },
0078     { XFER_PIO_0,       0x06814ea7 }
0079 };
0080 
0081 static struct hpt_clock hpt37x_timings_50[] = {
0082     { XFER_UDMA_6,      0x12848242 },
0083     { XFER_UDMA_5,      0x12848242 },
0084     { XFER_UDMA_4,      0x12ac8242 },
0085     { XFER_UDMA_3,      0x128c8242 },
0086     { XFER_UDMA_2,      0x120c8242 },
0087     { XFER_UDMA_1,      0x12148254 },
0088     { XFER_UDMA_0,      0x121882ea },
0089 
0090     { XFER_MW_DMA_2,    0x22808242 },
0091     { XFER_MW_DMA_1,    0x22808254 },
0092     { XFER_MW_DMA_0,    0x228082ea },
0093 
0094     { XFER_PIO_4,       0x0a81f442 },
0095     { XFER_PIO_3,       0x0a81f443 },
0096     { XFER_PIO_2,       0x0a81f454 },
0097     { XFER_PIO_1,       0x0ac1f465 },
0098     { XFER_PIO_0,       0x0ac1f48a }
0099 };
0100 
0101 static struct hpt_clock hpt37x_timings_66[] = {
0102     { XFER_UDMA_6,      0x1c869c62 },
0103     { XFER_UDMA_5,      0x1cae9c62 },   /* 0x1c8a9c62 */
0104     { XFER_UDMA_4,      0x1c8a9c62 },
0105     { XFER_UDMA_3,      0x1c8e9c62 },
0106     { XFER_UDMA_2,      0x1c929c62 },
0107     { XFER_UDMA_1,      0x1c9a9c62 },
0108     { XFER_UDMA_0,      0x1c829c62 },
0109 
0110     { XFER_MW_DMA_2,    0x2c829c62 },
0111     { XFER_MW_DMA_1,    0x2c829c66 },
0112     { XFER_MW_DMA_0,    0x2c829d2e },
0113 
0114     { XFER_PIO_4,       0x0c829c62 },
0115     { XFER_PIO_3,       0x0c829c84 },
0116     { XFER_PIO_2,       0x0c829ca6 },
0117     { XFER_PIO_1,       0x0d029d26 },
0118     { XFER_PIO_0,       0x0d029d5e }
0119 };
0120 
0121 
0122 static const struct hpt_chip hpt370 = {
0123     "HPT370",
0124     48,
0125     {
0126         hpt37x_timings_33,
0127         NULL,
0128         NULL,
0129         NULL
0130     }
0131 };
0132 
0133 static const struct hpt_chip hpt370a = {
0134     "HPT370A",
0135     48,
0136     {
0137         hpt37x_timings_33,
0138         NULL,
0139         hpt37x_timings_50,
0140         NULL
0141     }
0142 };
0143 
0144 static const struct hpt_chip hpt372 = {
0145     "HPT372",
0146     55,
0147     {
0148         hpt37x_timings_33,
0149         NULL,
0150         hpt37x_timings_50,
0151         hpt37x_timings_66
0152     }
0153 };
0154 
0155 static const struct hpt_chip hpt302 = {
0156     "HPT302",
0157     66,
0158     {
0159         hpt37x_timings_33,
0160         NULL,
0161         hpt37x_timings_50,
0162         hpt37x_timings_66
0163     }
0164 };
0165 
0166 static const struct hpt_chip hpt371 = {
0167     "HPT371",
0168     66,
0169     {
0170         hpt37x_timings_33,
0171         NULL,
0172         hpt37x_timings_50,
0173         hpt37x_timings_66
0174     }
0175 };
0176 
0177 static const struct hpt_chip hpt372a = {
0178     "HPT372A",
0179     66,
0180     {
0181         hpt37x_timings_33,
0182         NULL,
0183         hpt37x_timings_50,
0184         hpt37x_timings_66
0185     }
0186 };
0187 
0188 static const struct hpt_chip hpt374 = {
0189     "HPT374",
0190     48,
0191     {
0192         hpt37x_timings_33,
0193         NULL,
0194         NULL,
0195         NULL
0196     }
0197 };
0198 
0199 /**
0200  *  hpt37x_find_mode    -   reset the hpt37x bus
0201  *  @ap: ATA port
0202  *  @speed: transfer mode
0203  *
0204  *  Return the 32bit register programming information for this channel
0205  *  that matches the speed provided.
0206  */
0207 
0208 static u32 hpt37x_find_mode(struct ata_port *ap, int speed)
0209 {
0210     struct hpt_clock *clocks = ap->host->private_data;
0211 
0212     while (clocks->xfer_speed) {
0213         if (clocks->xfer_speed == speed)
0214             return clocks->timing;
0215         clocks++;
0216     }
0217     BUG();
0218     return 0xffffffffU; /* silence compiler warning */
0219 }
0220 
0221 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
0222                    const char * const list[])
0223 {
0224     unsigned char model_num[ATA_ID_PROD_LEN + 1];
0225     int i;
0226 
0227     ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
0228 
0229     i = match_string(list, -1, model_num);
0230     if (i >= 0) {
0231         ata_dev_warn(dev, "%s is not supported for %s\n",
0232                  modestr, list[i]);
0233         return 1;
0234     }
0235     return 0;
0236 }
0237 
0238 static const char * const bad_ata33[] = {
0239     "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
0240     "Maxtor 90845U3", "Maxtor 90650U2",
0241     "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
0242     "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
0243     "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
0244     "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
0245     "Maxtor 90510D4",
0246     "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
0247     "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
0248     "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
0249     "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
0250     "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
0251     NULL
0252 };
0253 
0254 static const char * const bad_ata100_5[] = {
0255     "IBM-DTLA-307075",
0256     "IBM-DTLA-307060",
0257     "IBM-DTLA-307045",
0258     "IBM-DTLA-307030",
0259     "IBM-DTLA-307020",
0260     "IBM-DTLA-307015",
0261     "IBM-DTLA-305040",
0262     "IBM-DTLA-305030",
0263     "IBM-DTLA-305020",
0264     "IC35L010AVER07-0",
0265     "IC35L020AVER07-0",
0266     "IC35L030AVER07-0",
0267     "IC35L040AVER07-0",
0268     "IC35L060AVER07-0",
0269     "WDC AC310200R",
0270     NULL
0271 };
0272 
0273 /**
0274  *  hpt370_filter   -   mode selection filter
0275  *  @adev: ATA device
0276  *  @mask: mode mask
0277  *
0278  *  Block UDMA on devices that cause trouble with this controller.
0279  */
0280 
0281 static unsigned int hpt370_filter(struct ata_device *adev, unsigned int mask)
0282 {
0283     if (adev->class == ATA_DEV_ATA) {
0284         if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
0285             mask &= ~ATA_MASK_UDMA;
0286         if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
0287             mask &= ~(0xE0 << ATA_SHIFT_UDMA);
0288     }
0289     return mask;
0290 }
0291 
0292 /**
0293  *  hpt370a_filter  -   mode selection filter
0294  *  @adev: ATA device
0295  *  @mask: mode mask
0296  *
0297  *  Block UDMA on devices that cause trouble with this controller.
0298  */
0299 
0300 static unsigned int hpt370a_filter(struct ata_device *adev, unsigned int mask)
0301 {
0302     if (adev->class == ATA_DEV_ATA) {
0303         if (hpt_dma_blacklisted(adev, "UDMA100", bad_ata100_5))
0304             mask &= ~(0xE0 << ATA_SHIFT_UDMA);
0305     }
0306     return mask;
0307 }
0308 
0309 /**
0310  *  hpt372_filter   -   mode selection filter
0311  *  @adev: ATA device
0312  *  @mask: mode mask
0313  *
0314  *  The Marvell bridge chips used on the HighPoint SATA cards do not seem
0315  *  to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
0316  */
0317 static unsigned int hpt372_filter(struct ata_device *adev, unsigned int mask)
0318 {
0319     if (ata_id_is_sata(adev->id))
0320         mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
0321 
0322     return mask;
0323 }
0324 
0325 /**
0326  *  hpt37x_cable_detect -   Detect the cable type
0327  *  @ap: ATA port to detect on
0328  *
0329  *  Return the cable type attached to this port
0330  */
0331 
0332 static int hpt37x_cable_detect(struct ata_port *ap)
0333 {
0334     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0335     u8 scr2, ata66;
0336 
0337     pci_read_config_byte(pdev, 0x5B, &scr2);
0338     pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
0339 
0340     udelay(10); /* debounce */
0341 
0342     /* Cable register now active */
0343     pci_read_config_byte(pdev, 0x5A, &ata66);
0344     /* Restore state */
0345     pci_write_config_byte(pdev, 0x5B, scr2);
0346 
0347     if (ata66 & (2 >> ap->port_no))
0348         return ATA_CBL_PATA40;
0349     else
0350         return ATA_CBL_PATA80;
0351 }
0352 
0353 /**
0354  *  hpt374_fn1_cable_detect -   Detect the cable type
0355  *  @ap: ATA port to detect on
0356  *
0357  *  Return the cable type attached to this port
0358  */
0359 
0360 static int hpt374_fn1_cable_detect(struct ata_port *ap)
0361 {
0362     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0363     unsigned int mcrbase = 0x50 + 4 * ap->port_no;
0364     u16 mcr3;
0365     u8 ata66;
0366 
0367     /* Do the extra channel work */
0368     pci_read_config_word(pdev, mcrbase + 2, &mcr3);
0369     /* Set bit 15 of 0x52 to enable TCBLID as input */
0370     pci_write_config_word(pdev, mcrbase + 2, mcr3 | 0x8000);
0371     pci_read_config_byte(pdev, 0x5A, &ata66);
0372     /* Reset TCBLID/FCBLID to output */
0373     pci_write_config_word(pdev, mcrbase + 2, mcr3);
0374 
0375     if (ata66 & (2 >> ap->port_no))
0376         return ATA_CBL_PATA40;
0377     else
0378         return ATA_CBL_PATA80;
0379 }
0380 
0381 /**
0382  *  hpt37x_pre_reset    -   reset the hpt37x bus
0383  *  @link: ATA link to reset
0384  *  @deadline: deadline jiffies for the operation
0385  *
0386  *  Perform the initial reset handling for the HPT37x.
0387  */
0388 
0389 static int hpt37x_pre_reset(struct ata_link *link, unsigned long deadline)
0390 {
0391     struct ata_port *ap = link->ap;
0392     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0393     static const struct pci_bits hpt37x_enable_bits[] = {
0394         { 0x50, 1, 0x04, 0x04 },
0395         { 0x54, 1, 0x04, 0x04 }
0396     };
0397     u8 mcr2;
0398 
0399     if (!pci_test_config_bits(pdev, &hpt37x_enable_bits[ap->port_no]))
0400         return -ENOENT;
0401 
0402     /* Reset the state machine */
0403     pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
0404     udelay(100);
0405 
0406     /*
0407      * Disable the "fast interrupt" prediction.  Don't hold off
0408      * on interrupts. (== 0x01 despite what the docs say)
0409      */
0410     pci_read_config_byte(pdev, 0x51 + 4 * ap->port_no, &mcr2);
0411     /* Is it HPT370/A? */
0412     if (pdev->device == PCI_DEVICE_ID_TTI_HPT366 && pdev->revision < 5) {
0413         mcr2 &= ~0x02;
0414         mcr2 |= 0x01;
0415     } else {
0416         mcr2 &= ~0x07;
0417     }
0418     pci_write_config_byte(pdev, 0x51 + 4 * ap->port_no, mcr2);
0419 
0420     return ata_sff_prereset(link, deadline);
0421 }
0422 
0423 static void hpt37x_set_mode(struct ata_port *ap, struct ata_device *adev,
0424                 u8 mode)
0425 {
0426     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0427     int addr = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
0428     u32 reg, timing, mask;
0429 
0430     /* Determine timing mask and find matching mode entry */
0431     if (mode < XFER_MW_DMA_0)
0432         mask = 0xcfc3ffff;
0433     else if (mode < XFER_UDMA_0)
0434         mask = 0x31c001ff;
0435     else
0436         mask = 0x303c0000;
0437 
0438     timing = hpt37x_find_mode(ap, mode);
0439 
0440     pci_read_config_dword(pdev, addr, &reg);
0441     reg = (reg & ~mask) | (timing & mask);
0442     pci_write_config_dword(pdev, addr, reg);
0443 }
0444 /**
0445  *  hpt37x_set_piomode      -   PIO setup
0446  *  @ap: ATA interface
0447  *  @adev: device on the interface
0448  *
0449  *  Perform PIO mode setup.
0450  */
0451 
0452 static void hpt37x_set_piomode(struct ata_port *ap, struct ata_device *adev)
0453 {
0454     hpt37x_set_mode(ap, adev, adev->pio_mode);
0455 }
0456 
0457 /**
0458  *  hpt37x_set_dmamode      -   DMA timing setup
0459  *  @ap: ATA interface
0460  *  @adev: Device being configured
0461  *
0462  *  Set up the channel for MWDMA or UDMA modes.
0463  */
0464 
0465 static void hpt37x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0466 {
0467     hpt37x_set_mode(ap, adev, adev->dma_mode);
0468 }
0469 
0470 /**
0471  *  hpt370_bmdma_stop       -   DMA engine stop
0472  *  @qc: ATA command
0473  *
0474  *  Work around the HPT370 DMA engine.
0475  */
0476 
0477 static void hpt370_bmdma_stop(struct ata_queued_cmd *qc)
0478 {
0479     struct ata_port *ap = qc->ap;
0480     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0481     void __iomem *bmdma = ap->ioaddr.bmdma_addr;
0482     u8 dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
0483     u8 dma_cmd;
0484 
0485     if (dma_stat & ATA_DMA_ACTIVE) {
0486         udelay(20);
0487         dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
0488     }
0489     if (dma_stat & ATA_DMA_ACTIVE) {
0490         /* Clear the engine */
0491         pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
0492         udelay(10);
0493         /* Stop DMA */
0494         dma_cmd = ioread8(bmdma + ATA_DMA_CMD);
0495         iowrite8(dma_cmd & ~ATA_DMA_START, bmdma + ATA_DMA_CMD);
0496         /* Clear Error */
0497         dma_stat = ioread8(bmdma + ATA_DMA_STATUS);
0498         iowrite8(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR,
0499              bmdma + ATA_DMA_STATUS);
0500         /* Clear the engine */
0501         pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
0502         udelay(10);
0503     }
0504     ata_bmdma_stop(qc);
0505 }
0506 
0507 /**
0508  *  hpt37x_bmdma_stop       -   DMA engine stop
0509  *  @qc: ATA command
0510  *
0511  *  Clean up after the HPT372 and later DMA engine
0512  */
0513 
0514 static void hpt37x_bmdma_stop(struct ata_queued_cmd *qc)
0515 {
0516     struct ata_port *ap = qc->ap;
0517     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0518     int mscreg = 0x50 + 4 * ap->port_no;
0519     u8 bwsr_stat, msc_stat;
0520 
0521     pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
0522     pci_read_config_byte(pdev, mscreg, &msc_stat);
0523     if (bwsr_stat & (1 << ap->port_no))
0524         pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
0525     ata_bmdma_stop(qc);
0526 }
0527 
0528 
0529 static struct scsi_host_template hpt37x_sht = {
0530     ATA_BMDMA_SHT(DRV_NAME),
0531 };
0532 
0533 /*
0534  *  Configuration for HPT370
0535  */
0536 
0537 static struct ata_port_operations hpt370_port_ops = {
0538     .inherits   = &ata_bmdma_port_ops,
0539 
0540     .bmdma_stop = hpt370_bmdma_stop,
0541 
0542     .mode_filter    = hpt370_filter,
0543     .cable_detect   = hpt37x_cable_detect,
0544     .set_piomode    = hpt37x_set_piomode,
0545     .set_dmamode    = hpt37x_set_dmamode,
0546     .prereset   = hpt37x_pre_reset,
0547 };
0548 
0549 /*
0550  *  Configuration for HPT370A. Close to 370 but less filters
0551  */
0552 
0553 static struct ata_port_operations hpt370a_port_ops = {
0554     .inherits   = &hpt370_port_ops,
0555     .mode_filter    = hpt370a_filter,
0556 };
0557 
0558 /*
0559  *  Configuration for HPT371 and HPT302.
0560  */
0561 
0562 static struct ata_port_operations hpt302_port_ops = {
0563     .inherits   = &ata_bmdma_port_ops,
0564 
0565     .bmdma_stop = hpt37x_bmdma_stop,
0566 
0567     .cable_detect   = hpt37x_cable_detect,
0568     .set_piomode    = hpt37x_set_piomode,
0569     .set_dmamode    = hpt37x_set_dmamode,
0570     .prereset   = hpt37x_pre_reset,
0571 };
0572 
0573 /*
0574  *  Configuration for HPT372. Mode setting works like 371 and 302
0575  *  but we have a mode filter.
0576  */
0577 
0578 static struct ata_port_operations hpt372_port_ops = {
0579     .inherits   = &hpt302_port_ops,
0580     .mode_filter    = hpt372_filter,
0581 };
0582 
0583 /*
0584  *  Configuration for HPT374. Mode setting and filtering works like 372
0585  *  but we have a different cable detection procedure for function 1.
0586  */
0587 
0588 static struct ata_port_operations hpt374_fn1_port_ops = {
0589     .inherits   = &hpt372_port_ops,
0590     .cable_detect   = hpt374_fn1_cable_detect,
0591 };
0592 
0593 /**
0594  *  hpt37x_clock_slot   -   Turn timing to PC clock entry
0595  *  @freq: Reported frequency in MHz
0596  *
0597  *  Turn the timing data into a clock slot (0 for 33, 1 for 40, 2 for 50
0598  *  and 3 for 66Mhz)
0599  */
0600 
0601 static int hpt37x_clock_slot(unsigned int freq)
0602 {
0603     if (freq < 40)
0604         return 0;   /* 33Mhz slot */
0605     if (freq < 45)
0606         return 1;   /* 40Mhz slot */
0607     if (freq < 55)
0608         return 2;   /* 50Mhz slot */
0609     return 3;       /* 60Mhz slot */
0610 }
0611 
0612 /**
0613  *  hpt37x_calibrate_dpll       -   Calibrate the DPLL loop
0614  *  @dev: PCI device
0615  *
0616  *  Perform a calibration cycle on the HPT37x DPLL. Returns 1 if this
0617  *  succeeds
0618  */
0619 
0620 static int hpt37x_calibrate_dpll(struct pci_dev *dev)
0621 {
0622     u8 reg5b;
0623     u32 reg5c;
0624     int tries;
0625 
0626     for (tries = 0; tries < 0x5000; tries++) {
0627         udelay(50);
0628         pci_read_config_byte(dev, 0x5b, &reg5b);
0629         if (reg5b & 0x80) {
0630             /* See if it stays set */
0631             for (tries = 0; tries < 0x1000; tries++) {
0632                 pci_read_config_byte(dev, 0x5b, &reg5b);
0633                 /* Failed ? */
0634                 if ((reg5b & 0x80) == 0)
0635                     return 0;
0636             }
0637             /* Turn off tuning, we have the DPLL set */
0638             pci_read_config_dword(dev, 0x5c, &reg5c);
0639             pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
0640             return 1;
0641         }
0642     }
0643     /* Never went stable */
0644     return 0;
0645 }
0646 
0647 static int hpt37x_pci_clock(struct pci_dev *pdev, unsigned int base)
0648 {
0649     unsigned int freq;
0650     u32 fcnt;
0651 
0652     /*
0653      * Some devices do not let this value be accessed via PCI space
0654      * according to the old driver. In addition we must use the value
0655      * from FN 0 on the HPT374.
0656      */
0657     if (pdev->device == PCI_DEVICE_ID_TTI_HPT374 &&
0658         (PCI_FUNC(pdev->devfn) & 1)) {
0659         struct pci_dev *pdev_fn0;
0660 
0661         pdev_fn0 = pci_get_slot(pdev->bus, pdev->devfn - 1);
0662         /* Someone hot plugged the controller on us? */
0663         if (!pdev_fn0)
0664             return 0;
0665         fcnt = inl(pci_resource_start(pdev_fn0, 4) + 0x90);
0666         pci_dev_put(pdev_fn0);
0667     } else  {
0668         fcnt = inl(pci_resource_start(pdev, 4) + 0x90);
0669     }
0670 
0671     if ((fcnt >> 12) != 0xABCDE) {
0672         u32 total = 0;
0673         int i;
0674         u16 sr;
0675 
0676         dev_warn(&pdev->dev, "BIOS clock data not set\n");
0677 
0678         /* This is the process the HPT371 BIOS is reported to use */
0679         for (i = 0; i < 128; i++) {
0680             pci_read_config_word(pdev, 0x78, &sr);
0681             total += sr & 0x1FF;
0682             udelay(15);
0683         }
0684         fcnt = total / 128;
0685     }
0686     fcnt &= 0x1FF;
0687 
0688     freq = (fcnt * base) / 192; /* in MHz */
0689 
0690     /* Clamp to bands */
0691     if (freq < 40)
0692         return 33;
0693     if (freq < 45)
0694         return 40;
0695     if (freq < 55)
0696         return 50;
0697     return 66;
0698 }
0699 
0700 /**
0701  *  hpt37x_init_one     -   Initialise an HPT37X/302
0702  *  @dev: PCI device
0703  *  @id: Entry in match table
0704  *
0705  *  Initialise an HPT37x device. There are some interesting complications
0706  *  here. Firstly the chip may report 366 and be one of several variants.
0707  *  Secondly all the timings depend on the clock for the chip which we must
0708  *  detect and look up
0709  *
0710  *  This is the known chip mappings. It may be missing a couple of later
0711  *  releases.
0712  *
0713  *  Chip version        PCI     Rev Notes
0714  *  HPT366          4 (HPT366)  0   Other driver
0715  *  HPT366          4 (HPT366)  1   Other driver
0716  *  HPT368          4 (HPT366)  2   Other driver
0717  *  HPT370          4 (HPT366)  3   UDMA100
0718  *  HPT370A         4 (HPT366)  4   UDMA100
0719  *  HPT372          4 (HPT366)  5   UDMA133 (1)
0720  *  HPT372N         4 (HPT366)  6   Other driver
0721  *  HPT372A         5 (HPT372)  1   UDMA133 (1)
0722  *  HPT372N         5 (HPT372)  2   Other driver
0723  *  HPT302          6 (HPT302)  1   UDMA133
0724  *  HPT302N         6 (HPT302)  2   Other driver
0725  *  HPT371          7 (HPT371)  *   UDMA133
0726  *  HPT374          8 (HPT374)  *   UDMA133 4 channel
0727  *  HPT372N         9 (HPT372N) *   Other driver
0728  *
0729  *  (1) UDMA133 support depends on the bus clock
0730  */
0731 
0732 static int hpt37x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
0733 {
0734     /* HPT370 - UDMA100 */
0735     static const struct ata_port_info info_hpt370 = {
0736         .flags = ATA_FLAG_SLAVE_POSS,
0737         .pio_mask = ATA_PIO4,
0738         .mwdma_mask = ATA_MWDMA2,
0739         .udma_mask = ATA_UDMA5,
0740         .port_ops = &hpt370_port_ops
0741     };
0742     /* HPT370A - UDMA100 */
0743     static const struct ata_port_info info_hpt370a = {
0744         .flags = ATA_FLAG_SLAVE_POSS,
0745         .pio_mask = ATA_PIO4,
0746         .mwdma_mask = ATA_MWDMA2,
0747         .udma_mask = ATA_UDMA5,
0748         .port_ops = &hpt370a_port_ops
0749     };
0750     /* HPT370 - UDMA66 */
0751     static const struct ata_port_info info_hpt370_33 = {
0752         .flags = ATA_FLAG_SLAVE_POSS,
0753         .pio_mask = ATA_PIO4,
0754         .mwdma_mask = ATA_MWDMA2,
0755         .udma_mask = ATA_UDMA4,
0756         .port_ops = &hpt370_port_ops
0757     };
0758     /* HPT370A - UDMA66 */
0759     static const struct ata_port_info info_hpt370a_33 = {
0760         .flags = ATA_FLAG_SLAVE_POSS,
0761         .pio_mask = ATA_PIO4,
0762         .mwdma_mask = ATA_MWDMA2,
0763         .udma_mask = ATA_UDMA4,
0764         .port_ops = &hpt370a_port_ops
0765     };
0766     /* HPT372 - UDMA133 */
0767     static const struct ata_port_info info_hpt372 = {
0768         .flags = ATA_FLAG_SLAVE_POSS,
0769         .pio_mask = ATA_PIO4,
0770         .mwdma_mask = ATA_MWDMA2,
0771         .udma_mask = ATA_UDMA6,
0772         .port_ops = &hpt372_port_ops
0773     };
0774     /* HPT371, 302 - UDMA133 */
0775     static const struct ata_port_info info_hpt302 = {
0776         .flags = ATA_FLAG_SLAVE_POSS,
0777         .pio_mask = ATA_PIO4,
0778         .mwdma_mask = ATA_MWDMA2,
0779         .udma_mask = ATA_UDMA6,
0780         .port_ops = &hpt302_port_ops
0781     };
0782     /* HPT374 - UDMA100, function 1 uses different cable_detect method */
0783     static const struct ata_port_info info_hpt374_fn0 = {
0784         .flags = ATA_FLAG_SLAVE_POSS,
0785         .pio_mask = ATA_PIO4,
0786         .mwdma_mask = ATA_MWDMA2,
0787         .udma_mask = ATA_UDMA5,
0788         .port_ops = &hpt372_port_ops
0789     };
0790     static const struct ata_port_info info_hpt374_fn1 = {
0791         .flags = ATA_FLAG_SLAVE_POSS,
0792         .pio_mask = ATA_PIO4,
0793         .mwdma_mask = ATA_MWDMA2,
0794         .udma_mask = ATA_UDMA5,
0795         .port_ops = &hpt374_fn1_port_ops
0796     };
0797 
0798     static const int MHz[4] = { 33, 40, 50, 66 };
0799     void *private_data = NULL;
0800     const struct ata_port_info *ppi[] = { NULL, NULL };
0801     u8 rev = dev->revision;
0802     u8 irqmask;
0803     u8 mcr1;
0804     unsigned int freq; /* MHz */
0805     int prefer_dpll = 1;
0806 
0807     unsigned long iobase = pci_resource_start(dev, 4);
0808 
0809     const struct hpt_chip *chip_table;
0810     int clock_slot;
0811     int rc;
0812 
0813     rc = pcim_enable_device(dev);
0814     if (rc)
0815         return rc;
0816 
0817     switch (dev->device) {
0818     case PCI_DEVICE_ID_TTI_HPT366:
0819         /* May be a later chip in disguise. Check */
0820         /* Older chips are in the HPT366 driver. Ignore them */
0821         if (rev < 3)
0822             return -ENODEV;
0823         /* N series chips have their own driver. Ignore */
0824         if (rev == 6)
0825             return -ENODEV;
0826 
0827         switch (rev) {
0828         case 3:
0829             ppi[0] = &info_hpt370;
0830             chip_table = &hpt370;
0831             prefer_dpll = 0;
0832             break;
0833         case 4:
0834             ppi[0] = &info_hpt370a;
0835             chip_table = &hpt370a;
0836             prefer_dpll = 0;
0837             break;
0838         case 5:
0839             ppi[0] = &info_hpt372;
0840             chip_table = &hpt372;
0841             break;
0842         default:
0843             dev_err(&dev->dev,
0844                 "Unknown HPT366 subtype, please report (%d)\n",
0845                    rev);
0846             return -ENODEV;
0847         }
0848         break;
0849     case PCI_DEVICE_ID_TTI_HPT372:
0850         /* 372N if rev >= 2 */
0851         if (rev >= 2)
0852             return -ENODEV;
0853         ppi[0] = &info_hpt372;
0854         chip_table = &hpt372a;
0855         break;
0856     case PCI_DEVICE_ID_TTI_HPT302:
0857         /* 302N if rev > 1 */
0858         if (rev > 1)
0859             return -ENODEV;
0860         ppi[0] = &info_hpt302;
0861         /* Check this */
0862         chip_table = &hpt302;
0863         break;
0864     case PCI_DEVICE_ID_TTI_HPT371:
0865         if (rev > 1)
0866             return -ENODEV;
0867         ppi[0] = &info_hpt302;
0868         chip_table = &hpt371;
0869         /*
0870          * Single channel device, master is not present but the BIOS
0871          * (or us for non x86) must mark it absent
0872          */
0873         pci_read_config_byte(dev, 0x50, &mcr1);
0874         mcr1 &= ~0x04;
0875         pci_write_config_byte(dev, 0x50, mcr1);
0876         break;
0877     case PCI_DEVICE_ID_TTI_HPT374:
0878         chip_table = &hpt374;
0879         if (!(PCI_FUNC(dev->devfn) & 1))
0880             *ppi = &info_hpt374_fn0;
0881         else
0882             *ppi = &info_hpt374_fn1;
0883         break;
0884     default:
0885         dev_err(&dev->dev, "PCI table is bogus, please report (%d)\n",
0886             dev->device);
0887         return -ENODEV;
0888     }
0889     /* Ok so this is a chip we support */
0890 
0891     pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
0892     pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
0893     pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
0894     pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
0895 
0896     pci_read_config_byte(dev, 0x5A, &irqmask);
0897     irqmask &= ~0x10;
0898     pci_write_config_byte(dev, 0x5a, irqmask);
0899 
0900     /*
0901      * HPT371 chips physically have only one channel, the secondary one,
0902      * but the primary channel registers do exist!  Go figure...
0903      * So,  we manually disable the non-existing channel here
0904      * (if the BIOS hasn't done this already).
0905      */
0906     if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
0907         u8 mcr1;
0908 
0909         pci_read_config_byte(dev, 0x50, &mcr1);
0910         mcr1 &= ~0x04;
0911         pci_write_config_byte(dev, 0x50, mcr1);
0912     }
0913 
0914     /*
0915      * default to pci clock. make sure MA15/16 are set to output
0916      * to prevent drives having problems with 40-pin cables. Needed
0917      * for some drives such as IBM-DTLA which will not enter ready
0918      * state on reset when PDIAG is a input.
0919      */
0920 
0921     pci_write_config_byte(dev, 0x5b, 0x23);
0922 
0923     /*
0924      * HighPoint does this for HPT372A.
0925      * NOTE: This register is only writeable via I/O space.
0926      */
0927     if (chip_table == &hpt372a)
0928         outb(0x0e, iobase + 0x9c);
0929 
0930     freq = hpt37x_pci_clock(dev, chip_table->base);
0931     if (!freq)
0932         return -ENODEV;
0933 
0934     /*
0935      *  Turn the frequency check into a band and then find a timing
0936      *  table to match it.
0937      */
0938 
0939     clock_slot = hpt37x_clock_slot(freq);
0940     if (chip_table->clocks[clock_slot] == NULL || prefer_dpll) {
0941         /*
0942          *  We need to try PLL mode instead
0943          *
0944          *  For non UDMA133 capable devices we should
0945          *  use a 50MHz DPLL by choice
0946          */
0947         unsigned int f_low, f_high;
0948         int dpll, adjust;
0949 
0950         /* Compute DPLL */
0951         dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
0952 
0953         f_low = (MHz[clock_slot] * 48) / MHz[dpll];
0954         f_high = f_low + 2;
0955         if (clock_slot > 1)
0956             f_high += 2;
0957 
0958         /* Select the DPLL clock. */
0959         pci_write_config_byte(dev, 0x5b, 0x21);
0960         pci_write_config_dword(dev, 0x5C,
0961                        (f_high << 16) | f_low | 0x100);
0962 
0963         for (adjust = 0; adjust < 8; adjust++) {
0964             if (hpt37x_calibrate_dpll(dev))
0965                 break;
0966             /*
0967              * See if it'll settle at a fractionally
0968              * different clock
0969              */
0970             if (adjust & 1)
0971                 f_low -= adjust >> 1;
0972             else
0973                 f_high += adjust >> 1;
0974             pci_write_config_dword(dev, 0x5C,
0975                            (f_high << 16) | f_low | 0x100);
0976         }
0977         if (adjust == 8) {
0978             dev_err(&dev->dev, "DPLL did not stabilize!\n");
0979             return -ENODEV;
0980         }
0981         if (dpll == 3)
0982             private_data = (void *)hpt37x_timings_66;
0983         else
0984             private_data = (void *)hpt37x_timings_50;
0985 
0986         dev_info(&dev->dev, "bus clock %dMHz, using %dMHz DPLL\n",
0987             MHz[clock_slot], MHz[dpll]);
0988     } else {
0989         private_data = (void *)chip_table->clocks[clock_slot];
0990         /*
0991          *  Perform a final fixup. Note that we will have used the
0992          *  DPLL on the HPT372 which means we don't have to worry
0993          *  about lack of UDMA133 support on lower clocks
0994          */
0995 
0996         if (clock_slot < 2 && ppi[0] == &info_hpt370)
0997             ppi[0] = &info_hpt370_33;
0998         if (clock_slot < 2 && ppi[0] == &info_hpt370a)
0999             ppi[0] = &info_hpt370a_33;
1000 
1001         dev_info(&dev->dev, "%s using %dMHz bus clock\n",
1002             chip_table->name, MHz[clock_slot]);
1003     }
1004 
1005     /* Now kick off ATA set up */
1006     return ata_pci_bmdma_init_one(dev, ppi, &hpt37x_sht, private_data, 0);
1007 }
1008 
1009 static const struct pci_device_id hpt37x[] = {
1010     { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
1011     { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
1012     { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
1013     { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), },
1014     { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
1015 
1016     { },
1017 };
1018 
1019 static struct pci_driver hpt37x_pci_driver = {
1020     .name       = DRV_NAME,
1021     .id_table   = hpt37x,
1022     .probe      = hpt37x_init_one,
1023     .remove     = ata_pci_remove_one
1024 };
1025 
1026 module_pci_driver(hpt37x_pci_driver);
1027 
1028 MODULE_AUTHOR("Alan Cox");
1029 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT37x/30x");
1030 MODULE_LICENSE("GPL");
1031 MODULE_DEVICE_TABLE(pci, hpt37x);
1032 MODULE_VERSION(DRV_VERSION);
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