drivers/ata/pata_hpt366.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
0004  *
0005  * This driver is heavily based upon:
0006  *
0007  * linux/drivers/ide/pci/hpt366.c       Version 0.36    April 25, 2003
0008  *
0009  * Copyright (C) 1999-2003      Andre Hedrick <andre@linux-ide.org>
0010  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
0011  * Portions Copyright (C) 2003      Red Hat Inc
0012  *
0013  *
0014  * TODO
0015  *  Look into engine reset on timeout errors. Should not be required.
0016  */
0017 #include <linux/kernel.h>
0018 #include <linux/module.h>
0019 #include <linux/pci.h>
0020 #include <linux/blkdev.h>
0021 #include <linux/delay.h>
0022 #include <scsi/scsi_host.h>
0023 #include <linux/libata.h>
0024
0025 #define DRV_NAME    "pata_hpt366"
0026 #define DRV_VERSION "0.6.13"
0027
0028 struct hpt_clock {
0029     u8  xfer_mode;
0030     u32 timing;
0031 };
0032
0033 /* key for bus clock timings
0034  * bit
0035  * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
0036  *        cycles = value + 1
0037  * 4:7    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
0038  *        cycles = value + 1
0039  * 8:11   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
0040  *        register access.
0041  * 12:15  cmd_low_time. Active time of DIOW_/DIOR_ during task file
0042  *        register access.
0043  * 16:18  udma_cycle_time. Clock cycles for UDMA xfer?
0044  * 19:21  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
0045  * 22:24  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
0046  *        register access.
0047  * 28     UDMA enable.
0048  * 29     DMA  enable.
0049  * 30     PIO_MST enable. If set, the chip is in bus master mode during
0050  *        PIO xfer.
0051  * 31     FIFO enable.
0052  */
0053
0054 static const struct hpt_clock hpt366_40[] = {
0055     {   XFER_UDMA_4,    0x900fd943  },
0056     {   XFER_UDMA_3,    0x900ad943  },
0057     {   XFER_UDMA_2,    0x900bd943  },
0058     {   XFER_UDMA_1,    0x9008d943  },
0059     {   XFER_UDMA_0,    0x9008d943  },
0060
0061     {   XFER_MW_DMA_2,  0xa008d943  },
0062     {   XFER_MW_DMA_1,  0xa010d955  },
0063     {   XFER_MW_DMA_0,  0xa010d9fc  },
0064
0065     {   XFER_PIO_4, 0xc008d963  },
0066     {   XFER_PIO_3, 0xc010d974  },
0067     {   XFER_PIO_2, 0xc010d997  },
0068     {   XFER_PIO_1, 0xc010d9c7  },
0069     {   XFER_PIO_0, 0xc018d9d9  },
0070     {   0,      0x0120d9d9  }
0071 };
0072
0073 static const struct hpt_clock hpt366_33[] = {
0074     {   XFER_UDMA_4,    0x90c9a731  },
0075     {   XFER_UDMA_3,    0x90cfa731  },
0076     {   XFER_UDMA_2,    0x90caa731  },
0077     {   XFER_UDMA_1,    0x90cba731  },
0078     {   XFER_UDMA_0,    0x90c8a731  },
0079
0080     {   XFER_MW_DMA_2,  0xa0c8a731  },
0081     {   XFER_MW_DMA_1,  0xa0c8a732  },  /* 0xa0c8a733 */
0082     {   XFER_MW_DMA_0,  0xa0c8a797  },
0083
0084     {   XFER_PIO_4, 0xc0c8a731  },
0085     {   XFER_PIO_3, 0xc0c8a742  },
0086     {   XFER_PIO_2, 0xc0d0a753  },
0087     {   XFER_PIO_1, 0xc0d0a7a3  },  /* 0xc0d0a793 */
0088     {   XFER_PIO_0, 0xc0d0a7aa  },  /* 0xc0d0a7a7 */
0089     {   0,      0x0120a7a7  }
0090 };
0091
0092 static const struct hpt_clock hpt366_25[] = {
0093     {   XFER_UDMA_4,    0x90c98521  },
0094     {   XFER_UDMA_3,    0x90cf8521  },
0095     {   XFER_UDMA_2,    0x90cf8521  },
0096     {   XFER_UDMA_1,    0x90cb8521  },
0097     {   XFER_UDMA_0,    0x90cb8521  },
0098
0099     {   XFER_MW_DMA_2,  0xa0ca8521  },
0100     {   XFER_MW_DMA_1,  0xa0ca8532  },
0101     {   XFER_MW_DMA_0,  0xa0ca8575  },
0102
0103     {   XFER_PIO_4, 0xc0ca8521  },
0104     {   XFER_PIO_3, 0xc0ca8532  },
0105     {   XFER_PIO_2, 0xc0ca8542  },
0106     {   XFER_PIO_1, 0xc0d08572  },
0107     {   XFER_PIO_0, 0xc0d08585  },
0108     {   0,      0x01208585  }
0109 };
0110
0111 /**
0112  *  hpt36x_find_mode    -   find the hpt36x timing
0113  *  @ap: ATA port
0114  *  @speed: transfer mode
0115  *
0116  *  Return the 32bit register programming information for this channel
0117  *  that matches the speed provided.
0118  */
0119
0120 static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
0121 {
0122     struct hpt_clock *clocks = ap->host->private_data;
0123
0124     while (clocks->xfer_mode) {
0125         if (clocks->xfer_mode == speed)
0126             return clocks->timing;
0127         clocks++;
0128     }
0129     BUG();
0130     return 0xffffffffU; /* silence compiler warning */
0131 }
0132
0133 static const char * const bad_ata33[] = {
0134     "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
0135     "Maxtor 90845U3", "Maxtor 90650U2",
0136     "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
0137     "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
0138     "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
0139     "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
0140     "Maxtor 90510D4",
0141     "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
0142     "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
0143     "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
0144     "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
0145     "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
0146     NULL
0147 };
0148
0149 static const char * const bad_ata66_4[] = {
0150     "IBM-DTLA-307075",
0151     "IBM-DTLA-307060",
0152     "IBM-DTLA-307045",
0153     "IBM-DTLA-307030",
0154     "IBM-DTLA-307020",
0155     "IBM-DTLA-307015",
0156     "IBM-DTLA-305040",
0157     "IBM-DTLA-305030",
0158     "IBM-DTLA-305020",
0159     "IC35L010AVER07-0",
0160     "IC35L020AVER07-0",
0161     "IC35L030AVER07-0",
0162     "IC35L040AVER07-0",
0163     "IC35L060AVER07-0",
0164     "WDC AC310200R",
0165     NULL
0166 };
0167
0168 static const char * const bad_ata66_3[] = {
0169     "WDC AC310200R",
0170     NULL
0171 };
0172
0173 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
0174                    const char * const list[])
0175 {
0176     unsigned char model_num[ATA_ID_PROD_LEN + 1];
0177     int i;
0178
0179     ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
0180
0181     i = match_string(list, -1, model_num);
0182     if (i >= 0) {
0183         ata_dev_warn(dev, "%s is not supported for %s\n", modestr, list[i]);
0184         return 1;
0185     }
0186     return 0;
0187 }
0188
0189 /**
0190  *  hpt366_filter   -   mode selection filter
0191  *  @adev: ATA device
0192  *  @mask: Current mask to manipulate and pass back
0193  *
0194  *  Block UDMA on devices that cause trouble with this controller.
0195  */
0196
0197 static unsigned int hpt366_filter(struct ata_device *adev, unsigned int mask)
0198 {
0199     if (adev->class == ATA_DEV_ATA) {
0200         if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
0201             mask &= ~ATA_MASK_UDMA;
0202         if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
0203             mask &= ~(0xF8 << ATA_SHIFT_UDMA);
0204         if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
0205             mask &= ~(0xF0 << ATA_SHIFT_UDMA);
0206     } else if (adev->class == ATA_DEV_ATAPI)
0207         mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
0208
0209     return mask;
0210 }
0211
0212 static int hpt36x_cable_detect(struct ata_port *ap)
0213 {
0214     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0215     u8 ata66;
0216
0217     /*
0218      * Each channel of pata_hpt366 occupies separate PCI function
0219      * as the primary channel and bit1 indicates the cable type.
0220      */
0221     pci_read_config_byte(pdev, 0x5A, &ata66);
0222     if (ata66 & 2)
0223         return ATA_CBL_PATA40;
0224     return ATA_CBL_PATA80;
0225 }
0226
0227 static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
0228                 u8 mode)
0229 {
0230     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0231     u32 addr = 0x40 + 4 * adev->devno;
0232     u32 mask, reg, t;
0233
0234     /* determine timing mask and find matching clock entry */
0235     if (mode < XFER_MW_DMA_0)
0236         mask = 0xc1f8ffff;
0237     else if (mode < XFER_UDMA_0)
0238         mask = 0x303800ff;
0239     else
0240         mask = 0x30070000;
0241
0242     t = hpt36x_find_mode(ap, mode);
0243
0244     /*
0245      * Combine new mode bits with old config bits and disable
0246      * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
0247      * problems handling I/O errors later.
0248      */
0249     pci_read_config_dword(pdev, addr, &reg);
0250     reg = ((reg & ~mask) | (t & mask)) & ~0xc0000000;
0251     pci_write_config_dword(pdev, addr, reg);
0252 }
0253
0254 /**
0255  *  hpt366_set_piomode      -   PIO setup
0256  *  @ap: ATA interface
0257  *  @adev: device on the interface
0258  *
0259  *  Perform PIO mode setup.
0260  */
0261
0262 static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
0263 {
0264     hpt366_set_mode(ap, adev, adev->pio_mode);
0265 }
0266
0267 /**
0268  *  hpt366_set_dmamode      -   DMA timing setup
0269  *  @ap: ATA interface
0270  *  @adev: Device being configured
0271  *
0272  *  Set up the channel for MWDMA or UDMA modes. Much the same as with
0273  *  PIO, load the mode number and then set MWDMA or UDMA flag.
0274  */
0275
0276 static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0277 {
0278     hpt366_set_mode(ap, adev, adev->dma_mode);
0279 }
0280
0281 /**
0282  *  hpt366_prereset     -   reset the hpt36x bus
0283  *  @link: ATA link to reset
0284  *  @deadline: deadline jiffies for the operation
0285  *
0286  *  Perform the initial reset handling for the 36x series controllers.
0287  *  Reset the hardware and state machine,
0288  */
0289
0290 static int hpt366_prereset(struct ata_link *link, unsigned long deadline)
0291 {
0292     struct ata_port *ap = link->ap;
0293     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0294     /*
0295      * HPT36x chips have one channel per function and have
0296      * both channel enable bits located differently and visible
0297      * to both functions -- really stupid design decision... :-(
0298      * Bit 4 is for the primary channel, bit 5 for the secondary.
0299      */
0300     static const struct pci_bits hpt366_enable_bits = {
0301         0x50, 1, 0x30, 0x30
0302     };
0303     u8 mcr2;
0304
0305     if (!pci_test_config_bits(pdev, &hpt366_enable_bits))
0306         return -ENOENT;
0307
0308     pci_read_config_byte(pdev, 0x51, &mcr2);
0309     if (mcr2 & 0x80)
0310         pci_write_config_byte(pdev, 0x51, mcr2 & ~0x80);
0311
0312     return ata_sff_prereset(link, deadline);
0313 }
0314
0315 static struct scsi_host_template hpt36x_sht = {
0316     ATA_BMDMA_SHT(DRV_NAME),
0317 };
0318
0319 /*
0320  *  Configuration for HPT366/68
0321  */
0322
0323 static struct ata_port_operations hpt366_port_ops = {
0324     .inherits   = &ata_bmdma_port_ops,
0325     .prereset   = hpt366_prereset,
0326     .cable_detect   = hpt36x_cable_detect,
0327     .mode_filter    = hpt366_filter,
0328     .set_piomode    = hpt366_set_piomode,
0329     .set_dmamode    = hpt366_set_dmamode,
0330 };
0331
0332 /**
0333  *  hpt36x_init_chipset -   common chip setup
0334  *  @dev: PCI device
0335  *
0336  *  Perform the chip setup work that must be done at both init and
0337  *  resume time
0338  */
0339
0340 static void hpt36x_init_chipset(struct pci_dev *dev)
0341 {
0342     u8 mcr1;
0343
0344     pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
0345     pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
0346     pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
0347     pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
0348
0349     /*
0350      * Now we'll have to force both channels enabled if at least one
0351      * of them has been enabled by BIOS...
0352      */
0353     pci_read_config_byte(dev, 0x50, &mcr1);
0354     if (mcr1 & 0x30)
0355         pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
0356 }
0357
0358 /**
0359  *  hpt36x_init_one     -   Initialise an HPT366/368
0360  *  @dev: PCI device
0361  *  @id: Entry in match table
0362  *
0363  *  Initialise an HPT36x device. There are some interesting complications
0364  *  here. Firstly the chip may report 366 and be one of several variants.
0365  *  Secondly all the timings depend on the clock for the chip which we must
0366  *  detect and look up
0367  *
0368  *  This is the known chip mappings. It may be missing a couple of later
0369  *  releases.
0370  *
0371  *  Chip version        PCI     Rev Notes
0372  *  HPT366          4 (HPT366)  0   UDMA66
0373  *  HPT366          4 (HPT366)  1   UDMA66
0374  *  HPT368          4 (HPT366)  2   UDMA66
0375  *  HPT37x/30x      4 (HPT366)  3+  Other driver
0376  *
0377  */
0378
0379 static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
0380 {
0381     static const struct ata_port_info info_hpt366 = {
0382         .flags = ATA_FLAG_SLAVE_POSS,
0383         .pio_mask = ATA_PIO4,
0384         .mwdma_mask = ATA_MWDMA2,
0385         .udma_mask = ATA_UDMA4,
0386         .port_ops = &hpt366_port_ops
0387     };
0388     const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
0389
0390     const void *hpriv = NULL;
0391     u32 reg1;
0392     int rc;
0393
0394     rc = pcim_enable_device(dev);
0395     if (rc)
0396         return rc;
0397
0398     /* May be a later chip in disguise. Check */
0399     /* Newer chips are not in the HPT36x driver. Ignore them */
0400     if (dev->revision > 2)
0401         return -ENODEV;
0402
0403     hpt36x_init_chipset(dev);
0404
0405     pci_read_config_dword(dev, 0x40,  &reg1);
0406
0407     /* PCI clocking determines the ATA timing values to use */
0408     /* info_hpt366 is safe against re-entry so we can scribble on it */
0409     switch ((reg1 & 0xf00) >> 8) {
0410     case 9:
0411         hpriv = &hpt366_40;
0412         break;
0413     case 5:
0414         hpriv = &hpt366_25;
0415         break;
0416     default:
0417         hpriv = &hpt366_33;
0418         break;
0419     }
0420     /* Now kick off ATA set up */
0421     return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, (void *)hpriv, 0);
0422 }
0423
0424 #ifdef CONFIG_PM_SLEEP
0425 static int hpt36x_reinit_one(struct pci_dev *dev)
0426 {
0427     struct ata_host *host = pci_get_drvdata(dev);
0428     int rc;
0429
0430     rc = ata_pci_device_do_resume(dev);
0431     if (rc)
0432         return rc;
0433     hpt36x_init_chipset(dev);
0434     ata_host_resume(host);
0435     return 0;
0436 }
0437 #endif
0438
0439 static const struct pci_device_id hpt36x[] = {
0440     { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
0441     { },
0442 };
0443
0444 static struct pci_driver hpt36x_pci_driver = {
0445     .name       = DRV_NAME,
0446     .id_table   = hpt36x,
0447     .probe      = hpt36x_init_one,
0448     .remove     = ata_pci_remove_one,
0449 #ifdef CONFIG_PM_SLEEP
0450     .suspend    = ata_pci_device_suspend,
0451     .resume     = hpt36x_reinit_one,
0452 #endif
0453 };
0454
0455 module_pci_driver(hpt36x_pci_driver);
0456
0457 MODULE_AUTHOR("Alan Cox");
0458 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
0459 MODULE_LICENSE("GPL");
0460 MODULE_DEVICE_TABLE(pci, hpt36x);
0461 MODULE_VERSION(DRV_VERSION);