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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Faraday Technology FTIDE010 driver
0004  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
0005  *
0006  * Includes portions of the SL2312/SL3516/Gemini PATA driver
0007  * Copyright (C) 2003 StorLine, Inc <jason@storlink.com.tw>
0008  * Copyright (C) 2009 Janos Laube <janos.dev@gmail.com>
0009  * Copyright (C) 2010 Frederic Pecourt <opengemini@free.fr>
0010  * Copyright (C) 2011 Tobias Waldvogel <tobias.waldvogel@gmail.com>
0011  */
0012 
0013 #include <linux/platform_device.h>
0014 #include <linux/module.h>
0015 #include <linux/libata.h>
0016 #include <linux/bitops.h>
0017 #include <linux/of_address.h>
0018 #include <linux/of_device.h>
0019 #include <linux/clk.h>
0020 #include "sata_gemini.h"
0021 
0022 #define DRV_NAME "pata_ftide010"
0023 
0024 /**
0025  * struct ftide010 - state container for the Faraday FTIDE010
0026  * @dev: pointer back to the device representing this controller
0027  * @base: remapped I/O space address
0028  * @pclk: peripheral clock for the IDE block
0029  * @host: pointer to the ATA host for this device
0030  * @master_cbl: master cable type
0031  * @slave_cbl: slave cable type
0032  * @sg: Gemini SATA bridge pointer, if running on the Gemini
0033  * @master_to_sata0: Gemini SATA bridge: the ATA master is connected
0034  * to the SATA0 bridge
0035  * @slave_to_sata0: Gemini SATA bridge: the ATA slave is connected
0036  * to the SATA0 bridge
0037  * @master_to_sata1: Gemini SATA bridge: the ATA master is connected
0038  * to the SATA1 bridge
0039  * @slave_to_sata1: Gemini SATA bridge: the ATA slave is connected
0040  * to the SATA1 bridge
0041  */
0042 struct ftide010 {
0043     struct device *dev;
0044     void __iomem *base;
0045     struct clk *pclk;
0046     struct ata_host *host;
0047     unsigned int master_cbl;
0048     unsigned int slave_cbl;
0049     /* Gemini-specific properties */
0050     struct sata_gemini *sg;
0051     bool master_to_sata0;
0052     bool slave_to_sata0;
0053     bool master_to_sata1;
0054     bool slave_to_sata1;
0055 };
0056 
0057 #define FTIDE010_DMA_REG    0x00
0058 #define FTIDE010_DMA_STATUS 0x02
0059 #define FTIDE010_IDE_BMDTPR 0x04
0060 #define FTIDE010_IDE_DEVICE_ID  0x08
0061 #define FTIDE010_PIO_TIMING 0x10
0062 #define FTIDE010_MWDMA_TIMING   0x11
0063 #define FTIDE010_UDMA_TIMING0   0x12 /* Master */
0064 #define FTIDE010_UDMA_TIMING1   0x13 /* Slave */
0065 #define FTIDE010_CLK_MOD    0x14
0066 /* These registers are mapped directly to the IDE registers */
0067 #define FTIDE010_CMD_DATA   0x20
0068 #define FTIDE010_ERROR_FEATURES 0x21
0069 #define FTIDE010_NSECT      0x22
0070 #define FTIDE010_LBAL       0x23
0071 #define FTIDE010_LBAM       0x24
0072 #define FTIDE010_LBAH       0x25
0073 #define FTIDE010_DEVICE     0x26
0074 #define FTIDE010_STATUS_COMMAND 0x27
0075 #define FTIDE010_ALTSTAT_CTRL   0x36
0076 
0077 /* Set this bit for UDMA mode 5 and 6 */
0078 #define FTIDE010_UDMA_TIMING_MODE_56    BIT(7)
0079 
0080 /* 0 = 50 MHz, 1 = 66 MHz */
0081 #define FTIDE010_CLK_MOD_DEV0_CLK_SEL   BIT(0)
0082 #define FTIDE010_CLK_MOD_DEV1_CLK_SEL   BIT(1)
0083 /* Enable UDMA on a device */
0084 #define FTIDE010_CLK_MOD_DEV0_UDMA_EN   BIT(4)
0085 #define FTIDE010_CLK_MOD_DEV1_UDMA_EN   BIT(5)
0086 
0087 static struct scsi_host_template pata_ftide010_sht = {
0088     ATA_BMDMA_SHT(DRV_NAME),
0089 };
0090 
0091 /*
0092  * Bus timings
0093  *
0094  * The unit of the below required timings is two clock periods of the ATA
0095  * reference clock which is 30 nanoseconds per unit at 66MHz and 20
0096  * nanoseconds per unit at 50 MHz. The PIO timings assume 33MHz speed for
0097  * PIO.
0098  *
0099  * pio_active_time: array of 5 elements for T2 timing for Mode 0,
0100  * 1, 2, 3 and 4. Range 0..15.
0101  * pio_recovery_time: array of 5 elements for T2l timing for Mode 0,
0102  * 1, 2, 3 and 4. Range 0..15.
0103  * mdma_50_active_time: array of 4 elements for Td timing for multi
0104  * word DMA, Mode 0, 1, and 2 at 50 MHz. Range 0..15.
0105  * mdma_50_recovery_time: array of 4 elements for Tk timing for
0106  * multi word DMA, Mode 0, 1 and 2 at 50 MHz. Range 0..15.
0107  * mdma_66_active_time: array of 4 elements for Td timing for multi
0108  * word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
0109  * mdma_66_recovery_time: array of 4 elements for Tk timing for
0110  * multi word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
0111  * udma_50_setup_time: array of 4 elements for Tvds timing for ultra
0112  * DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz. Range 0..7.
0113  * udma_50_hold_time: array of 4 elements for Tdvh timing for
0114  * multi word DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz, Range 0..7.
0115  * udma_66_setup_time: array of 4 elements for Tvds timing for multi
0116  * word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 66 MHz. Range 0..7.
0117  * udma_66_hold_time: array of 4 elements for Tdvh timing for
0118  * multi word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 66 MHz. Range 0..7.
0119  */
0120 static const u8 pio_active_time[5] = {10, 10, 10, 3, 3};
0121 static const u8 pio_recovery_time[5] = {10, 3, 1, 3, 1};
0122 static const u8 mwdma_50_active_time[3] = {6, 2, 2};
0123 static const u8 mwdma_50_recovery_time[3] = {6, 2, 1};
0124 static const u8 mwdma_66_active_time[3] = {8, 3, 3};
0125 static const u8 mwdma_66_recovery_time[3] = {8, 2, 1};
0126 static const u8 udma_50_setup_time[6] = {3, 3, 2, 2, 1, 1};
0127 static const u8 udma_50_hold_time[6] = {3, 1, 1, 1, 1, 1};
0128 static const u8 udma_66_setup_time[7] = {4, 4, 3, 2, };
0129 static const u8 udma_66_hold_time[7] = {};
0130 
0131 /*
0132  * We set 66 MHz for all MWDMA modes
0133  */
0134 static const bool set_mdma_66_mhz[] = { true, true, true, true };
0135 
0136 /*
0137  * We set 66 MHz for UDMA modes 3, 4 and 6 and no others
0138  */
0139 static const bool set_udma_66_mhz[] = { false, false, false, true, true, false, true };
0140 
0141 static void ftide010_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0142 {
0143     struct ftide010 *ftide = ap->host->private_data;
0144     u8 speed = adev->dma_mode;
0145     u8 devno = adev->devno & 1;
0146     u8 udma_en_mask;
0147     u8 f66m_en_mask;
0148     u8 clkreg;
0149     u8 timreg;
0150     u8 i;
0151 
0152     /* Target device 0 (master) or 1 (slave) */
0153     if (!devno) {
0154         udma_en_mask = FTIDE010_CLK_MOD_DEV0_UDMA_EN;
0155         f66m_en_mask = FTIDE010_CLK_MOD_DEV0_CLK_SEL;
0156     } else {
0157         udma_en_mask = FTIDE010_CLK_MOD_DEV1_UDMA_EN;
0158         f66m_en_mask = FTIDE010_CLK_MOD_DEV1_CLK_SEL;
0159     }
0160 
0161     clkreg = readb(ftide->base + FTIDE010_CLK_MOD);
0162     clkreg &= ~udma_en_mask;
0163     clkreg &= ~f66m_en_mask;
0164 
0165     if (speed & XFER_UDMA_0) {
0166         i = speed & ~XFER_UDMA_0;
0167         dev_dbg(ftide->dev, "set UDMA mode %02x, index %d\n",
0168             speed, i);
0169 
0170         clkreg |= udma_en_mask;
0171         if (set_udma_66_mhz[i]) {
0172             clkreg |= f66m_en_mask;
0173             timreg = udma_66_setup_time[i] << 4 |
0174                 udma_66_hold_time[i];
0175         } else {
0176             timreg = udma_50_setup_time[i] << 4 |
0177                 udma_50_hold_time[i];
0178         }
0179 
0180         /* A special bit needs to be set for modes 5 and 6 */
0181         if (i >= 5)
0182             timreg |= FTIDE010_UDMA_TIMING_MODE_56;
0183 
0184         dev_dbg(ftide->dev, "UDMA write clkreg = %02x, timreg = %02x\n",
0185             clkreg, timreg);
0186 
0187         writeb(clkreg, ftide->base + FTIDE010_CLK_MOD);
0188         writeb(timreg, ftide->base + FTIDE010_UDMA_TIMING0 + devno);
0189     } else {
0190         i = speed & ~XFER_MW_DMA_0;
0191         dev_dbg(ftide->dev, "set MWDMA mode %02x, index %d\n",
0192             speed, i);
0193 
0194         if (set_mdma_66_mhz[i]) {
0195             clkreg |= f66m_en_mask;
0196             timreg = mwdma_66_active_time[i] << 4 |
0197                 mwdma_66_recovery_time[i];
0198         } else {
0199             timreg = mwdma_50_active_time[i] << 4 |
0200                 mwdma_50_recovery_time[i];
0201         }
0202         dev_dbg(ftide->dev,
0203             "MWDMA write clkreg = %02x, timreg = %02x\n",
0204             clkreg, timreg);
0205         /* This will affect all devices */
0206         writeb(clkreg, ftide->base + FTIDE010_CLK_MOD);
0207         writeb(timreg, ftide->base + FTIDE010_MWDMA_TIMING);
0208     }
0209 
0210     /*
0211      * Store the current device (master or slave) in ap->private_data
0212      * so that .qc_issue() can detect if this changes and reprogram
0213      * the DMA settings.
0214      */
0215     ap->private_data = adev;
0216 
0217     return;
0218 }
0219 
0220 static void ftide010_set_piomode(struct ata_port *ap, struct ata_device *adev)
0221 {
0222     struct ftide010 *ftide = ap->host->private_data;
0223     u8 pio = adev->pio_mode - XFER_PIO_0;
0224 
0225     dev_dbg(ftide->dev, "set PIO mode %02x, index %d\n",
0226         adev->pio_mode, pio);
0227     writeb(pio_active_time[pio] << 4 | pio_recovery_time[pio],
0228            ftide->base + FTIDE010_PIO_TIMING);
0229 }
0230 
0231 /*
0232  * We implement our own qc_issue() callback since we may need to set up
0233  * the timings differently for master and slave transfers: the CLK_MOD_REG
0234  * and MWDMA_TIMING_REG is shared between master and slave, so reprogramming
0235  * this may be necessary.
0236  */
0237 static unsigned int ftide010_qc_issue(struct ata_queued_cmd *qc)
0238 {
0239     struct ata_port *ap = qc->ap;
0240     struct ata_device *adev = qc->dev;
0241 
0242     /*
0243      * If the device changed, i.e. slave->master, master->slave,
0244      * then set up the DMA mode again so we are sure the timings
0245      * are correct.
0246      */
0247     if (adev != ap->private_data && ata_dma_enabled(adev))
0248         ftide010_set_dmamode(ap, adev);
0249 
0250     return ata_bmdma_qc_issue(qc);
0251 }
0252 
0253 static struct ata_port_operations pata_ftide010_port_ops = {
0254     .inherits   = &ata_bmdma_port_ops,
0255     .set_dmamode    = ftide010_set_dmamode,
0256     .set_piomode    = ftide010_set_piomode,
0257     .qc_issue   = ftide010_qc_issue,
0258 };
0259 
0260 static struct ata_port_info ftide010_port_info = {
0261     .flags      = ATA_FLAG_SLAVE_POSS,
0262     .mwdma_mask = ATA_MWDMA2,
0263     .udma_mask  = ATA_UDMA6,
0264     .pio_mask   = ATA_PIO4,
0265     .port_ops   = &pata_ftide010_port_ops,
0266 };
0267 
0268 #if IS_ENABLED(CONFIG_SATA_GEMINI)
0269 
0270 static int pata_ftide010_gemini_port_start(struct ata_port *ap)
0271 {
0272     struct ftide010 *ftide = ap->host->private_data;
0273     struct device *dev = ftide->dev;
0274     struct sata_gemini *sg = ftide->sg;
0275     int bridges = 0;
0276     int ret;
0277 
0278     ret = ata_bmdma_port_start(ap);
0279     if (ret)
0280         return ret;
0281 
0282     if (ftide->master_to_sata0) {
0283         dev_info(dev, "SATA0 (master) start\n");
0284         ret = gemini_sata_start_bridge(sg, 0);
0285         if (!ret)
0286             bridges++;
0287     }
0288     if (ftide->master_to_sata1) {
0289         dev_info(dev, "SATA1 (master) start\n");
0290         ret = gemini_sata_start_bridge(sg, 1);
0291         if (!ret)
0292             bridges++;
0293     }
0294     /* Avoid double-starting */
0295     if (ftide->slave_to_sata0 && !ftide->master_to_sata0) {
0296         dev_info(dev, "SATA0 (slave) start\n");
0297         ret = gemini_sata_start_bridge(sg, 0);
0298         if (!ret)
0299             bridges++;
0300     }
0301     /* Avoid double-starting */
0302     if (ftide->slave_to_sata1 && !ftide->master_to_sata1) {
0303         dev_info(dev, "SATA1 (slave) start\n");
0304         ret = gemini_sata_start_bridge(sg, 1);
0305         if (!ret)
0306             bridges++;
0307     }
0308 
0309     dev_info(dev, "brought %d bridges online\n", bridges);
0310     return (bridges > 0) ? 0 : -EINVAL; // -ENODEV;
0311 }
0312 
0313 static void pata_ftide010_gemini_port_stop(struct ata_port *ap)
0314 {
0315     struct ftide010 *ftide = ap->host->private_data;
0316     struct device *dev = ftide->dev;
0317     struct sata_gemini *sg = ftide->sg;
0318 
0319     if (ftide->master_to_sata0) {
0320         dev_info(dev, "SATA0 (master) stop\n");
0321         gemini_sata_stop_bridge(sg, 0);
0322     }
0323     if (ftide->master_to_sata1) {
0324         dev_info(dev, "SATA1 (master) stop\n");
0325         gemini_sata_stop_bridge(sg, 1);
0326     }
0327     /* Avoid double-stopping */
0328     if (ftide->slave_to_sata0 && !ftide->master_to_sata0) {
0329         dev_info(dev, "SATA0 (slave) stop\n");
0330         gemini_sata_stop_bridge(sg, 0);
0331     }
0332     /* Avoid double-stopping */
0333     if (ftide->slave_to_sata1 && !ftide->master_to_sata1) {
0334         dev_info(dev, "SATA1 (slave) stop\n");
0335         gemini_sata_stop_bridge(sg, 1);
0336     }
0337 }
0338 
0339 static int pata_ftide010_gemini_cable_detect(struct ata_port *ap)
0340 {
0341     struct ftide010 *ftide = ap->host->private_data;
0342 
0343     /*
0344      * Return the master cable, I have no clue how to return a different
0345      * cable for the slave than for the master.
0346      */
0347     return ftide->master_cbl;
0348 }
0349 
0350 static int pata_ftide010_gemini_init(struct ftide010 *ftide,
0351                      struct ata_port_info *pi,
0352                      bool is_ata1)
0353 {
0354     struct device *dev = ftide->dev;
0355     struct sata_gemini *sg;
0356     enum gemini_muxmode muxmode;
0357 
0358     /* Look up SATA bridge */
0359     sg = gemini_sata_bridge_get();
0360     if (IS_ERR(sg))
0361         return PTR_ERR(sg);
0362     ftide->sg = sg;
0363 
0364     muxmode = gemini_sata_get_muxmode(sg);
0365 
0366     /* Special ops */
0367     pata_ftide010_port_ops.port_start =
0368         pata_ftide010_gemini_port_start;
0369     pata_ftide010_port_ops.port_stop =
0370         pata_ftide010_gemini_port_stop;
0371     pata_ftide010_port_ops.cable_detect =
0372         pata_ftide010_gemini_cable_detect;
0373 
0374     /* Flag port as SATA-capable */
0375     if (gemini_sata_bridge_enabled(sg, is_ata1))
0376         pi->flags |= ATA_FLAG_SATA;
0377 
0378     /* This device has broken DMA, only PIO works */
0379     if (of_machine_is_compatible("itian,sq201")) {
0380         pi->mwdma_mask = 0;
0381         pi->udma_mask = 0;
0382     }
0383 
0384     /*
0385      * We assume that a simple 40-wire cable is used in the PATA mode.
0386      * if you're adding a system using the PATA interface, make sure
0387      * the right cable is set up here, it might be necessary to use
0388      * special hardware detection or encode the cable type in the device
0389      * tree with special properties.
0390      */
0391     if (!is_ata1) {
0392         switch (muxmode) {
0393         case GEMINI_MUXMODE_0:
0394             ftide->master_cbl = ATA_CBL_SATA;
0395             ftide->slave_cbl = ATA_CBL_PATA40;
0396             ftide->master_to_sata0 = true;
0397             break;
0398         case GEMINI_MUXMODE_1:
0399             ftide->master_cbl = ATA_CBL_SATA;
0400             ftide->slave_cbl = ATA_CBL_NONE;
0401             ftide->master_to_sata0 = true;
0402             break;
0403         case GEMINI_MUXMODE_2:
0404             ftide->master_cbl = ATA_CBL_PATA40;
0405             ftide->slave_cbl = ATA_CBL_PATA40;
0406             break;
0407         case GEMINI_MUXMODE_3:
0408             ftide->master_cbl = ATA_CBL_SATA;
0409             ftide->slave_cbl = ATA_CBL_SATA;
0410             ftide->master_to_sata0 = true;
0411             ftide->slave_to_sata1 = true;
0412             break;
0413         }
0414     } else {
0415         switch (muxmode) {
0416         case GEMINI_MUXMODE_0:
0417             ftide->master_cbl = ATA_CBL_SATA;
0418             ftide->slave_cbl = ATA_CBL_NONE;
0419             ftide->master_to_sata1 = true;
0420             break;
0421         case GEMINI_MUXMODE_1:
0422             ftide->master_cbl = ATA_CBL_SATA;
0423             ftide->slave_cbl = ATA_CBL_PATA40;
0424             ftide->master_to_sata1 = true;
0425             break;
0426         case GEMINI_MUXMODE_2:
0427             ftide->master_cbl = ATA_CBL_SATA;
0428             ftide->slave_cbl = ATA_CBL_SATA;
0429             ftide->slave_to_sata0 = true;
0430             ftide->master_to_sata1 = true;
0431             break;
0432         case GEMINI_MUXMODE_3:
0433             ftide->master_cbl = ATA_CBL_PATA40;
0434             ftide->slave_cbl = ATA_CBL_PATA40;
0435             break;
0436         }
0437     }
0438     dev_info(dev, "set up Gemini PATA%d\n", is_ata1);
0439 
0440     return 0;
0441 }
0442 #else
0443 static int pata_ftide010_gemini_init(struct ftide010 *ftide,
0444                      struct ata_port_info *pi,
0445                      bool is_ata1)
0446 {
0447     return -ENOTSUPP;
0448 }
0449 #endif
0450 
0451 
0452 static int pata_ftide010_probe(struct platform_device *pdev)
0453 {
0454     struct device *dev = &pdev->dev;
0455     struct device_node *np = dev->of_node;
0456     struct ata_port_info pi = ftide010_port_info;
0457     const struct ata_port_info *ppi[] = { &pi, NULL };
0458     struct ftide010 *ftide;
0459     struct resource *res;
0460     int irq;
0461     int ret;
0462     int i;
0463 
0464     ftide = devm_kzalloc(dev, sizeof(*ftide), GFP_KERNEL);
0465     if (!ftide)
0466         return -ENOMEM;
0467     ftide->dev = dev;
0468 
0469     irq = platform_get_irq(pdev, 0);
0470     if (irq < 0)
0471         return irq;
0472 
0473     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0474     if (!res)
0475         return -ENODEV;
0476 
0477     ftide->base = devm_ioremap_resource(dev, res);
0478     if (IS_ERR(ftide->base))
0479         return PTR_ERR(ftide->base);
0480 
0481     ftide->pclk = devm_clk_get(dev, "PCLK");
0482     if (!IS_ERR(ftide->pclk)) {
0483         ret = clk_prepare_enable(ftide->pclk);
0484         if (ret) {
0485             dev_err(dev, "failed to enable PCLK\n");
0486             return ret;
0487         }
0488     }
0489 
0490     /* Some special Cortina Gemini init, if needed */
0491     if (of_device_is_compatible(np, "cortina,gemini-pata")) {
0492         /*
0493          * We need to know which instance is probing (the
0494          * Gemini has two instances of FTIDE010) and we do
0495          * this simply by looking at the physical base
0496          * address, which is 0x63400000 for ATA1, else we
0497          * are ATA0. This will also set up the cable types.
0498          */
0499         ret = pata_ftide010_gemini_init(ftide,
0500                 &pi,
0501                 (res->start == 0x63400000));
0502         if (ret)
0503             goto err_dis_clk;
0504     } else {
0505         /* Else assume we are connected using PATA40 */
0506         ftide->master_cbl = ATA_CBL_PATA40;
0507         ftide->slave_cbl = ATA_CBL_PATA40;
0508     }
0509 
0510     ftide->host = ata_host_alloc_pinfo(dev, ppi, 1);
0511     if (!ftide->host) {
0512         ret = -ENOMEM;
0513         goto err_dis_clk;
0514     }
0515     ftide->host->private_data = ftide;
0516 
0517     for (i = 0; i < ftide->host->n_ports; i++) {
0518         struct ata_port *ap = ftide->host->ports[i];
0519         struct ata_ioports *ioaddr = &ap->ioaddr;
0520 
0521         ioaddr->bmdma_addr = ftide->base + FTIDE010_DMA_REG;
0522         ioaddr->cmd_addr = ftide->base + FTIDE010_CMD_DATA;
0523         ioaddr->ctl_addr = ftide->base + FTIDE010_ALTSTAT_CTRL;
0524         ioaddr->altstatus_addr = ftide->base + FTIDE010_ALTSTAT_CTRL;
0525         ata_sff_std_ports(ioaddr);
0526     }
0527 
0528     dev_info(dev, "device ID %08x, irq %d, reg %pR\n",
0529          readl(ftide->base + FTIDE010_IDE_DEVICE_ID), irq, res);
0530 
0531     ret = ata_host_activate(ftide->host, irq, ata_bmdma_interrupt,
0532                 0, &pata_ftide010_sht);
0533     if (ret)
0534         goto err_dis_clk;
0535 
0536     return 0;
0537 
0538 err_dis_clk:
0539     clk_disable_unprepare(ftide->pclk);
0540 
0541     return ret;
0542 }
0543 
0544 static int pata_ftide010_remove(struct platform_device *pdev)
0545 {
0546     struct ata_host *host = platform_get_drvdata(pdev);
0547     struct ftide010 *ftide = host->private_data;
0548 
0549     ata_host_detach(ftide->host);
0550     clk_disable_unprepare(ftide->pclk);
0551 
0552     return 0;
0553 }
0554 
0555 static const struct of_device_id pata_ftide010_of_match[] = {
0556     { .compatible = "faraday,ftide010", },
0557     { /* sentinel */ }
0558 };
0559 
0560 static struct platform_driver pata_ftide010_driver = {
0561     .driver = {
0562         .name = DRV_NAME,
0563         .of_match_table = of_match_ptr(pata_ftide010_of_match),
0564     },
0565     .probe = pata_ftide010_probe,
0566     .remove = pata_ftide010_remove,
0567 };
0568 module_platform_driver(pata_ftide010_driver);
0569 
0570 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
0571 MODULE_LICENSE("GPL");
0572 MODULE_ALIAS("platform:" DRV_NAME);
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