drivers/ata/pata_efar.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *    pata_efar.c - EFAR PIIX clone controller driver
0004  *
0005  *  (C) 2005 Red Hat
0006  *  (C) 2009-2010 Bartlomiej Zolnierkiewicz
0007  *
0008  *    Some parts based on ata_piix.c by Jeff Garzik and others.
0009  *
0010  *    The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later
0011  *    Intel ICH controllers the EFAR widened the UDMA mode register bits
0012  *    and doesn't require the funky clock selection.
0013  */
0014
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/pci.h>
0018 #include <linux/blkdev.h>
0019 #include <linux/delay.h>
0020 #include <linux/device.h>
0021 #include <scsi/scsi_host.h>
0022 #include <linux/libata.h>
0023 #include <linux/ata.h>
0024
0025 #define DRV_NAME    "pata_efar"
0026 #define DRV_VERSION "0.4.5"
0027
0028 /**
0029  *  efar_pre_reset  -   Enable bits
0030  *  @link: ATA link
0031  *  @deadline: deadline jiffies for the operation
0032  *
0033  *  Perform cable detection for the EFAR ATA interface. This is
0034  *  different to the PIIX arrangement
0035  */
0036
0037 static int efar_pre_reset(struct ata_link *link, unsigned long deadline)
0038 {
0039     static const struct pci_bits efar_enable_bits[] = {
0040         { 0x41U, 1U, 0x80UL, 0x80UL },  /* port 0 */
0041         { 0x43U, 1U, 0x80UL, 0x80UL },  /* port 1 */
0042     };
0043     struct ata_port *ap = link->ap;
0044     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0045
0046     if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no]))
0047         return -ENOENT;
0048
0049     return ata_sff_prereset(link, deadline);
0050 }
0051
0052 /**
0053  *  efar_cable_detect   -   check for 40/80 pin
0054  *  @ap: Port
0055  *
0056  *  Perform cable detection for the EFAR ATA interface. This is
0057  *  different to the PIIX arrangement
0058  */
0059
0060 static int efar_cable_detect(struct ata_port *ap)
0061 {
0062     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0063     u8 tmp;
0064
0065     pci_read_config_byte(pdev, 0x47, &tmp);
0066     if (tmp & (2 >> ap->port_no))
0067         return ATA_CBL_PATA40;
0068     return ATA_CBL_PATA80;
0069 }
0070
0071 static DEFINE_SPINLOCK(efar_lock);
0072
0073 /**
0074  *  efar_set_piomode - Initialize host controller PATA PIO timings
0075  *  @ap: Port whose timings we are configuring
0076  *  @adev: Device to program
0077  *
0078  *  Set PIO mode for device, in host controller PCI config space.
0079  *
0080  *  LOCKING:
0081  *  None (inherited from caller).
0082  */
0083
0084 static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev)
0085 {
0086     unsigned int pio    = adev->pio_mode - XFER_PIO_0;
0087     struct pci_dev *dev = to_pci_dev(ap->host->dev);
0088     unsigned int master_port = ap->port_no ? 0x42 : 0x40;
0089     unsigned long flags;
0090     u16 master_data;
0091     u8 udma_enable;
0092     int control = 0;
0093
0094     /*
0095      *  See Intel Document 298600-004 for the timing programing rules
0096      *  for PIIX/ICH. The EFAR is a clone so very similar
0097      */
0098
0099     static const     /* ISP  RTC */
0100     u8 timings[][2] = { { 0, 0 },
0101                 { 0, 0 },
0102                 { 1, 0 },
0103                 { 2, 1 },
0104                 { 2, 3 }, };
0105
0106     if (pio > 1)
0107         control |= 1;   /* TIME */
0108     if (ata_pio_need_iordy(adev))   /* PIO 3/4 require IORDY */
0109         control |= 2;   /* IE */
0110     /* Intel specifies that the prefetch/posting is for disk only */
0111     if (adev->class == ATA_DEV_ATA)
0112         control |= 4;   /* PPE */
0113
0114     spin_lock_irqsave(&efar_lock, flags);
0115
0116     pci_read_config_word(dev, master_port, &master_data);
0117
0118     /* Set PPE, IE, and TIME as appropriate */
0119     if (adev->devno == 0) {
0120         master_data &= 0xCCF0;
0121         master_data |= control;
0122         master_data |= (timings[pio][0] << 12) |
0123             (timings[pio][1] << 8);
0124     } else {
0125         int shift = 4 * ap->port_no;
0126         u8 slave_data;
0127
0128         master_data &= 0xFF0F;
0129         master_data |= (control << 4);
0130
0131         /* Slave timing in separate register */
0132         pci_read_config_byte(dev, 0x44, &slave_data);
0133         slave_data &= ap->port_no ? 0x0F : 0xF0;
0134         slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift;
0135         pci_write_config_byte(dev, 0x44, slave_data);
0136     }
0137
0138     master_data |= 0x4000;  /* Ensure SITRE is set */
0139     pci_write_config_word(dev, master_port, master_data);
0140
0141     pci_read_config_byte(dev, 0x48, &udma_enable);
0142     udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
0143     pci_write_config_byte(dev, 0x48, udma_enable);
0144     spin_unlock_irqrestore(&efar_lock, flags);
0145 }
0146
0147 /**
0148  *  efar_set_dmamode - Initialize host controller PATA DMA timings
0149  *  @ap: Port whose timings we are configuring
0150  *  @adev: Device to program
0151  *
0152  *  Set UDMA/MWDMA mode for device, in host controller PCI config space.
0153  *
0154  *  LOCKING:
0155  *  None (inherited from caller).
0156  */
0157
0158 static void efar_set_dmamode (struct ata_port *ap, struct ata_device *adev)
0159 {
0160     struct pci_dev *dev = to_pci_dev(ap->host->dev);
0161     u8 master_port      = ap->port_no ? 0x42 : 0x40;
0162     u16 master_data;
0163     u8 speed        = adev->dma_mode;
0164     int devid       = adev->devno + 2 * ap->port_no;
0165     unsigned long flags;
0166     u8 udma_enable;
0167
0168     static const     /* ISP  RTC */
0169     u8 timings[][2] = { { 0, 0 },
0170                 { 0, 0 },
0171                 { 1, 0 },
0172                 { 2, 1 },
0173                 { 2, 3 }, };
0174
0175     spin_lock_irqsave(&efar_lock, flags);
0176
0177     pci_read_config_word(dev, master_port, &master_data);
0178     pci_read_config_byte(dev, 0x48, &udma_enable);
0179
0180     if (speed >= XFER_UDMA_0) {
0181         unsigned int udma   = adev->dma_mode - XFER_UDMA_0;
0182         u16 udma_timing;
0183
0184         udma_enable |= (1 << devid);
0185
0186         /* Load the UDMA mode number */
0187         pci_read_config_word(dev, 0x4A, &udma_timing);
0188         udma_timing &= ~(7 << (4 * devid));
0189         udma_timing |= udma << (4 * devid);
0190         pci_write_config_word(dev, 0x4A, udma_timing);
0191     } else {
0192         /*
0193          * MWDMA is driven by the PIO timings. We must also enable
0194          * IORDY unconditionally along with TIME1. PPE has already
0195          * been set when the PIO timing was set.
0196          */
0197         unsigned int mwdma  = adev->dma_mode - XFER_MW_DMA_0;
0198         unsigned int control;
0199         u8 slave_data;
0200         const unsigned int needed_pio[3] = {
0201             XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
0202         };
0203         int pio = needed_pio[mwdma] - XFER_PIO_0;
0204
0205         control = 3;    /* IORDY|TIME1 */
0206
0207         /* If the drive MWDMA is faster than it can do PIO then
0208            we must force PIO into PIO0 */
0209
0210         if (adev->pio_mode < needed_pio[mwdma])
0211             /* Enable DMA timing only */
0212             control |= 8;   /* PIO cycles in PIO0 */
0213
0214         if (adev->devno) {  /* Slave */
0215             master_data &= 0xFF4F;  /* Mask out IORDY|TIME1|DMAONLY */
0216             master_data |= control << 4;
0217             pci_read_config_byte(dev, 0x44, &slave_data);
0218             slave_data &= ap->port_no ? 0x0F : 0xF0;
0219             /* Load the matching timing */
0220             slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
0221             pci_write_config_byte(dev, 0x44, slave_data);
0222         } else {    /* Master */
0223             master_data &= 0xCCF4;  /* Mask out IORDY|TIME1|DMAONLY
0224                            and master timing bits */
0225             master_data |= control;
0226             master_data |=
0227                 (timings[pio][0] << 12) |
0228                 (timings[pio][1] << 8);
0229         }
0230         udma_enable &= ~(1 << devid);
0231         pci_write_config_word(dev, master_port, master_data);
0232     }
0233     pci_write_config_byte(dev, 0x48, udma_enable);
0234     spin_unlock_irqrestore(&efar_lock, flags);
0235 }
0236
0237 static struct scsi_host_template efar_sht = {
0238     ATA_BMDMA_SHT(DRV_NAME),
0239 };
0240
0241 static struct ata_port_operations efar_ops = {
0242     .inherits       = &ata_bmdma_port_ops,
0243     .cable_detect       = efar_cable_detect,
0244     .set_piomode        = efar_set_piomode,
0245     .set_dmamode        = efar_set_dmamode,
0246     .prereset       = efar_pre_reset,
0247 };
0248
0249
0250 /**
0251  *  efar_init_one - Register EFAR ATA PCI device with kernel services
0252  *  @pdev: PCI device to register
0253  *  @ent: Entry in efar_pci_tbl matching with @pdev
0254  *
0255  *  Called from kernel PCI layer.
0256  *
0257  *  LOCKING:
0258  *  Inherited from PCI layer (may sleep).
0259  *
0260  *  RETURNS:
0261  *  Zero on success, or -ERRNO value.
0262  */
0263
0264 static int efar_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
0265 {
0266     static const struct ata_port_info info = {
0267         .flags      = ATA_FLAG_SLAVE_POSS,
0268         .pio_mask   = ATA_PIO4,
0269         .mwdma_mask = ATA_MWDMA12_ONLY,
0270         .udma_mask  = ATA_UDMA4,
0271         .port_ops   = &efar_ops,
0272     };
0273     const struct ata_port_info *ppi[] = { &info, &info };
0274
0275     ata_print_version_once(&pdev->dev, DRV_VERSION);
0276
0277     return ata_pci_bmdma_init_one(pdev, ppi, &efar_sht, NULL,
0278                       ATA_HOST_PARALLEL_SCAN);
0279 }
0280
0281 static const struct pci_device_id efar_pci_tbl[] = {
0282     { PCI_VDEVICE(EFAR, 0x9130), },
0283
0284     { } /* terminate list */
0285 };
0286
0287 static struct pci_driver efar_pci_driver = {
0288     .name           = DRV_NAME,
0289     .id_table       = efar_pci_tbl,
0290     .probe          = efar_init_one,
0291     .remove         = ata_pci_remove_one,
0292 #ifdef CONFIG_PM_SLEEP
0293     .suspend        = ata_pci_device_suspend,
0294     .resume         = ata_pci_device_resume,
0295 #endif
0296 };
0297
0298 module_pci_driver(efar_pci_driver);
0299
0300 MODULE_AUTHOR("Alan Cox");
0301 MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones");
0302 MODULE_LICENSE("GPL");
0303 MODULE_DEVICE_TABLE(pci, efar_pci_tbl);
0304 MODULE_VERSION(DRV_VERSION);