drivers/ata/pata_cs5536.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * pata_cs5536.c    - CS5536 PATA for new ATA layer
0004  *            (C) 2007 Martin K. Petersen <mkp@mkp.net>
0005  *            (C) 2011 Bartlomiej Zolnierkiewicz
0006  *
0007  * Documentation:
0008  *  Available from AMD web site.
0009  *
0010  * The IDE timing registers for the CS5536 live in the Geode Machine
0011  * Specific Register file and not PCI config space.  Most BIOSes
0012  * virtualize the PCI registers so the chip looks like a standard IDE
0013  * controller.  Unfortunately not all implementations get this right.
0014  * In particular some have problems with unaligned accesses to the
0015  * virtualized PCI registers.  This driver always does full dword
0016  * writes to work around the issue.  Also, in case of a bad BIOS this
0017  * driver can be loaded with the "msr=1" parameter which forces using
0018  * the Machine Specific Registers to configure the device.
0019  */
0020
0021 #include <linux/kernel.h>
0022 #include <linux/module.h>
0023 #include <linux/pci.h>
0024 #include <linux/blkdev.h>
0025 #include <linux/delay.h>
0026 #include <linux/libata.h>
0027 #include <scsi/scsi_host.h>
0028 #include <linux/dmi.h>
0029
0030 #ifdef CONFIG_X86_32
0031 #include <asm/msr.h>
0032 static int use_msr;
0033 module_param_named(msr, use_msr, int, 0644);
0034 MODULE_PARM_DESC(msr, "Force using MSR to configure IDE function (Default: 0)");
0035 #else
0036 #undef rdmsr    /* avoid accidental MSR usage on, e.g. x86-64 */
0037 #undef wrmsr
0038 #define rdmsr(x, y, z) do { } while (0)
0039 #define wrmsr(x, y, z) do { } while (0)
0040 #define use_msr 0
0041 #endif
0042
0043 #define DRV_NAME    "pata_cs5536"
0044 #define DRV_VERSION "0.0.8"
0045
0046 enum {
0047     MSR_IDE_CFG     = 0x51300010,
0048     PCI_IDE_CFG     = 0x40,
0049
0050     CFG         = 0,
0051     DTC         = 2,
0052     CAST            = 3,
0053     ETC         = 4,
0054
0055     IDE_CFG_CHANEN      = (1 << 1),
0056     IDE_CFG_CABLE       = (1 << 17) | (1 << 16),
0057
0058     IDE_D0_SHIFT        = 24,
0059     IDE_D1_SHIFT        = 16,
0060     IDE_DRV_MASK        = 0xff,
0061
0062     IDE_CAST_D0_SHIFT   = 6,
0063     IDE_CAST_D1_SHIFT   = 4,
0064     IDE_CAST_DRV_MASK   = 0x3,
0065     IDE_CAST_CMD_MASK   = 0xff,
0066     IDE_CAST_CMD_SHIFT  = 24,
0067
0068     IDE_ETC_UDMA_MASK   = 0xc0,
0069 };
0070
0071 /* Some Bachmann OT200 devices have a non working UDMA support due a
0072  * missing resistor.
0073  */
0074 static const struct dmi_system_id udma_quirk_dmi_table[] = {
0075     {
0076         .ident = "Bachmann electronic OT200",
0077         .matches = {
0078             DMI_MATCH(DMI_SYS_VENDOR, "Bachmann electronic"),
0079             DMI_MATCH(DMI_PRODUCT_NAME, "OT200"),
0080             DMI_MATCH(DMI_PRODUCT_VERSION, "1")
0081         },
0082     },
0083     { }
0084 };
0085
0086 static int cs5536_read(struct pci_dev *pdev, int reg, u32 *val)
0087 {
0088     if (unlikely(use_msr)) {
0089         u32 dummy __maybe_unused;
0090
0091         rdmsr(MSR_IDE_CFG + reg, *val, dummy);
0092         return 0;
0093     }
0094
0095     return pci_read_config_dword(pdev, PCI_IDE_CFG + reg * 4, val);
0096 }
0097
0098 static int cs5536_write(struct pci_dev *pdev, int reg, int val)
0099 {
0100     if (unlikely(use_msr)) {
0101         wrmsr(MSR_IDE_CFG + reg, val, 0);
0102         return 0;
0103     }
0104
0105     return pci_write_config_dword(pdev, PCI_IDE_CFG + reg * 4, val);
0106 }
0107
0108 static void cs5536_program_dtc(struct ata_device *adev, u8 tim)
0109 {
0110     struct pci_dev *pdev = to_pci_dev(adev->link->ap->host->dev);
0111     int dshift = adev->devno ? IDE_D1_SHIFT : IDE_D0_SHIFT;
0112     u32 dtc;
0113
0114     cs5536_read(pdev, DTC, &dtc);
0115     dtc &= ~(IDE_DRV_MASK << dshift);
0116     dtc |= tim << dshift;
0117     cs5536_write(pdev, DTC, dtc);
0118 }
0119
0120 /**
0121  *  cs5536_cable_detect -   detect cable type
0122  *  @ap: Port to detect on
0123  *
0124  *  Perform cable detection for ATA66 capable cable.
0125  *
0126  *  Returns a cable type.
0127  */
0128
0129 static int cs5536_cable_detect(struct ata_port *ap)
0130 {
0131     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0132     u32 cfg;
0133
0134     cs5536_read(pdev, CFG, &cfg);
0135
0136     if (cfg & IDE_CFG_CABLE)
0137         return ATA_CBL_PATA80;
0138     else
0139         return ATA_CBL_PATA40;
0140 }
0141
0142 /**
0143  *  cs5536_set_piomode      -   PIO setup
0144  *  @ap: ATA interface
0145  *  @adev: device on the interface
0146  */
0147
0148 static void cs5536_set_piomode(struct ata_port *ap, struct ata_device *adev)
0149 {
0150     static const u8 drv_timings[5] = {
0151         0x98, 0x55, 0x32, 0x21, 0x20,
0152     };
0153
0154     static const u8 addr_timings[5] = {
0155         0x2, 0x1, 0x0, 0x0, 0x0,
0156     };
0157
0158     static const u8 cmd_timings[5] = {
0159         0x99, 0x92, 0x90, 0x22, 0x20,
0160     };
0161
0162     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0163     struct ata_device *pair = ata_dev_pair(adev);
0164     int mode = adev->pio_mode - XFER_PIO_0;
0165     int cmdmode = mode;
0166     int cshift = adev->devno ? IDE_CAST_D1_SHIFT : IDE_CAST_D0_SHIFT;
0167     u32 cast;
0168
0169     if (pair)
0170         cmdmode = min(mode, pair->pio_mode - XFER_PIO_0);
0171
0172     cs5536_program_dtc(adev, drv_timings[mode]);
0173
0174     cs5536_read(pdev, CAST, &cast);
0175
0176     cast &= ~(IDE_CAST_DRV_MASK << cshift);
0177     cast |= addr_timings[mode] << cshift;
0178
0179     cast &= ~(IDE_CAST_CMD_MASK << IDE_CAST_CMD_SHIFT);
0180     cast |= cmd_timings[cmdmode] << IDE_CAST_CMD_SHIFT;
0181
0182     cs5536_write(pdev, CAST, cast);
0183 }
0184
0185 /**
0186  *  cs5536_set_dmamode      -   DMA timing setup
0187  *  @ap: ATA interface
0188  *  @adev: Device being configured
0189  *
0190  */
0191
0192 static void cs5536_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0193 {
0194     static const u8 udma_timings[6] = {
0195         0xc2, 0xc1, 0xc0, 0xc4, 0xc5, 0xc6,
0196     };
0197
0198     static const u8 mwdma_timings[3] = {
0199         0x67, 0x21, 0x20,
0200     };
0201
0202     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0203     u32 etc;
0204     int mode = adev->dma_mode;
0205     int dshift = adev->devno ? IDE_D1_SHIFT : IDE_D0_SHIFT;
0206
0207     cs5536_read(pdev, ETC, &etc);
0208
0209     if (mode >= XFER_UDMA_0) {
0210         etc &= ~(IDE_DRV_MASK << dshift);
0211         etc |= udma_timings[mode - XFER_UDMA_0] << dshift;
0212     } else { /* MWDMA */
0213         etc &= ~(IDE_ETC_UDMA_MASK << dshift);
0214         cs5536_program_dtc(adev, mwdma_timings[mode - XFER_MW_DMA_0]);
0215     }
0216
0217     cs5536_write(pdev, ETC, etc);
0218 }
0219
0220 static struct scsi_host_template cs5536_sht = {
0221     ATA_BMDMA_SHT(DRV_NAME),
0222 };
0223
0224 static struct ata_port_operations cs5536_port_ops = {
0225     .inherits       = &ata_bmdma32_port_ops,
0226     .cable_detect       = cs5536_cable_detect,
0227     .set_piomode        = cs5536_set_piomode,
0228     .set_dmamode        = cs5536_set_dmamode,
0229 };
0230
0231 /**
0232  *  cs5536_init_one
0233  *  @dev: PCI device
0234  *  @id: Entry in match table
0235  *
0236  */
0237
0238 static int cs5536_init_one(struct pci_dev *dev, const struct pci_device_id *id)
0239 {
0240     static const struct ata_port_info info = {
0241         .flags = ATA_FLAG_SLAVE_POSS,
0242         .pio_mask = ATA_PIO4,
0243         .mwdma_mask = ATA_MWDMA2,
0244         .udma_mask = ATA_UDMA5,
0245         .port_ops = &cs5536_port_ops,
0246     };
0247
0248     static const struct ata_port_info no_udma_info = {
0249         .flags = ATA_FLAG_SLAVE_POSS,
0250         .pio_mask = ATA_PIO4,
0251         .port_ops = &cs5536_port_ops,
0252     };
0253
0254
0255     const struct ata_port_info *ppi[2];
0256     u32 cfg;
0257
0258     if (dmi_check_system(udma_quirk_dmi_table))
0259         ppi[0] = &no_udma_info;
0260     else
0261         ppi[0] = &info;
0262
0263     ppi[1] = &ata_dummy_port_info;
0264
0265     if (use_msr)
0266         dev_err(&dev->dev, DRV_NAME ": Using MSR regs instead of PCI\n");
0267
0268     cs5536_read(dev, CFG, &cfg);
0269
0270     if ((cfg & IDE_CFG_CHANEN) == 0) {
0271         dev_err(&dev->dev, DRV_NAME ": disabled by BIOS\n");
0272         return -ENODEV;
0273     }
0274
0275     return ata_pci_bmdma_init_one(dev, ppi, &cs5536_sht, NULL, 0);
0276 }
0277
0278 static const struct pci_device_id cs5536[] = {
0279     { PCI_VDEVICE(AMD,  PCI_DEVICE_ID_AMD_CS5536_IDE), },
0280     { PCI_VDEVICE(AMD,  PCI_DEVICE_ID_AMD_CS5536_DEV_IDE), },
0281     { },
0282 };
0283
0284 static struct pci_driver cs5536_pci_driver = {
0285     .name       = DRV_NAME,
0286     .id_table   = cs5536,
0287     .probe      = cs5536_init_one,
0288     .remove     = ata_pci_remove_one,
0289 #ifdef CONFIG_PM_SLEEP
0290     .suspend    = ata_pci_device_suspend,
0291     .resume     = ata_pci_device_resume,
0292 #endif
0293 };
0294
0295 module_pci_driver(cs5536_pci_driver);
0296
0297 MODULE_AUTHOR("Martin K. Petersen");
0298 MODULE_DESCRIPTION("low-level driver for the CS5536 IDE controller");
0299 MODULE_LICENSE("GPL");
0300 MODULE_DEVICE_TABLE(pci, cs5536);
0301 MODULE_VERSION(DRV_VERSION);