drivers/ata/pata_cmd64x.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * pata_cmd64x.c    - CMD64x PATA for new ATA layer
0004  *            (C) 2005 Red Hat Inc
0005  *            Alan Cox <alan@lxorguk.ukuu.org.uk>
0006  *            (C) 2009-2010 Bartlomiej Zolnierkiewicz
0007  *            (C) 2012 MontaVista Software, LLC <source@mvista.com>
0008  *
0009  * Based upon
0010  * linux/drivers/ide/pci/cmd64x.c       Version 1.30    Sept 10, 2002
0011  *
0012  * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
0013  *           Note, this driver is not used at all on other systems because
0014  *           there the "BIOS" has done all of the following already.
0015  *           Due to massive hardware bugs, UltraDMA is only supported
0016  *           on the 646U2 and not on the 646U.
0017  *
0018  * Copyright (C) 1998       Eddie C. Dost  (ecd@skynet.be)
0019  * Copyright (C) 1998       David S. Miller (davem@redhat.com)
0020  *
0021  * Copyright (C) 1999-2002  Andre Hedrick <andre@linux-ide.org>
0022  *
0023  * TODO
0024  *  Testing work
0025  */
0026
0027 #include <linux/kernel.h>
0028 #include <linux/module.h>
0029 #include <linux/pci.h>
0030 #include <linux/blkdev.h>
0031 #include <linux/delay.h>
0032 #include <scsi/scsi_host.h>
0033 #include <linux/libata.h>
0034
0035 #define DRV_NAME "pata_cmd64x"
0036 #define DRV_VERSION "0.2.18"
0037
0038 /*
0039  * CMD64x specific registers definition.
0040  */
0041
0042 enum {
0043     CFR         = 0x50,
0044         CFR_INTR_CH0  = 0x04,
0045     CNTRL       = 0x51,
0046         CNTRL_CH0     = 0x04,
0047         CNTRL_CH1     = 0x08,
0048     CMDTIM      = 0x52,
0049     ARTTIM0     = 0x53,
0050     DRWTIM0     = 0x54,
0051     ARTTIM1     = 0x55,
0052     DRWTIM1     = 0x56,
0053     ARTTIM23    = 0x57,
0054         ARTTIM23_DIS_RA2  = 0x04,
0055         ARTTIM23_DIS_RA3  = 0x08,
0056         ARTTIM23_INTR_CH1 = 0x10,
0057     DRWTIM2     = 0x58,
0058     BRST        = 0x59,
0059     DRWTIM3     = 0x5b,
0060     BMIDECR0    = 0x70,
0061     MRDMODE     = 0x71,
0062         MRDMODE_INTR_CH0 = 0x04,
0063         MRDMODE_INTR_CH1 = 0x08,
0064     BMIDESR0    = 0x72,
0065     UDIDETCR0   = 0x73,
0066     DTPR0       = 0x74,
0067     BMIDECR1    = 0x78,
0068     BMIDECSR    = 0x79,
0069     UDIDETCR1   = 0x7B,
0070     DTPR1       = 0x7C
0071 };
0072
0073 static int cmd648_cable_detect(struct ata_port *ap)
0074 {
0075     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0076     u8 r;
0077
0078     /* Check cable detect bits */
0079     pci_read_config_byte(pdev, BMIDECSR, &r);
0080     if (r & (1 << ap->port_no))
0081         return ATA_CBL_PATA80;
0082     return ATA_CBL_PATA40;
0083 }
0084
0085 /**
0086  *  cmd64x_set_timing   -   set PIO and MWDMA timing
0087  *  @ap: ATA interface
0088  *  @adev: ATA device
0089  *  @mode: mode
0090  *
0091  *  Called to do the PIO and MWDMA mode setup.
0092  */
0093
0094 static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode)
0095 {
0096     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0097     struct ata_timing t;
0098     const unsigned long T = 1000000 / 33;
0099     const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
0100
0101     u8 reg;
0102
0103     /* Port layout is not logical so use a table */
0104     const u8 arttim_port[2][2] = {
0105         { ARTTIM0, ARTTIM1 },
0106         { ARTTIM23, ARTTIM23 }
0107     };
0108     const u8 drwtim_port[2][2] = {
0109         { DRWTIM0, DRWTIM1 },
0110         { DRWTIM2, DRWTIM3 }
0111     };
0112
0113     int arttim = arttim_port[ap->port_no][adev->devno];
0114     int drwtim = drwtim_port[ap->port_no][adev->devno];
0115
0116     /* ata_timing_compute is smart and will produce timings for MWDMA
0117        that don't violate the drives PIO capabilities. */
0118     if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
0119         ata_dev_err(adev, DRV_NAME ": mode computation failed.\n");
0120         return;
0121     }
0122     if (ap->port_no) {
0123         /* Slave has shared address setup */
0124         struct ata_device *pair = ata_dev_pair(adev);
0125
0126         if (pair) {
0127             struct ata_timing tp;
0128             ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
0129             ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
0130         }
0131     }
0132
0133     ata_dev_dbg(adev, DRV_NAME ": active %d recovery %d setup %d.\n",
0134         t.active, t.recover, t.setup);
0135     if (t.recover > 16) {
0136         t.active += t.recover - 16;
0137         t.recover = 16;
0138     }
0139     if (t.active > 16)
0140         t.active = 16;
0141
0142     /* Now convert the clocks into values we can actually stuff into
0143        the chip */
0144
0145     if (t.recover == 16)
0146         t.recover = 0;
0147     else if (t.recover > 1)
0148         t.recover--;
0149     else
0150         t.recover = 15;
0151
0152     if (t.setup > 4)
0153         t.setup = 0xC0;
0154     else
0155         t.setup = setup_data[t.setup];
0156
0157     t.active &= 0x0F;   /* 0 = 16 */
0158
0159     /* Load setup timing */
0160     pci_read_config_byte(pdev, arttim, &reg);
0161     reg &= 0x3F;
0162     reg |= t.setup;
0163     pci_write_config_byte(pdev, arttim, reg);
0164
0165     /* Load active/recovery */
0166     pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
0167 }
0168
0169 /**
0170  *  cmd64x_set_piomode  -   set initial PIO mode data
0171  *  @ap: ATA interface
0172  *  @adev: ATA device
0173  *
0174  *  Used when configuring the devices ot set the PIO timings. All the
0175  *  actual work is done by the PIO/MWDMA setting helper
0176  */
0177
0178 static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
0179 {
0180     cmd64x_set_timing(ap, adev, adev->pio_mode);
0181 }
0182
0183 /**
0184  *  cmd64x_set_dmamode  -   set initial DMA mode data
0185  *  @ap: ATA interface
0186  *  @adev: ATA device
0187  *
0188  *  Called to do the DMA mode setup.
0189  */
0190
0191 static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0192 {
0193     static const u8 udma_data[] = {
0194         0x30, 0x20, 0x10, 0x20, 0x10, 0x00
0195     };
0196
0197     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0198     u8 regU, regD;
0199
0200     int pciU = UDIDETCR0 + 8 * ap->port_no;
0201     int pciD = BMIDESR0 + 8 * ap->port_no;
0202     int shift = 2 * adev->devno;
0203
0204     pci_read_config_byte(pdev, pciD, &regD);
0205     pci_read_config_byte(pdev, pciU, &regU);
0206
0207     /* DMA bits off */
0208     regD &= ~(0x20 << adev->devno);
0209     /* DMA control bits */
0210     regU &= ~(0x30 << shift);
0211     /* DMA timing bits */
0212     regU &= ~(0x05 << adev->devno);
0213
0214     if (adev->dma_mode >= XFER_UDMA_0) {
0215         /* Merge the timing value */
0216         regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
0217         /* Merge the control bits */
0218         regU |= 1 << adev->devno; /* UDMA on */
0219         if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
0220             regU |= 4 << adev->devno;
0221     } else {
0222         regU &= ~ (1 << adev->devno);   /* UDMA off */
0223         cmd64x_set_timing(ap, adev, adev->dma_mode);
0224     }
0225
0226     regD |= 0x20 << adev->devno;
0227
0228     pci_write_config_byte(pdev, pciU, regU);
0229     pci_write_config_byte(pdev, pciD, regD);
0230 }
0231
0232 /**
0233  *  cmd64x_sff_irq_check    -   check IDE interrupt
0234  *  @ap: ATA interface
0235  *
0236  *  Check IDE interrupt in CFR/ARTTIM23 registers.
0237  */
0238
0239 static bool cmd64x_sff_irq_check(struct ata_port *ap)
0240 {
0241     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0242     int irq_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
0243     int irq_reg  = ap->port_no ? ARTTIM23 : CFR;
0244     u8 irq_stat;
0245
0246     /* NOTE: reading the register should clear the interrupt */
0247     pci_read_config_byte(pdev, irq_reg, &irq_stat);
0248
0249     return irq_stat & irq_mask;
0250 }
0251
0252 /**
0253  *  cmd64x_sff_irq_clear    -   clear IDE interrupt
0254  *  @ap: ATA interface
0255  *
0256  *  Clear IDE interrupt in CFR/ARTTIM23 and DMA status registers.
0257  */
0258
0259 static void cmd64x_sff_irq_clear(struct ata_port *ap)
0260 {
0261     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0262     int irq_reg = ap->port_no ? ARTTIM23 : CFR;
0263     u8 irq_stat;
0264
0265     ata_bmdma_irq_clear(ap);
0266
0267     /* Reading the register should be enough to clear the interrupt */
0268     pci_read_config_byte(pdev, irq_reg, &irq_stat);
0269 }
0270
0271 /**
0272  *  cmd648_sff_irq_check    -   check IDE interrupt
0273  *  @ap: ATA interface
0274  *
0275  *  Check IDE interrupt in MRDMODE register.
0276  */
0277
0278 static bool cmd648_sff_irq_check(struct ata_port *ap)
0279 {
0280     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0281     unsigned long base = pci_resource_start(pdev, 4);
0282     int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0;
0283     u8 mrdmode = inb(base + 1);
0284
0285     return mrdmode & irq_mask;
0286 }
0287
0288 /**
0289  *  cmd648_sff_irq_clear    -   clear IDE interrupt
0290  *  @ap: ATA interface
0291  *
0292  *  Clear IDE interrupt in MRDMODE and DMA status registers.
0293  */
0294
0295 static void cmd648_sff_irq_clear(struct ata_port *ap)
0296 {
0297     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0298     unsigned long base = pci_resource_start(pdev, 4);
0299     int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0;
0300     u8 mrdmode;
0301
0302     ata_bmdma_irq_clear(ap);
0303
0304     /* Clear this port's interrupt bit (leaving the other port alone) */
0305     mrdmode  = inb(base + 1);
0306     mrdmode &= ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1);
0307     outb(mrdmode | irq_mask, base + 1);
0308 }
0309
0310 /**
0311  *  cmd646r1_bmdma_stop -   DMA stop callback
0312  *  @qc: Command in progress
0313  *
0314  *  Stub for now while investigating the r1 quirk in the old driver.
0315  */
0316
0317 static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
0318 {
0319     ata_bmdma_stop(qc);
0320 }
0321
0322 static struct scsi_host_template cmd64x_sht = {
0323     ATA_BMDMA_SHT(DRV_NAME),
0324 };
0325
0326 static const struct ata_port_operations cmd64x_base_ops = {
0327     .inherits   = &ata_bmdma_port_ops,
0328     .set_piomode    = cmd64x_set_piomode,
0329     .set_dmamode    = cmd64x_set_dmamode,
0330 };
0331
0332 static struct ata_port_operations cmd64x_port_ops = {
0333     .inherits   = &cmd64x_base_ops,
0334     .sff_irq_check  = cmd64x_sff_irq_check,
0335     .sff_irq_clear  = cmd64x_sff_irq_clear,
0336     .cable_detect   = ata_cable_40wire,
0337 };
0338
0339 static struct ata_port_operations cmd646r1_port_ops = {
0340     .inherits   = &cmd64x_base_ops,
0341     .sff_irq_check  = cmd64x_sff_irq_check,
0342     .sff_irq_clear  = cmd64x_sff_irq_clear,
0343     .bmdma_stop = cmd646r1_bmdma_stop,
0344     .cable_detect   = ata_cable_40wire,
0345 };
0346
0347 static struct ata_port_operations cmd646r3_port_ops = {
0348     .inherits   = &cmd64x_base_ops,
0349     .sff_irq_check  = cmd648_sff_irq_check,
0350     .sff_irq_clear  = cmd648_sff_irq_clear,
0351     .cable_detect   = ata_cable_40wire,
0352 };
0353
0354 static struct ata_port_operations cmd648_port_ops = {
0355     .inherits   = &cmd64x_base_ops,
0356     .sff_irq_check  = cmd648_sff_irq_check,
0357     .sff_irq_clear  = cmd648_sff_irq_clear,
0358     .cable_detect   = cmd648_cable_detect,
0359 };
0360
0361 static void cmd64x_fixup(struct pci_dev *pdev)
0362 {
0363     u8 mrdmode;
0364
0365     pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
0366     pci_read_config_byte(pdev, MRDMODE, &mrdmode);
0367     mrdmode &= ~0x30;   /* IRQ set up */
0368     mrdmode |= 0x02;    /* Memory read line enable */
0369     pci_write_config_byte(pdev, MRDMODE, mrdmode);
0370
0371     /* PPC specific fixup copied from old driver */
0372 #ifdef CONFIG_PPC
0373     pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
0374 #endif
0375 }
0376
0377 static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
0378 {
0379     static const struct ata_port_info cmd_info[7] = {
0380         {   /* CMD 643 - no UDMA */
0381             .flags = ATA_FLAG_SLAVE_POSS,
0382             .pio_mask = ATA_PIO4,
0383             .mwdma_mask = ATA_MWDMA2,
0384             .port_ops = &cmd64x_port_ops
0385         },
0386         {   /* CMD 646 with broken UDMA */
0387             .flags = ATA_FLAG_SLAVE_POSS,
0388             .pio_mask = ATA_PIO4,
0389             .mwdma_mask = ATA_MWDMA2,
0390             .port_ops = &cmd64x_port_ops
0391         },
0392         {   /* CMD 646U with broken UDMA */
0393             .flags = ATA_FLAG_SLAVE_POSS,
0394             .pio_mask = ATA_PIO4,
0395             .mwdma_mask = ATA_MWDMA2,
0396             .port_ops = &cmd646r3_port_ops
0397         },
0398         {   /* CMD 646U2 with working UDMA */
0399             .flags = ATA_FLAG_SLAVE_POSS,
0400             .pio_mask = ATA_PIO4,
0401             .mwdma_mask = ATA_MWDMA2,
0402             .udma_mask = ATA_UDMA2,
0403             .port_ops = &cmd646r3_port_ops
0404         },
0405         {   /* CMD 646 rev 1  */
0406             .flags = ATA_FLAG_SLAVE_POSS,
0407             .pio_mask = ATA_PIO4,
0408             .mwdma_mask = ATA_MWDMA2,
0409             .port_ops = &cmd646r1_port_ops
0410         },
0411         {   /* CMD 648 */
0412             .flags = ATA_FLAG_SLAVE_POSS,
0413             .pio_mask = ATA_PIO4,
0414             .mwdma_mask = ATA_MWDMA2,
0415             .udma_mask = ATA_UDMA4,
0416             .port_ops = &cmd648_port_ops
0417         },
0418         {   /* CMD 649 */
0419             .flags = ATA_FLAG_SLAVE_POSS,
0420             .pio_mask = ATA_PIO4,
0421             .mwdma_mask = ATA_MWDMA2,
0422             .udma_mask = ATA_UDMA5,
0423             .port_ops = &cmd648_port_ops
0424         }
0425     };
0426     const struct ata_port_info *ppi[] = {
0427         &cmd_info[id->driver_data],
0428         &cmd_info[id->driver_data],
0429         NULL
0430     };
0431     u8 reg;
0432     int rc;
0433     struct pci_dev *bridge = pdev->bus->self;
0434     /* mobility split bridges don't report enabled ports correctly */
0435     int port_ok = !(bridge && bridge->vendor ==
0436             PCI_VENDOR_ID_MOBILITY_ELECTRONICS);
0437     /* all (with exceptions below) apart from 643 have CNTRL_CH0 bit */
0438     int cntrl_ch0_ok = (id->driver_data != 0);
0439
0440     rc = pcim_enable_device(pdev);
0441     if (rc)
0442         return rc;
0443
0444     if (id->driver_data == 0)   /* 643 */
0445         ata_pci_bmdma_clear_simplex(pdev);
0446
0447     if (pdev->device == PCI_DEVICE_ID_CMD_646)
0448         switch (pdev->revision) {
0449         /* UDMA works since rev 5 */
0450         default:
0451             ppi[0] = &cmd_info[3];
0452             ppi[1] = &cmd_info[3];
0453             break;
0454         /* Interrupts in MRDMODE since rev 3 */
0455         case 3:
0456         case 4:
0457             ppi[0] = &cmd_info[2];
0458             ppi[1] = &cmd_info[2];
0459             break;
0460         /* Rev 1 with other problems? */
0461         case 1:
0462             ppi[0] = &cmd_info[4];
0463             ppi[1] = &cmd_info[4];
0464             fallthrough;
0465         /* Early revs have no CNTRL_CH0 */
0466         case 2:
0467         case 0:
0468             cntrl_ch0_ok = 0;
0469             break;
0470         }
0471
0472     cmd64x_fixup(pdev);
0473
0474     /* check for enabled ports */
0475     pci_read_config_byte(pdev, CNTRL, &reg);
0476     if (!port_ok)
0477         dev_notice(&pdev->dev, "Mobility Bridge detected, ignoring CNTRL port enable/disable\n");
0478     if (port_ok && cntrl_ch0_ok && !(reg & CNTRL_CH0)) {
0479         dev_notice(&pdev->dev, "Primary port is disabled\n");
0480         ppi[0] = &ata_dummy_port_info;
0481
0482     }
0483     if (port_ok && !(reg & CNTRL_CH1)) {
0484         dev_notice(&pdev->dev, "Secondary port is disabled\n");
0485         ppi[1] = &ata_dummy_port_info;
0486     }
0487
0488     return ata_pci_bmdma_init_one(pdev, ppi, &cmd64x_sht, NULL, 0);
0489 }
0490
0491 #ifdef CONFIG_PM_SLEEP
0492 static int cmd64x_reinit_one(struct pci_dev *pdev)
0493 {
0494     struct ata_host *host = pci_get_drvdata(pdev);
0495     int rc;
0496
0497     rc = ata_pci_device_do_resume(pdev);
0498     if (rc)
0499         return rc;
0500
0501     cmd64x_fixup(pdev);
0502
0503     ata_host_resume(host);
0504     return 0;
0505 }
0506 #endif
0507
0508 static const struct pci_device_id cmd64x[] = {
0509     { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
0510     { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
0511     { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 5 },
0512     { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 6 },
0513
0514     { },
0515 };
0516
0517 static struct pci_driver cmd64x_pci_driver = {
0518     .name       = DRV_NAME,
0519     .id_table   = cmd64x,
0520     .probe      = cmd64x_init_one,
0521     .remove     = ata_pci_remove_one,
0522 #ifdef CONFIG_PM_SLEEP
0523     .suspend    = ata_pci_device_suspend,
0524     .resume     = cmd64x_reinit_one,
0525 #endif
0526 };
0527
0528 module_pci_driver(cmd64x_pci_driver);
0529
0530 MODULE_AUTHOR("Alan Cox");
0531 MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
0532 MODULE_LICENSE("GPL");
0533 MODULE_DEVICE_TABLE(pci, cmd64x);
0534 MODULE_VERSION(DRV_VERSION);