drivers/ata/pata_bk3710.c

0001 // SPDX-License-Identifier: GPL-2.0
0002
0003 /*
0004  * Palmchip BK3710 PATA controller driver
0005  *
0006  * Copyright (c) 2017 Samsung Electronics Co., Ltd.
0007  *      http://www.samsung.com
0008  *
0009  * Based on palm_bk3710.c:
0010  *
0011  * Copyright (C) 2006 Texas Instruments.
0012  * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
0013  */
0014
0015 #include <linux/ata.h>
0016 #include <linux/clk.h>
0017 #include <linux/delay.h>
0018 #include <linux/init.h>
0019 #include <linux/ioport.h>
0020 #include <linux/kernel.h>
0021 #include <linux/libata.h>
0022 #include <linux/module.h>
0023 #include <linux/platform_device.h>
0024 #include <linux/types.h>
0025
0026 #define DRV_NAME "pata_bk3710"
0027
0028 #define BK3710_TF_OFFSET    0x1F0
0029 #define BK3710_CTL_OFFSET   0x3F6
0030
0031 #define BK3710_BMISP        0x02
0032 #define BK3710_IDETIMP      0x40
0033 #define BK3710_UDMACTL      0x48
0034 #define BK3710_MISCCTL      0x50
0035 #define BK3710_REGSTB       0x54
0036 #define BK3710_REGRCVR      0x58
0037 #define BK3710_DATSTB       0x5C
0038 #define BK3710_DATRCVR      0x60
0039 #define BK3710_DMASTB       0x64
0040 #define BK3710_DMARCVR      0x68
0041 #define BK3710_UDMASTB      0x6C
0042 #define BK3710_UDMATRP      0x70
0043 #define BK3710_UDMAENV      0x74
0044 #define BK3710_IORDYTMP     0x78
0045
0046 static struct scsi_host_template pata_bk3710_sht = {
0047     ATA_BMDMA_SHT(DRV_NAME),
0048 };
0049
0050 static unsigned int ideclk_period; /* in nanoseconds */
0051
0052 struct pata_bk3710_udmatiming {
0053     unsigned int rptime;    /* tRP -- Ready to pause time (nsec) */
0054     unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */
0055                 /* tENV is always a minimum of 20 nsec */
0056 };
0057
0058 static const struct pata_bk3710_udmatiming pata_bk3710_udmatimings[6] = {
0059     { 160, 240 / 2 },   /* UDMA Mode 0 */
0060     { 125, 160 / 2 },   /* UDMA Mode 1 */
0061     { 100, 120 / 2 },   /* UDMA Mode 2 */
0062     { 100,  90 / 2 },   /* UDMA Mode 3 */
0063     { 100,  60 / 2 },   /* UDMA Mode 4 */
0064     {  85,  40 / 2 },   /* UDMA Mode 5 */
0065 };
0066
0067 static void pata_bk3710_setudmamode(void __iomem *base, unsigned int dev,
0068                     unsigned int mode)
0069 {
0070     u32 val32;
0071     u16 val16;
0072     u8 tenv, trp, t0;
0073
0074     /* DMA Data Setup */
0075     t0 = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].cycletime,
0076               ideclk_period) - 1;
0077     tenv = DIV_ROUND_UP(20, ideclk_period) - 1;
0078     trp = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].rptime,
0079                ideclk_period) - 1;
0080
0081     /* udmastb Ultra DMA Access Strobe Width */
0082     val32 = ioread32(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8));
0083     val32 |= t0 << (dev ? 8 : 0);
0084     iowrite32(val32, base + BK3710_UDMASTB);
0085
0086     /* udmatrp Ultra DMA Ready to Pause Time */
0087     val32 = ioread32(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8));
0088     val32 |= trp << (dev ? 8 : 0);
0089     iowrite32(val32, base + BK3710_UDMATRP);
0090
0091     /* udmaenv Ultra DMA envelop Time */
0092     val32 = ioread32(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8));
0093     val32 |= tenv << (dev ? 8 : 0);
0094     iowrite32(val32, base + BK3710_UDMAENV);
0095
0096     /* Enable UDMA for Device */
0097     val16 = ioread16(base + BK3710_UDMACTL) | (1 << dev);
0098     iowrite16(val16, base + BK3710_UDMACTL);
0099 }
0100
0101 static void pata_bk3710_setmwdmamode(void __iomem *base, unsigned int dev,
0102                      unsigned short min_cycle,
0103                      unsigned int mode)
0104 {
0105     const struct ata_timing *t;
0106     int cycletime;
0107     u32 val32;
0108     u16 val16;
0109     u8 td, tkw, t0;
0110
0111     t = ata_timing_find_mode(mode);
0112     cycletime = max_t(int, t->cycle, min_cycle);
0113
0114     /* DMA Data Setup */
0115     t0 = DIV_ROUND_UP(cycletime, ideclk_period);
0116     td = DIV_ROUND_UP(t->active, ideclk_period);
0117     tkw = t0 - td - 1;
0118     td--;
0119
0120     val32 = ioread32(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8));
0121     val32 |= td << (dev ? 8 : 0);
0122     iowrite32(val32, base + BK3710_DMASTB);
0123
0124     val32 = ioread32(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8));
0125     val32 |= tkw << (dev ? 8 : 0);
0126     iowrite32(val32, base + BK3710_DMARCVR);
0127
0128     /* Disable UDMA for Device */
0129     val16 = ioread16(base + BK3710_UDMACTL) & ~(1 << dev);
0130     iowrite16(val16, base + BK3710_UDMACTL);
0131 }
0132
0133 static void pata_bk3710_set_dmamode(struct ata_port *ap,
0134                     struct ata_device *adev)
0135 {
0136     void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr;
0137     int is_slave = adev->devno;
0138     const u8 xferspeed = adev->dma_mode;
0139
0140     if (xferspeed >= XFER_UDMA_0)
0141         pata_bk3710_setudmamode(base, is_slave,
0142                     xferspeed - XFER_UDMA_0);
0143     else
0144         pata_bk3710_setmwdmamode(base, is_slave,
0145                      adev->id[ATA_ID_EIDE_DMA_MIN],
0146                      xferspeed);
0147 }
0148
0149 static void pata_bk3710_setpiomode(void __iomem *base, struct ata_device *pair,
0150                    unsigned int dev, unsigned int cycletime,
0151                    unsigned int mode)
0152 {
0153     const struct ata_timing *t;
0154     u32 val32;
0155     u8 t2, t2i, t0;
0156
0157     t = ata_timing_find_mode(XFER_PIO_0 + mode);
0158
0159     /* PIO Data Setup */
0160     t0 = DIV_ROUND_UP(cycletime, ideclk_period);
0161     t2 = DIV_ROUND_UP(t->active, ideclk_period);
0162
0163     t2i = t0 - t2 - 1;
0164     t2--;
0165
0166     val32 = ioread32(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8));
0167     val32 |= t2 << (dev ? 8 : 0);
0168     iowrite32(val32, base + BK3710_DATSTB);
0169
0170     val32 = ioread32(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8));
0171     val32 |= t2i << (dev ? 8 : 0);
0172     iowrite32(val32, base + BK3710_DATRCVR);
0173
0174     /* FIXME: this is broken also in the old driver */
0175     if (pair) {
0176         u8 mode2 = pair->pio_mode - XFER_PIO_0;
0177
0178         if (mode2 < mode)
0179             mode = mode2;
0180     }
0181
0182     /* TASKFILE Setup */
0183     t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period);
0184     t2 = DIV_ROUND_UP(t->act8b, ideclk_period);
0185
0186     t2i = t0 - t2 - 1;
0187     t2--;
0188
0189     val32 = ioread32(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8));
0190     val32 |= t2 << (dev ? 8 : 0);
0191     iowrite32(val32, base + BK3710_REGSTB);
0192
0193     val32 = ioread32(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8));
0194     val32 |= t2i << (dev ? 8 : 0);
0195     iowrite32(val32, base + BK3710_REGRCVR);
0196 }
0197
0198 static void pata_bk3710_set_piomode(struct ata_port *ap,
0199                     struct ata_device *adev)
0200 {
0201     void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr;
0202     struct ata_device *pair = ata_dev_pair(adev);
0203     const struct ata_timing *t = ata_timing_find_mode(adev->pio_mode);
0204     const u16 *id = adev->id;
0205     unsigned int cycle_time = 0;
0206     int is_slave = adev->devno;
0207     const u8 pio = adev->pio_mode - XFER_PIO_0;
0208
0209     if (id[ATA_ID_FIELD_VALID] & 2) {
0210         if (ata_id_has_iordy(id))
0211             cycle_time = id[ATA_ID_EIDE_PIO_IORDY];
0212         else
0213             cycle_time = id[ATA_ID_EIDE_PIO];
0214
0215         /* conservative "downgrade" for all pre-ATA2 drives */
0216         if (pio < 3 && cycle_time < t->cycle)
0217             cycle_time = 0; /* use standard timing */
0218     }
0219
0220     if (!cycle_time)
0221         cycle_time = t->cycle;
0222
0223     pata_bk3710_setpiomode(base, pair, is_slave, cycle_time, pio);
0224 }
0225
0226 static void pata_bk3710_chipinit(void __iomem *base)
0227 {
0228     /*
0229      * REVISIT:  the ATA reset signal needs to be managed through a
0230      * GPIO, which means it should come from platform_data.  Until
0231      * we get and use such information, we have to trust that things
0232      * have been reset before we get here.
0233      */
0234
0235     /*
0236      * Program the IDETIMP Register Value based on the following assumptions
0237      *
0238      * (ATA_IDETIMP_IDEEN       , ENABLE ) |
0239      * (ATA_IDETIMP_PREPOST1    , DISABLE) |
0240      * (ATA_IDETIMP_PREPOST0    , DISABLE) |
0241      *
0242      * DM6446 silicon rev 2.1 and earlier have no observed net benefit
0243      * from enabling prefetch/postwrite.
0244      */
0245     iowrite16(BIT(15), base + BK3710_IDETIMP);
0246
0247     /*
0248      * UDMACTL Ultra-ATA DMA Control
0249      * (ATA_UDMACTL_UDMAP1  , 0 ) |
0250      * (ATA_UDMACTL_UDMAP0  , 0 )
0251      *
0252      */
0253     iowrite16(0, base + BK3710_UDMACTL);
0254
0255     /*
0256      * MISCCTL Miscellaneous Conrol Register
0257      * (ATA_MISCCTL_HWNHLD1P    , 1 cycle)
0258      * (ATA_MISCCTL_HWNHLD0P    , 1 cycle)
0259      * (ATA_MISCCTL_TIMORIDE    , 1)
0260      */
0261     iowrite32(0x001, base + BK3710_MISCCTL);
0262
0263     /*
0264      * IORDYTMP IORDY Timer for Primary Register
0265      * (ATA_IORDYTMP_IORDYTMP   , DISABLE)
0266      */
0267     iowrite32(0, base + BK3710_IORDYTMP);
0268
0269     /*
0270      * Configure BMISP Register
0271      * (ATA_BMISP_DMAEN1    , DISABLE ) |
0272      * (ATA_BMISP_DMAEN0    , DISABLE ) |
0273      * (ATA_BMISP_IORDYINT  , CLEAR)    |
0274      * (ATA_BMISP_INTRSTAT  , CLEAR)    |
0275      * (ATA_BMISP_DMAERROR  , CLEAR)
0276      */
0277     iowrite16(0xE, base + BK3710_BMISP);
0278
0279     pata_bk3710_setpiomode(base, NULL, 0, 600, 0);
0280     pata_bk3710_setpiomode(base, NULL, 1, 600, 0);
0281 }
0282
0283 static struct ata_port_operations pata_bk3710_ports_ops = {
0284     .inherits       = &ata_bmdma_port_ops,
0285     .cable_detect       = ata_cable_80wire,
0286
0287     .set_piomode        = pata_bk3710_set_piomode,
0288     .set_dmamode        = pata_bk3710_set_dmamode,
0289 };
0290
0291 static int __init pata_bk3710_probe(struct platform_device *pdev)
0292 {
0293     struct clk *clk;
0294     struct resource *mem;
0295     struct ata_host *host;
0296     struct ata_port *ap;
0297     void __iomem *base;
0298     unsigned long rate;
0299     int irq;
0300
0301     clk = devm_clk_get(&pdev->dev, NULL);
0302     if (IS_ERR(clk))
0303         return -ENODEV;
0304
0305     clk_enable(clk);
0306     rate = clk_get_rate(clk);
0307     if (!rate)
0308         return -EINVAL;
0309
0310     /* NOTE:  round *down* to meet minimum timings; we count in clocks */
0311     ideclk_period = 1000000000UL / rate;
0312
0313     mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0314
0315     irq = platform_get_irq(pdev, 0);
0316     if (irq < 0) {
0317         pr_err(DRV_NAME ": failed to get IRQ resource\n");
0318         return irq;
0319     }
0320
0321     base = devm_ioremap_resource(&pdev->dev, mem);
0322     if (IS_ERR(base))
0323         return PTR_ERR(base);
0324
0325     /* configure the Palmchip controller */
0326     pata_bk3710_chipinit(base);
0327
0328     /* allocate host */
0329     host = ata_host_alloc(&pdev->dev, 1);
0330     if (!host)
0331         return -ENOMEM;
0332     ap = host->ports[0];
0333
0334     ap->ops = &pata_bk3710_ports_ops;
0335     ap->pio_mask = ATA_PIO4;
0336     ap->mwdma_mask = ATA_MWDMA2;
0337     ap->udma_mask = rate < 100000000 ? ATA_UDMA4 : ATA_UDMA5;
0338     ap->flags |= ATA_FLAG_SLAVE_POSS;
0339
0340     ap->ioaddr.data_addr        = base + BK3710_TF_OFFSET;
0341     ap->ioaddr.error_addr       = base + BK3710_TF_OFFSET + 1;
0342     ap->ioaddr.feature_addr     = base + BK3710_TF_OFFSET + 1;
0343     ap->ioaddr.nsect_addr       = base + BK3710_TF_OFFSET + 2;
0344     ap->ioaddr.lbal_addr        = base + BK3710_TF_OFFSET + 3;
0345     ap->ioaddr.lbam_addr        = base + BK3710_TF_OFFSET + 4;
0346     ap->ioaddr.lbah_addr        = base + BK3710_TF_OFFSET + 5;
0347     ap->ioaddr.device_addr      = base + BK3710_TF_OFFSET + 6;
0348     ap->ioaddr.status_addr      = base + BK3710_TF_OFFSET + 7;
0349     ap->ioaddr.command_addr     = base + BK3710_TF_OFFSET + 7;
0350
0351     ap->ioaddr.altstatus_addr   = base + BK3710_CTL_OFFSET;
0352     ap->ioaddr.ctl_addr     = base + BK3710_CTL_OFFSET;
0353
0354     ap->ioaddr.bmdma_addr       = base;
0355
0356     ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx",
0357               (unsigned long)base + BK3710_TF_OFFSET,
0358               (unsigned long)base + BK3710_CTL_OFFSET);
0359
0360     /* activate */
0361     return ata_host_activate(host, irq, ata_sff_interrupt, 0,
0362                  &pata_bk3710_sht);
0363 }
0364
0365 /* work with hotplug and coldplug */
0366 MODULE_ALIAS("platform:palm_bk3710");
0367
0368 static struct platform_driver pata_bk3710_driver = {
0369     .driver = {
0370         .name = "palm_bk3710",
0371     },
0372 };
0373
0374 static int __init pata_bk3710_init(void)
0375 {
0376     return platform_driver_probe(&pata_bk3710_driver, pata_bk3710_probe);
0377 }
0378
0379 module_init(pata_bk3710_init);
0380 MODULE_LICENSE("GPL v2");