drivers/ata/pata_artop.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *    pata_artop.c - ARTOP ATA controller driver
0004  *
0005  *  (C) 2006 Red Hat
0006  *  (C) 2007,2011 Bartlomiej Zolnierkiewicz
0007  *
0008  *    Based in part on drivers/ide/pci/aec62xx.c
0009  *  Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
0010  *  865/865R fixes for Macintosh card version from a patch to the old
0011  *      driver by Thibaut VARENE <varenet@parisc-linux.org>
0012  *  When setting the PCI latency we must set 0x80 or higher for burst
0013  *      performance Alessandro Zummo <alessandro.zummo@towertech.it>
0014  *
0015  *  TODO
0016  *  Investigate no_dsc on 850R
0017  *  Clock detect
0018  */
0019
0020 #include <linux/kernel.h>
0021 #include <linux/module.h>
0022 #include <linux/pci.h>
0023 #include <linux/blkdev.h>
0024 #include <linux/delay.h>
0025 #include <linux/device.h>
0026 #include <scsi/scsi_host.h>
0027 #include <linux/libata.h>
0028 #include <linux/ata.h>
0029
0030 #define DRV_NAME    "pata_artop"
0031 #define DRV_VERSION "0.4.8"
0032
0033 /*
0034  *  The ARTOP has 33 Mhz and "over clocked" timing tables. Until we
0035  *  get PCI bus speed functionality we leave this as 0. Its a variable
0036  *  for when we get the functionality and also for folks wanting to
0037  *  test stuff.
0038  */
0039
0040 static int clock = 0;
0041
0042 /**
0043  *  artop62x0_pre_reset -   probe begin
0044  *  @link: link
0045  *  @deadline: deadline jiffies for the operation
0046  *
0047  *  Nothing complicated needed here.
0048  */
0049
0050 static int artop62x0_pre_reset(struct ata_link *link, unsigned long deadline)
0051 {
0052     static const struct pci_bits artop_enable_bits[] = {
0053         { 0x4AU, 1U, 0x02UL, 0x02UL },  /* port 0 */
0054         { 0x4AU, 1U, 0x04UL, 0x04UL },  /* port 1 */
0055     };
0056
0057     struct ata_port *ap = link->ap;
0058     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0059
0060     /* Odd numbered device ids are the units with enable bits. */
0061     if ((pdev->device & 1) &&
0062         !pci_test_config_bits(pdev, &artop_enable_bits[ap->port_no]))
0063         return -ENOENT;
0064
0065     return ata_sff_prereset(link, deadline);
0066 }
0067
0068 /**
0069  *  artop6260_cable_detect  -   identify cable type
0070  *  @ap: Port
0071  *
0072  *  Identify the cable type for the ARTOP interface in question
0073  */
0074
0075 static int artop6260_cable_detect(struct ata_port *ap)
0076 {
0077     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0078     u8 tmp;
0079     pci_read_config_byte(pdev, 0x49, &tmp);
0080     if (tmp & (1 << ap->port_no))
0081         return ATA_CBL_PATA40;
0082     return ATA_CBL_PATA80;
0083 }
0084
0085 /**
0086  *  artop6210_load_piomode - Load a set of PATA PIO timings
0087  *  @ap: Port whose timings we are configuring
0088  *  @adev: Device
0089  *  @pio: PIO mode
0090  *
0091  *  Set PIO mode for device, in host controller PCI config space. This
0092  *  is used both to set PIO timings in PIO mode and also to set the
0093  *  matching PIO clocking for UDMA, as well as the MWDMA timings.
0094  *
0095  *  LOCKING:
0096  *  None (inherited from caller).
0097  */
0098
0099 static void artop6210_load_piomode(struct ata_port *ap, struct ata_device *adev, unsigned int pio)
0100 {
0101     struct pci_dev *pdev    = to_pci_dev(ap->host->dev);
0102     int dn = adev->devno + 2 * ap->port_no;
0103     static const u16 timing[2][5] = {
0104         { 0x0000, 0x000A, 0x0008, 0x0303, 0x0301 },
0105         { 0x0700, 0x070A, 0x0708, 0x0403, 0x0401 }
0106
0107     };
0108     /* Load the PIO timing active/recovery bits */
0109     pci_write_config_word(pdev, 0x40 + 2 * dn, timing[clock][pio]);
0110 }
0111
0112 /**
0113  *  artop6210_set_piomode - Initialize host controller PATA PIO timings
0114  *  @ap: Port whose timings we are configuring
0115  *  @adev: Device we are configuring
0116  *
0117  *  Set PIO mode for device, in host controller PCI config space. For
0118  *  ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
0119  *  the event UDMA is used the later call to set_dmamode will set the
0120  *  bits as required.
0121  *
0122  *  LOCKING:
0123  *  None (inherited from caller).
0124  */
0125
0126 static void artop6210_set_piomode(struct ata_port *ap, struct ata_device *adev)
0127 {
0128     struct pci_dev *pdev    = to_pci_dev(ap->host->dev);
0129     int dn = adev->devno + 2 * ap->port_no;
0130     u8 ultra;
0131
0132     artop6210_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
0133
0134     /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
0135     pci_read_config_byte(pdev, 0x54, &ultra);
0136     ultra &= ~(3 << (2 * dn));
0137     pci_write_config_byte(pdev, 0x54, ultra);
0138 }
0139
0140 /**
0141  *  artop6260_load_piomode - Initialize host controller PATA PIO timings
0142  *  @ap: Port whose timings we are configuring
0143  *  @adev: Device we are configuring
0144  *  @pio: PIO mode
0145  *
0146  *  Set PIO mode for device, in host controller PCI config space. The
0147  *  ARTOP6260 and relatives store the timing data differently.
0148  *
0149  *  LOCKING:
0150  *  None (inherited from caller).
0151  */
0152
0153 static void artop6260_load_piomode (struct ata_port *ap, struct ata_device *adev, unsigned int pio)
0154 {
0155     struct pci_dev *pdev    = to_pci_dev(ap->host->dev);
0156     int dn = adev->devno + 2 * ap->port_no;
0157     static const u8 timing[2][5] = {
0158         { 0x00, 0x0A, 0x08, 0x33, 0x31 },
0159         { 0x70, 0x7A, 0x78, 0x43, 0x41 }
0160
0161     };
0162     /* Load the PIO timing active/recovery bits */
0163     pci_write_config_byte(pdev, 0x40 + dn, timing[clock][pio]);
0164 }
0165
0166 /**
0167  *  artop6260_set_piomode - Initialize host controller PATA PIO timings
0168  *  @ap: Port whose timings we are configuring
0169  *  @adev: Device we are configuring
0170  *
0171  *  Set PIO mode for device, in host controller PCI config space. For
0172  *  ARTOP we must also clear the UDMA bits if we are not doing UDMA. In
0173  *  the event UDMA is used the later call to set_dmamode will set the
0174  *  bits as required.
0175  *
0176  *  LOCKING:
0177  *  None (inherited from caller).
0178  */
0179
0180 static void artop6260_set_piomode(struct ata_port *ap, struct ata_device *adev)
0181 {
0182     struct pci_dev *pdev    = to_pci_dev(ap->host->dev);
0183     u8 ultra;
0184
0185     artop6260_load_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
0186
0187     /* Clear the UDMA mode bits (set_dmamode will redo this if needed) */
0188     pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
0189     ultra &= ~(7 << (4  * adev->devno));    /* One nibble per drive */
0190     pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
0191 }
0192
0193 /**
0194  *  artop6210_set_dmamode - Initialize host controller PATA PIO timings
0195  *  @ap: Port whose timings we are configuring
0196  *  @adev: Device whose timings we are configuring
0197  *
0198  *  Set DMA mode for device, in host controller PCI config space.
0199  *
0200  *  LOCKING:
0201  *  None (inherited from caller).
0202  */
0203
0204 static void artop6210_set_dmamode (struct ata_port *ap, struct ata_device *adev)
0205 {
0206     unsigned int pio;
0207     struct pci_dev *pdev    = to_pci_dev(ap->host->dev);
0208     int dn = adev->devno + 2 * ap->port_no;
0209     u8 ultra;
0210
0211     if (adev->dma_mode == XFER_MW_DMA_0)
0212         pio = 1;
0213     else
0214         pio = 4;
0215
0216     /* Load the PIO timing active/recovery bits */
0217     artop6210_load_piomode(ap, adev, pio);
0218
0219     pci_read_config_byte(pdev, 0x54, &ultra);
0220     ultra &= ~(3 << (2 * dn));
0221
0222     /* Add ultra DMA bits if in UDMA mode */
0223     if (adev->dma_mode >= XFER_UDMA_0) {
0224         u8 mode = (adev->dma_mode - XFER_UDMA_0) + 1 - clock;
0225         if (mode == 0)
0226             mode = 1;
0227         ultra |= (mode << (2 * dn));
0228     }
0229     pci_write_config_byte(pdev, 0x54, ultra);
0230 }
0231
0232 /**
0233  *  artop6260_set_dmamode - Initialize host controller PATA PIO timings
0234  *  @ap: Port whose timings we are configuring
0235  *  @adev: Device we are configuring
0236  *
0237  *  Set DMA mode for device, in host controller PCI config space. The
0238  *  ARTOP6260 and relatives store the timing data differently.
0239  *
0240  *  LOCKING:
0241  *  None (inherited from caller).
0242  */
0243
0244 static void artop6260_set_dmamode (struct ata_port *ap, struct ata_device *adev)
0245 {
0246     unsigned int pio;
0247     struct pci_dev *pdev    = to_pci_dev(ap->host->dev);
0248     u8 ultra;
0249
0250     if (adev->dma_mode == XFER_MW_DMA_0)
0251         pio = 1;
0252     else
0253         pio = 4;
0254
0255     /* Load the PIO timing active/recovery bits */
0256     artop6260_load_piomode(ap, adev, pio);
0257
0258     /* Add ultra DMA bits if in UDMA mode */
0259     pci_read_config_byte(pdev, 0x44 + ap->port_no, &ultra);
0260     ultra &= ~(7 << (4  * adev->devno));    /* One nibble per drive */
0261     if (adev->dma_mode >= XFER_UDMA_0) {
0262         u8 mode = adev->dma_mode - XFER_UDMA_0 + 1 - clock;
0263         if (mode == 0)
0264             mode = 1;
0265         ultra |= (mode << (4 * adev->devno));
0266     }
0267     pci_write_config_byte(pdev, 0x44 + ap->port_no, ultra);
0268 }
0269
0270 /**
0271  *  artop6210_qc_defer  -   implement serialization
0272  *  @qc: command
0273  *
0274  *  Issue commands per host on this chip.
0275  */
0276
0277 static int artop6210_qc_defer(struct ata_queued_cmd *qc)
0278 {
0279     struct ata_host *host = qc->ap->host;
0280     struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
0281     int rc;
0282
0283     /* First apply the usual rules */
0284     rc = ata_std_qc_defer(qc);
0285     if (rc != 0)
0286         return rc;
0287
0288     /* Now apply serialization rules. Only allow a command if the
0289        other channel state machine is idle */
0290     if (alt && alt->qc_active)
0291         return  ATA_DEFER_PORT;
0292     return 0;
0293 }
0294
0295 static struct scsi_host_template artop_sht = {
0296     ATA_BMDMA_SHT(DRV_NAME),
0297 };
0298
0299 static struct ata_port_operations artop6210_ops = {
0300     .inherits       = &ata_bmdma_port_ops,
0301     .cable_detect       = ata_cable_40wire,
0302     .set_piomode        = artop6210_set_piomode,
0303     .set_dmamode        = artop6210_set_dmamode,
0304     .prereset       = artop62x0_pre_reset,
0305     .qc_defer       = artop6210_qc_defer,
0306 };
0307
0308 static struct ata_port_operations artop6260_ops = {
0309     .inherits       = &ata_bmdma_port_ops,
0310     .cable_detect       = artop6260_cable_detect,
0311     .set_piomode        = artop6260_set_piomode,
0312     .set_dmamode        = artop6260_set_dmamode,
0313     .prereset       = artop62x0_pre_reset,
0314 };
0315
0316 static void atp8xx_fixup(struct pci_dev *pdev)
0317 {
0318     u8 reg;
0319
0320     switch (pdev->device) {
0321     case 0x0005:
0322         /* BIOS may have left us in UDMA, clear it before libata probe */
0323         pci_write_config_byte(pdev, 0x54, 0);
0324         break;
0325     case 0x0008:
0326     case 0x0009:
0327         /* Mac systems come up with some registers not set as we
0328            will need them */
0329
0330         /* Clear reset & test bits */
0331         pci_read_config_byte(pdev, 0x49, &reg);
0332         pci_write_config_byte(pdev, 0x49, reg & ~0x30);
0333
0334         /* PCI latency must be > 0x80 for burst mode, tweak it
0335          * if required.
0336          */
0337         pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &reg);
0338         if (reg <= 0x80)
0339             pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x90);
0340
0341         /* Enable IRQ output and burst mode */
0342         pci_read_config_byte(pdev, 0x4a, &reg);
0343         pci_write_config_byte(pdev, 0x4a, (reg & ~0x01) | 0x80);
0344         break;
0345     }
0346 }
0347
0348 /**
0349  *  artop_init_one - Register ARTOP ATA PCI device with kernel services
0350  *  @pdev: PCI device to register
0351  *  @id: PCI device ID
0352  *
0353  *  Called from kernel PCI layer.
0354  *
0355  *  LOCKING:
0356  *  Inherited from PCI layer (may sleep).
0357  *
0358  *  RETURNS:
0359  *  Zero on success, or -ERRNO value.
0360  */
0361
0362 static int artop_init_one (struct pci_dev *pdev, const struct pci_device_id *id)
0363 {
0364     static const struct ata_port_info info_6210 = {
0365         .flags      = ATA_FLAG_SLAVE_POSS,
0366         .pio_mask   = ATA_PIO4,
0367         .mwdma_mask = ATA_MWDMA2,
0368         .udma_mask  = ATA_UDMA2,
0369         .port_ops   = &artop6210_ops,
0370     };
0371     static const struct ata_port_info info_626x = {
0372         .flags      = ATA_FLAG_SLAVE_POSS,
0373         .pio_mask   = ATA_PIO4,
0374         .mwdma_mask = ATA_MWDMA2,
0375         .udma_mask  = ATA_UDMA4,
0376         .port_ops   = &artop6260_ops,
0377     };
0378     static const struct ata_port_info info_628x = {
0379         .flags      = ATA_FLAG_SLAVE_POSS,
0380         .pio_mask   = ATA_PIO4,
0381         .mwdma_mask = ATA_MWDMA2,
0382         .udma_mask  = ATA_UDMA5,
0383         .port_ops   = &artop6260_ops,
0384     };
0385     static const struct ata_port_info info_628x_fast = {
0386         .flags      = ATA_FLAG_SLAVE_POSS,
0387         .pio_mask   = ATA_PIO4,
0388         .mwdma_mask = ATA_MWDMA2,
0389         .udma_mask  = ATA_UDMA6,
0390         .port_ops   = &artop6260_ops,
0391     };
0392     const struct ata_port_info *ppi[] = { NULL, NULL };
0393     int rc;
0394
0395     ata_print_version_once(&pdev->dev, DRV_VERSION);
0396
0397     rc = pcim_enable_device(pdev);
0398     if (rc)
0399         return rc;
0400
0401     switch (id->driver_data) {
0402     case 0:     /* 6210 variant */
0403         ppi[0] = &info_6210;
0404         break;
0405     case 1:     /* 6260 */
0406         ppi[0] = &info_626x;
0407         break;
0408     case 2:     /* 6280 or 6280 + fast */
0409         if (inb(pci_resource_start(pdev, 4)) & 0x10)
0410             ppi[0] = &info_628x_fast;
0411         else
0412             ppi[0] = &info_628x;
0413         break;
0414     }
0415
0416     BUG_ON(ppi[0] == NULL);
0417
0418     atp8xx_fixup(pdev);
0419
0420     return ata_pci_bmdma_init_one(pdev, ppi, &artop_sht, NULL, 0);
0421 }
0422
0423 static const struct pci_device_id artop_pci_tbl[] = {
0424     { PCI_VDEVICE(ARTOP, 0x0005), 0 },
0425     { PCI_VDEVICE(ARTOP, 0x0006), 1 },
0426     { PCI_VDEVICE(ARTOP, 0x0007), 1 },
0427     { PCI_VDEVICE(ARTOP, 0x0008), 2 },
0428     { PCI_VDEVICE(ARTOP, 0x0009), 2 },
0429
0430     { } /* terminate list */
0431 };
0432
0433 #ifdef CONFIG_PM_SLEEP
0434 static int atp8xx_reinit_one(struct pci_dev *pdev)
0435 {
0436     struct ata_host *host = pci_get_drvdata(pdev);
0437     int rc;
0438
0439     rc = ata_pci_device_do_resume(pdev);
0440     if (rc)
0441         return rc;
0442
0443     atp8xx_fixup(pdev);
0444
0445     ata_host_resume(host);
0446     return 0;
0447 }
0448 #endif
0449
0450 static struct pci_driver artop_pci_driver = {
0451     .name           = DRV_NAME,
0452     .id_table       = artop_pci_tbl,
0453     .probe          = artop_init_one,
0454     .remove         = ata_pci_remove_one,
0455 #ifdef CONFIG_PM_SLEEP
0456     .suspend        = ata_pci_device_suspend,
0457     .resume         = atp8xx_reinit_one,
0458 #endif
0459 };
0460
0461 module_pci_driver(artop_pci_driver);
0462
0463 MODULE_AUTHOR("Alan Cox, Bartlomiej Zolnierkiewicz");
0464 MODULE_DESCRIPTION("SCSI low-level driver for ARTOP PATA");
0465 MODULE_LICENSE("GPL");
0466 MODULE_DEVICE_TABLE(pci, artop_pci_tbl);
0467 MODULE_VERSION(DRV_VERSION);