drivers/ata/pata_amd.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * pata_amd.c   - AMD PATA for new ATA layer
0004  *            (C) 2005-2006 Red Hat Inc
0005  *
0006  *  Based on pata-sil680. Errata information is taken from data sheets
0007  *  and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
0008  *  claimed by sata-nv.c.
0009  *
0010  *  TODO:
0011  *  Variable system clock when/if it makes sense
0012  *  Power management on ports
0013  *
0014  *
0015  *  Documentation publicly available.
0016  */
0017
0018 #include <linux/kernel.h>
0019 #include <linux/module.h>
0020 #include <linux/pci.h>
0021 #include <linux/blkdev.h>
0022 #include <linux/delay.h>
0023 #include <scsi/scsi_host.h>
0024 #include <linux/libata.h>
0025
0026 #define DRV_NAME "pata_amd"
0027 #define DRV_VERSION "0.4.1"
0028
0029 /**
0030  *  timing_setup        -   shared timing computation and load
0031  *  @ap: ATA port being set up
0032  *  @adev: drive being configured
0033  *  @offset: port offset
0034  *  @speed: target speed
0035  *  @clock: clock multiplier (number of times 33MHz for this part)
0036  *
0037  *  Perform the actual timing set up for Nvidia or AMD PATA devices.
0038  *  The actual devices vary so they all call into this helper function
0039  *  providing the clock multipler and offset (because AMD and Nvidia put
0040  *  the ports at different locations).
0041  */
0042
0043 static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
0044 {
0045     static const unsigned char amd_cyc2udma[] = {
0046         6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
0047     };
0048
0049     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0050     struct ata_device *peer = ata_dev_pair(adev);
0051     int dn = ap->port_no * 2 + adev->devno;
0052     struct ata_timing at, apeer;
0053     int T, UT;
0054     const int amd_clock = 33333;    /* KHz. */
0055     u8 t;
0056
0057     T = 1000000000 / amd_clock;
0058     UT = T;
0059     if (clock >= 2)
0060         UT = T / 2;
0061
0062     if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
0063         dev_err(&pdev->dev, "unknown mode %d\n", speed);
0064         return;
0065     }
0066
0067     if (peer) {
0068         /* This may be over conservative */
0069         if (ata_dma_enabled(peer)) {
0070             ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
0071             ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
0072         }
0073         ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
0074         ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
0075     }
0076
0077     if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
0078     if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
0079
0080     /*
0081      *  Now do the setup work
0082      */
0083
0084     /* Configure the address set up timing */
0085     pci_read_config_byte(pdev, offset + 0x0C, &t);
0086     t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
0087     pci_write_config_byte(pdev, offset + 0x0C , t);
0088
0089     /* Configure the 8bit I/O timing */
0090     pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
0091         ((clamp_val(at.act8b, 1, 16) - 1) << 4) | (clamp_val(at.rec8b, 1, 16) - 1));
0092
0093     /* Drive timing */
0094     pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
0095         ((clamp_val(at.active, 1, 16) - 1) << 4) | (clamp_val(at.recover, 1, 16) - 1));
0096
0097     switch (clock) {
0098         case 1:
0099         t = at.udma ? (0xc0 | (clamp_val(at.udma, 2, 5) - 2)) : 0x03;
0100         break;
0101
0102         case 2:
0103         t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 2, 10)]) : 0x03;
0104         break;
0105
0106         case 3:
0107         t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 10)]) : 0x03;
0108         break;
0109
0110         case 4:
0111         t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 15)]) : 0x03;
0112         break;
0113
0114         default:
0115             return;
0116     }
0117
0118     /* UDMA timing */
0119     if (at.udma)
0120         pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
0121 }
0122
0123 /**
0124  *  amd_pre_reset       -   perform reset handling
0125  *  @link: ATA link
0126  *  @deadline: deadline jiffies for the operation
0127  *
0128  *  Reset sequence checking enable bits to see which ports are
0129  *  active.
0130  */
0131
0132 static int amd_pre_reset(struct ata_link *link, unsigned long deadline)
0133 {
0134     static const struct pci_bits amd_enable_bits[] = {
0135         { 0x40, 1, 0x02, 0x02 },
0136         { 0x40, 1, 0x01, 0x01 }
0137     };
0138
0139     struct ata_port *ap = link->ap;
0140     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0141
0142     if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
0143         return -ENOENT;
0144
0145     return ata_sff_prereset(link, deadline);
0146 }
0147
0148 /**
0149  *  amd_cable_detect    -   report cable type
0150  *  @ap: port
0151  *
0152  *  AMD controller/BIOS setups record the cable type in word 0x42
0153  */
0154
0155 static int amd_cable_detect(struct ata_port *ap)
0156 {
0157     static const u32 bitmask[2] = {0x03, 0x0C};
0158     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0159     u8 ata66;
0160
0161     pci_read_config_byte(pdev, 0x42, &ata66);
0162     if (ata66 & bitmask[ap->port_no])
0163         return ATA_CBL_PATA80;
0164     return ATA_CBL_PATA40;
0165 }
0166
0167 /**
0168  *  amd_fifo_setup      -   set the PIO FIFO for ATA/ATAPI
0169  *  @ap: ATA interface
0170  *
0171  *  Set the PCI fifo for this device according to the devices present
0172  *  on the bus at this point in time. We need to turn the post write buffer
0173  *  off for ATAPI devices as we may need to issue a word sized write to the
0174  *  device as the final I/O
0175  */
0176
0177 static void amd_fifo_setup(struct ata_port *ap)
0178 {
0179     struct ata_device *adev;
0180     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0181     static const u8 fifobit[2] = { 0xC0, 0x30};
0182     u8 fifo = fifobit[ap->port_no];
0183     u8 r;
0184
0185
0186     ata_for_each_dev(adev, &ap->link, ENABLED) {
0187         if (adev->class == ATA_DEV_ATAPI)
0188             fifo = 0;
0189     }
0190     if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411) /* FIFO is broken */
0191         fifo = 0;
0192
0193     /* On the later chips the read prefetch bits become no-op bits */
0194     pci_read_config_byte(pdev, 0x41, &r);
0195     r &= ~fifobit[ap->port_no];
0196     r |= fifo;
0197     pci_write_config_byte(pdev, 0x41, r);
0198 }
0199
0200 /**
0201  *  amd33_set_piomode   -   set initial PIO mode data
0202  *  @ap: ATA interface
0203  *  @adev: ATA device
0204  *
0205  *  Program the AMD registers for PIO mode.
0206  */
0207
0208 static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
0209 {
0210     amd_fifo_setup(ap);
0211     timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
0212 }
0213
0214 static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
0215 {
0216     amd_fifo_setup(ap);
0217     timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
0218 }
0219
0220 static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
0221 {
0222     amd_fifo_setup(ap);
0223     timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
0224 }
0225
0226 static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
0227 {
0228     amd_fifo_setup(ap);
0229     timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
0230 }
0231
0232 /**
0233  *  amd33_set_dmamode   -   set initial DMA mode data
0234  *  @ap: ATA interface
0235  *  @adev: ATA device
0236  *
0237  *  Program the MWDMA/UDMA modes for the AMD and Nvidia
0238  *  chipset.
0239  */
0240
0241 static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0242 {
0243     timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
0244 }
0245
0246 static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0247 {
0248     timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
0249 }
0250
0251 static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0252 {
0253     timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
0254 }
0255
0256 static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0257 {
0258     timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
0259 }
0260
0261 /* Both host-side and drive-side detection results are worthless on NV
0262  * PATAs.  Ignore them and just follow what BIOS configured.  Both the
0263  * current configuration in PCI config reg and ACPI GTM result are
0264  * cached during driver attach and are consulted to select transfer
0265  * mode.
0266  */
0267 static unsigned int nv_mode_filter(struct ata_device *dev,
0268                    unsigned int xfer_mask)
0269 {
0270     static const unsigned int udma_mask_map[] =
0271         { ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0,
0272           ATA_UDMA3, ATA_UDMA4, ATA_UDMA5, ATA_UDMA6 };
0273     struct ata_port *ap = dev->link->ap;
0274     char acpi_str[32] = "";
0275     u32 saved_udma, udma;
0276     const struct ata_acpi_gtm *gtm;
0277     unsigned int bios_limit = 0, acpi_limit = 0, limit;
0278
0279     /* find out what BIOS configured */
0280     udma = saved_udma = (unsigned long)ap->host->private_data;
0281
0282     if (ap->port_no == 0)
0283         udma >>= 16;
0284     if (dev->devno == 0)
0285         udma >>= 8;
0286
0287     if ((udma & 0xc0) == 0xc0)
0288         bios_limit = ata_pack_xfermask(0, 0, udma_mask_map[udma & 0x7]);
0289
0290     /* consult ACPI GTM too */
0291     gtm = ata_acpi_init_gtm(ap);
0292     if (gtm) {
0293         acpi_limit = ata_acpi_gtm_xfermask(dev, gtm);
0294
0295         snprintf(acpi_str, sizeof(acpi_str), " (%u:%u:0x%x)",
0296              gtm->drive[0].dma, gtm->drive[1].dma, gtm->flags);
0297     }
0298
0299     /* be optimistic, EH can take care of things if something goes wrong */
0300     limit = bios_limit | acpi_limit;
0301
0302     /* If PIO or DMA isn't configured at all, don't limit.  Let EH
0303      * handle it.
0304      */
0305     if (!(limit & ATA_MASK_PIO))
0306         limit |= ATA_MASK_PIO;
0307     if (!(limit & (ATA_MASK_MWDMA | ATA_MASK_UDMA)))
0308         limit |= ATA_MASK_MWDMA | ATA_MASK_UDMA;
0309     /* PIO4, MWDMA2, UDMA2 should always be supported regardless of
0310        cable detection result */
0311     limit |= ata_pack_xfermask(ATA_PIO4, ATA_MWDMA2, ATA_UDMA2);
0312
0313     ata_port_dbg(ap,
0314              "nv_mode_filter: 0x%x&0x%x->0x%x, BIOS=0x%x (0x%x) ACPI=0x%x%s\n",
0315              xfer_mask, limit, xfer_mask & limit, bios_limit,
0316              saved_udma, acpi_limit, acpi_str);
0317
0318     return xfer_mask & limit;
0319 }
0320
0321 /**
0322  *  nv_pre_reset    -   cable detection
0323  *  @link: ATA link
0324  *  @deadline: deadline jiffies for the operation
0325  *
0326  *  Perform cable detection. The BIOS stores this in PCI config
0327  *  space for us.
0328  */
0329
0330 static int nv_pre_reset(struct ata_link *link, unsigned long deadline)
0331 {
0332     static const struct pci_bits nv_enable_bits[] = {
0333         { 0x50, 1, 0x02, 0x02 },
0334         { 0x50, 1, 0x01, 0x01 }
0335     };
0336
0337     struct ata_port *ap = link->ap;
0338     struct pci_dev *pdev = to_pci_dev(ap->host->dev);
0339
0340     if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
0341         return -ENOENT;
0342
0343     return ata_sff_prereset(link, deadline);
0344 }
0345
0346 /**
0347  *  nv100_set_piomode   -   set initial PIO mode data
0348  *  @ap: ATA interface
0349  *  @adev: ATA device
0350  *
0351  *  Program the AMD registers for PIO mode.
0352  */
0353
0354 static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
0355 {
0356     timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
0357 }
0358
0359 static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
0360 {
0361     timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
0362 }
0363
0364 /**
0365  *  nv100_set_dmamode   -   set initial DMA mode data
0366  *  @ap: ATA interface
0367  *  @adev: ATA device
0368  *
0369  *  Program the MWDMA/UDMA modes for the AMD and Nvidia
0370  *  chipset.
0371  */
0372
0373 static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0374 {
0375     timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
0376 }
0377
0378 static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
0379 {
0380     timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
0381 }
0382
0383 static void nv_host_stop(struct ata_host *host)
0384 {
0385     u32 udma = (unsigned long)host->private_data;
0386
0387     /* restore PCI config register 0x60 */
0388     pci_write_config_dword(to_pci_dev(host->dev), 0x60, udma);
0389 }
0390
0391 static struct scsi_host_template amd_sht = {
0392     ATA_BMDMA_SHT(DRV_NAME),
0393 };
0394
0395 static const struct ata_port_operations amd_base_port_ops = {
0396     .inherits   = &ata_bmdma32_port_ops,
0397     .prereset   = amd_pre_reset,
0398 };
0399
0400 static struct ata_port_operations amd33_port_ops = {
0401     .inherits   = &amd_base_port_ops,
0402     .cable_detect   = ata_cable_40wire,
0403     .set_piomode    = amd33_set_piomode,
0404     .set_dmamode    = amd33_set_dmamode,
0405 };
0406
0407 static struct ata_port_operations amd66_port_ops = {
0408     .inherits   = &amd_base_port_ops,
0409     .cable_detect   = ata_cable_unknown,
0410     .set_piomode    = amd66_set_piomode,
0411     .set_dmamode    = amd66_set_dmamode,
0412 };
0413
0414 static struct ata_port_operations amd100_port_ops = {
0415     .inherits   = &amd_base_port_ops,
0416     .cable_detect   = ata_cable_unknown,
0417     .set_piomode    = amd100_set_piomode,
0418     .set_dmamode    = amd100_set_dmamode,
0419 };
0420
0421 static struct ata_port_operations amd133_port_ops = {
0422     .inherits   = &amd_base_port_ops,
0423     .cable_detect   = amd_cable_detect,
0424     .set_piomode    = amd133_set_piomode,
0425     .set_dmamode    = amd133_set_dmamode,
0426 };
0427
0428 static const struct ata_port_operations nv_base_port_ops = {
0429     .inherits   = &ata_bmdma_port_ops,
0430     .cable_detect   = ata_cable_ignore,
0431     .mode_filter    = nv_mode_filter,
0432     .prereset   = nv_pre_reset,
0433     .host_stop  = nv_host_stop,
0434 };
0435
0436 static struct ata_port_operations nv100_port_ops = {
0437     .inherits   = &nv_base_port_ops,
0438     .set_piomode    = nv100_set_piomode,
0439     .set_dmamode    = nv100_set_dmamode,
0440 };
0441
0442 static struct ata_port_operations nv133_port_ops = {
0443     .inherits   = &nv_base_port_ops,
0444     .set_piomode    = nv133_set_piomode,
0445     .set_dmamode    = nv133_set_dmamode,
0446 };
0447
0448 static void amd_clear_fifo(struct pci_dev *pdev)
0449 {
0450     u8 fifo;
0451     /* Disable the FIFO, the FIFO logic will re-enable it as
0452        appropriate */
0453     pci_read_config_byte(pdev, 0x41, &fifo);
0454     fifo &= 0x0F;
0455     pci_write_config_byte(pdev, 0x41, fifo);
0456 }
0457
0458 static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
0459 {
0460     static const struct ata_port_info info[10] = {
0461         {   /* 0: AMD 7401 - no swdma */
0462             .flags = ATA_FLAG_SLAVE_POSS,
0463             .pio_mask = ATA_PIO4,
0464             .mwdma_mask = ATA_MWDMA2,
0465             .udma_mask = ATA_UDMA2,
0466             .port_ops = &amd33_port_ops
0467         },
0468         {   /* 1: Early AMD7409 - no swdma */
0469             .flags = ATA_FLAG_SLAVE_POSS,
0470             .pio_mask = ATA_PIO4,
0471             .mwdma_mask = ATA_MWDMA2,
0472             .udma_mask = ATA_UDMA4,
0473             .port_ops = &amd66_port_ops
0474         },
0475         {   /* 2: AMD 7409 */
0476             .flags = ATA_FLAG_SLAVE_POSS,
0477             .pio_mask = ATA_PIO4,
0478             .mwdma_mask = ATA_MWDMA2,
0479             .udma_mask = ATA_UDMA4,
0480             .port_ops = &amd66_port_ops
0481         },
0482         {   /* 3: AMD 7411 */
0483             .flags = ATA_FLAG_SLAVE_POSS,
0484             .pio_mask = ATA_PIO4,
0485             .mwdma_mask = ATA_MWDMA2,
0486             .udma_mask = ATA_UDMA5,
0487             .port_ops = &amd100_port_ops
0488         },
0489         {   /* 4: AMD 7441 */
0490             .flags = ATA_FLAG_SLAVE_POSS,
0491             .pio_mask = ATA_PIO4,
0492             .mwdma_mask = ATA_MWDMA2,
0493             .udma_mask = ATA_UDMA5,
0494             .port_ops = &amd100_port_ops
0495         },
0496         {   /* 5: AMD 8111 - no swdma */
0497             .flags = ATA_FLAG_SLAVE_POSS,
0498             .pio_mask = ATA_PIO4,
0499             .mwdma_mask = ATA_MWDMA2,
0500             .udma_mask = ATA_UDMA6,
0501             .port_ops = &amd133_port_ops
0502         },
0503         {   /* 6: AMD 8111 UDMA 100 (Serenade) - no swdma */
0504             .flags = ATA_FLAG_SLAVE_POSS,
0505             .pio_mask = ATA_PIO4,
0506             .mwdma_mask = ATA_MWDMA2,
0507             .udma_mask = ATA_UDMA5,
0508             .port_ops = &amd133_port_ops
0509         },
0510         {   /* 7: Nvidia Nforce */
0511             .flags = ATA_FLAG_SLAVE_POSS,
0512             .pio_mask = ATA_PIO4,
0513             .mwdma_mask = ATA_MWDMA2,
0514             .udma_mask = ATA_UDMA5,
0515             .port_ops = &nv100_port_ops
0516         },
0517         {   /* 8: Nvidia Nforce2 and later - no swdma */
0518             .flags = ATA_FLAG_SLAVE_POSS,
0519             .pio_mask = ATA_PIO4,
0520             .mwdma_mask = ATA_MWDMA2,
0521             .udma_mask = ATA_UDMA6,
0522             .port_ops = &nv133_port_ops
0523         },
0524         {   /* 9: AMD CS5536 (Geode companion) */
0525             .flags = ATA_FLAG_SLAVE_POSS,
0526             .pio_mask = ATA_PIO4,
0527             .mwdma_mask = ATA_MWDMA2,
0528             .udma_mask = ATA_UDMA5,
0529             .port_ops = &amd100_port_ops
0530         }
0531     };
0532     const struct ata_port_info *ppi[] = { NULL, NULL };
0533     int type = id->driver_data;
0534     void *hpriv = NULL;
0535     u8 fifo;
0536     int rc;
0537
0538     ata_print_version_once(&pdev->dev, DRV_VERSION);
0539
0540     rc = pcim_enable_device(pdev);
0541     if (rc)
0542         return rc;
0543
0544     pci_read_config_byte(pdev, 0x41, &fifo);
0545
0546     /* Check for AMD7409 without swdma errata and if found adjust type */
0547     if (type == 1 && pdev->revision > 0x7)
0548         type = 2;
0549
0550     /* Serenade ? */
0551     if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
0552              pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
0553         type = 6;   /* UDMA 100 only */
0554
0555     /*
0556      * Okay, type is determined now.  Apply type-specific workarounds.
0557      */
0558     ppi[0] = &info[type];
0559
0560     if (type < 3)
0561         ata_pci_bmdma_clear_simplex(pdev);
0562     if (pdev->vendor == PCI_VENDOR_ID_AMD)
0563         amd_clear_fifo(pdev);
0564     /* Cable detection on Nvidia chips doesn't work too well,
0565      * cache BIOS programmed UDMA mode.
0566      */
0567     if (type == 7 || type == 8) {
0568         u32 udma;
0569
0570         pci_read_config_dword(pdev, 0x60, &udma);
0571         hpriv = (void *)(unsigned long)udma;
0572     }
0573
0574     /* And fire it up */
0575     return ata_pci_bmdma_init_one(pdev, ppi, &amd_sht, hpriv, 0);
0576 }
0577
0578 #ifdef CONFIG_PM_SLEEP
0579 static int amd_reinit_one(struct pci_dev *pdev)
0580 {
0581     struct ata_host *host = pci_get_drvdata(pdev);
0582     int rc;
0583
0584     rc = ata_pci_device_do_resume(pdev);
0585     if (rc)
0586         return rc;
0587
0588     if (pdev->vendor == PCI_VENDOR_ID_AMD) {
0589         amd_clear_fifo(pdev);
0590         if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 ||
0591             pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
0592             ata_pci_bmdma_clear_simplex(pdev);
0593     }
0594     ata_host_resume(host);
0595     return 0;
0596 }
0597 #endif
0598
0599 static const struct pci_device_id amd[] = {
0600     { PCI_VDEVICE(AMD,  PCI_DEVICE_ID_AMD_COBRA_7401),      0 },
0601     { PCI_VDEVICE(AMD,  PCI_DEVICE_ID_AMD_VIPER_7409),      1 },
0602     { PCI_VDEVICE(AMD,  PCI_DEVICE_ID_AMD_VIPER_7411),      3 },
0603     { PCI_VDEVICE(AMD,  PCI_DEVICE_ID_AMD_OPUS_7441),       4 },
0604     { PCI_VDEVICE(AMD,  PCI_DEVICE_ID_AMD_8111_IDE),        5 },
0605     { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_IDE),   7 },
0606     { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE),  8 },
0607     { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 },
0608     { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE),  8 },
0609     { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 },
0610     { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 },
0611     { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 },
0612     { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 },
0613     { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 },
0614     { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 },
0615     { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 },
0616     { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 },
0617     { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 8 },
0618     { PCI_VDEVICE(NVIDIA,   PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 8 },
0619     { PCI_VDEVICE(AMD,  PCI_DEVICE_ID_AMD_CS5536_IDE),      9 },
0620     { PCI_VDEVICE(AMD,  PCI_DEVICE_ID_AMD_CS5536_DEV_IDE),  9 },
0621
0622     { },
0623 };
0624
0625 static struct pci_driver amd_pci_driver = {
0626     .name       = DRV_NAME,
0627     .id_table   = amd,
0628     .probe      = amd_init_one,
0629     .remove     = ata_pci_remove_one,
0630 #ifdef CONFIG_PM_SLEEP
0631     .suspend    = ata_pci_device_suspend,
0632     .resume     = amd_reinit_one,
0633 #endif
0634 };
0635
0636 module_pci_driver(amd_pci_driver);
0637
0638 MODULE_AUTHOR("Alan Cox");
0639 MODULE_DESCRIPTION("low-level driver for AMD and Nvidia PATA IDE");
0640 MODULE_LICENSE("GPL");
0641 MODULE_DEVICE_TABLE(pci, amd);
0642 MODULE_VERSION(DRV_VERSION);