drivers/ata/libata-pata-timings.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Helper library for PATA timings
0004  *
0005  *  Copyright 2003-2004 Red Hat, Inc.  All rights reserved.
0006  *  Copyright 2003-2004 Jeff Garzik
0007  */
0008
0009 #include <linux/kernel.h>
0010 #include <linux/module.h>
0011 #include <linux/libata.h>
0012
0013 /*
0014  * This mode timing computation functionality is ported over from
0015  * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
0016  */
0017 /*
0018  * PIO 0-4, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
0019  * These were taken from ATA/ATAPI-6 standard, rev 0a, except
0020  * for UDMA6, which is currently supported only by Maxtor drives.
0021  *
0022  * For PIO 5/6 MWDMA 3/4 see the CFA specification 3.0.
0023  */
0024
0025 static const struct ata_timing ata_timing[] = {
0026 /*  { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 0,  960,   0 }, */
0027     { XFER_PIO_0,     70, 290, 240, 600, 165, 150, 0,  600,   0 },
0028     { XFER_PIO_1,     50, 290,  93, 383, 125, 100, 0,  383,   0 },
0029     { XFER_PIO_2,     30, 290,  40, 330, 100,  90, 0,  240,   0 },
0030     { XFER_PIO_3,     30,  80,  70, 180,  80,  70, 0,  180,   0 },
0031     { XFER_PIO_4,     25,  70,  25, 120,  70,  25, 0,  120,   0 },
0032     { XFER_PIO_5,     15,  65,  25, 100,  65,  25, 0,  100,   0 },
0033     { XFER_PIO_6,     10,  55,  20,  80,  55,  20, 0,   80,   0 },
0034
0035     { XFER_SW_DMA_0, 120,   0,   0,   0, 480, 480, 50, 960,   0 },
0036     { XFER_SW_DMA_1,  90,   0,   0,   0, 240, 240, 30, 480,   0 },
0037     { XFER_SW_DMA_2,  60,   0,   0,   0, 120, 120, 20, 240,   0 },
0038
0039     { XFER_MW_DMA_0,  60,   0,   0,   0, 215, 215, 20, 480,   0 },
0040     { XFER_MW_DMA_1,  45,   0,   0,   0,  80,  50, 5,  150,   0 },
0041     { XFER_MW_DMA_2,  25,   0,   0,   0,  70,  25, 5,  120,   0 },
0042     { XFER_MW_DMA_3,  25,   0,   0,   0,  65,  25, 5,  100,   0 },
0043     { XFER_MW_DMA_4,  25,   0,   0,   0,  55,  20, 5,   80,   0 },
0044
0045 /*  { XFER_UDMA_SLOW,  0,   0,   0,   0,   0,   0, 0,    0, 150 }, */
0046     { XFER_UDMA_0,     0,   0,   0,   0,   0,   0, 0,    0, 120 },
0047     { XFER_UDMA_1,     0,   0,   0,   0,   0,   0, 0,    0,  80 },
0048     { XFER_UDMA_2,     0,   0,   0,   0,   0,   0, 0,    0,  60 },
0049     { XFER_UDMA_3,     0,   0,   0,   0,   0,   0, 0,    0,  45 },
0050     { XFER_UDMA_4,     0,   0,   0,   0,   0,   0, 0,    0,  30 },
0051     { XFER_UDMA_5,     0,   0,   0,   0,   0,   0, 0,    0,  20 },
0052     { XFER_UDMA_6,     0,   0,   0,   0,   0,   0, 0,    0,  15 },
0053
0054     { 0xFF }
0055 };
0056
0057 #define ENOUGH(v, unit)     (((v)-1)/(unit)+1)
0058 #define EZ(v, unit)     ((v)?ENOUGH(((v) * 1000), unit):0)
0059
0060 static void ata_timing_quantize(const struct ata_timing *t,
0061                 struct ata_timing *q, int T, int UT)
0062 {
0063     q->setup    = EZ(t->setup,       T);
0064     q->act8b    = EZ(t->act8b,       T);
0065     q->rec8b    = EZ(t->rec8b,       T);
0066     q->cyc8b    = EZ(t->cyc8b,       T);
0067     q->active   = EZ(t->active,      T);
0068     q->recover  = EZ(t->recover,     T);
0069     q->dmack_hold   = EZ(t->dmack_hold,  T);
0070     q->cycle    = EZ(t->cycle,       T);
0071     q->udma     = EZ(t->udma,       UT);
0072 }
0073
0074 void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
0075               struct ata_timing *m, unsigned int what)
0076 {
0077     if (what & ATA_TIMING_SETUP)
0078         m->setup = max(a->setup, b->setup);
0079     if (what & ATA_TIMING_ACT8B)
0080         m->act8b = max(a->act8b, b->act8b);
0081     if (what & ATA_TIMING_REC8B)
0082         m->rec8b = max(a->rec8b, b->rec8b);
0083     if (what & ATA_TIMING_CYC8B)
0084         m->cyc8b = max(a->cyc8b, b->cyc8b);
0085     if (what & ATA_TIMING_ACTIVE)
0086         m->active = max(a->active, b->active);
0087     if (what & ATA_TIMING_RECOVER)
0088         m->recover = max(a->recover, b->recover);
0089     if (what & ATA_TIMING_DMACK_HOLD)
0090         m->dmack_hold = max(a->dmack_hold, b->dmack_hold);
0091     if (what & ATA_TIMING_CYCLE)
0092         m->cycle = max(a->cycle, b->cycle);
0093     if (what & ATA_TIMING_UDMA)
0094         m->udma = max(a->udma, b->udma);
0095 }
0096 EXPORT_SYMBOL_GPL(ata_timing_merge);
0097
0098 const struct ata_timing *ata_timing_find_mode(u8 xfer_mode)
0099 {
0100     const struct ata_timing *t = ata_timing;
0101
0102     while (xfer_mode > t->mode)
0103         t++;
0104
0105     if (xfer_mode == t->mode)
0106         return t;
0107
0108     WARN_ONCE(true, "%s: unable to find timing for xfer_mode 0x%x\n",
0109             __func__, xfer_mode);
0110
0111     return NULL;
0112 }
0113 EXPORT_SYMBOL_GPL(ata_timing_find_mode);
0114
0115 int ata_timing_compute(struct ata_device *adev, unsigned short speed,
0116                struct ata_timing *t, int T, int UT)
0117 {
0118     const u16 *id = adev->id;
0119     const struct ata_timing *s;
0120     struct ata_timing p;
0121
0122     /*
0123      * Find the mode.
0124      */
0125     s = ata_timing_find_mode(speed);
0126     if (!s)
0127         return -EINVAL;
0128
0129     memcpy(t, s, sizeof(*s));
0130
0131     /*
0132      * If the drive is an EIDE drive, it can tell us it needs extended
0133      * PIO/MW_DMA cycle timing.
0134      */
0135
0136     if (id[ATA_ID_FIELD_VALID] & 2) {   /* EIDE drive */
0137         memset(&p, 0, sizeof(p));
0138
0139         if (speed >= XFER_PIO_0 && speed < XFER_SW_DMA_0) {
0140             if (speed <= XFER_PIO_2)
0141                 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO];
0142             else if ((speed <= XFER_PIO_4) ||
0143                  (speed == XFER_PIO_5 && !ata_id_is_cfa(id)))
0144                 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY];
0145         } else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
0146             p.cycle = id[ATA_ID_EIDE_DMA_MIN];
0147
0148         ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
0149     }
0150
0151     /*
0152      * Convert the timing to bus clock counts.
0153      */
0154
0155     ata_timing_quantize(t, t, T, UT);
0156
0157     /*
0158      * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
0159      * S.M.A.R.T * and some other commands. We have to ensure that the
0160      * DMA cycle timing is slower/equal than the fastest PIO timing.
0161      */
0162
0163     if (speed > XFER_PIO_6) {
0164         ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
0165         ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
0166     }
0167
0168     /*
0169      * Lengthen active & recovery time so that cycle time is correct.
0170      */
0171
0172     if (t->act8b + t->rec8b < t->cyc8b) {
0173         t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
0174         t->rec8b = t->cyc8b - t->act8b;
0175     }
0176
0177     if (t->active + t->recover < t->cycle) {
0178         t->active += (t->cycle - (t->active + t->recover)) / 2;
0179         t->recover = t->cycle - t->active;
0180     }
0181
0182     /*
0183      * In a few cases quantisation may produce enough errors to
0184      * leave t->cycle too low for the sum of active and recovery
0185      * if so we must correct this.
0186      */
0187     if (t->active + t->recover > t->cycle)
0188         t->cycle = t->active + t->recover;
0189
0190     return 0;
0191 }
0192 EXPORT_SYMBOL_GPL(ata_timing_compute);