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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Freescale QorIQ AHCI SATA platform driver
0004  *
0005  * Copyright 2015 Freescale, Inc.
0006  *   Tang Yuantian <Yuantian.Tang@freescale.com>
0007  */
0008 
0009 #include <linux/acpi.h>
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/pm.h>
0013 #include <linux/ahci_platform.h>
0014 #include <linux/device.h>
0015 #include <linux/of_address.h>
0016 #include <linux/of.h>
0017 #include <linux/of_device.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/libata.h>
0020 #include "ahci.h"
0021 
0022 #define DRV_NAME "ahci-qoriq"
0023 
0024 /* port register definition */
0025 #define PORT_PHY1   0xA8
0026 #define PORT_PHY2   0xAC
0027 #define PORT_PHY3   0xB0
0028 #define PORT_PHY4   0xB4
0029 #define PORT_PHY5   0xB8
0030 #define PORT_AXICC  0xBC
0031 #define PORT_TRANS  0xC8
0032 
0033 /* port register default value */
0034 #define AHCI_PORT_PHY_1_CFG 0xa003fffe
0035 #define AHCI_PORT_PHY2_CFG  0x28184d1f
0036 #define AHCI_PORT_PHY3_CFG  0x0e081509
0037 #define AHCI_PORT_TRANS_CFG 0x08000029
0038 #define AHCI_PORT_AXICC_CFG 0x3fffffff
0039 
0040 /* for ls1021a */
0041 #define LS1021A_PORT_PHY2   0x28183414
0042 #define LS1021A_PORT_PHY3   0x0e080e06
0043 #define LS1021A_PORT_PHY4   0x064a080b
0044 #define LS1021A_PORT_PHY5   0x2aa86470
0045 #define LS1021A_AXICC_ADDR  0xC0
0046 
0047 #define SATA_ECC_DISABLE    0x00020000
0048 #define ECC_DIS_ARMV8_CH2   0x80000000
0049 #define ECC_DIS_LS1088A     0x40000000
0050 
0051 enum ahci_qoriq_type {
0052     AHCI_LS1021A,
0053     AHCI_LS1028A,
0054     AHCI_LS1043A,
0055     AHCI_LS2080A,
0056     AHCI_LS1046A,
0057     AHCI_LS1088A,
0058     AHCI_LS2088A,
0059     AHCI_LX2160A,
0060 };
0061 
0062 struct ahci_qoriq_priv {
0063     struct ccsr_ahci *reg_base;
0064     enum ahci_qoriq_type type;
0065     void __iomem *ecc_addr;
0066     bool is_dmacoherent;
0067 };
0068 
0069 static bool ecc_initialized;
0070 
0071 static const struct of_device_id ahci_qoriq_of_match[] = {
0072     { .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
0073     { .compatible = "fsl,ls1028a-ahci", .data = (void *)AHCI_LS1028A},
0074     { .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
0075     { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
0076     { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
0077     { .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
0078     { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
0079     { .compatible = "fsl,lx2160a-ahci", .data = (void *)AHCI_LX2160A},
0080     { /* sentinel */ }
0081 };
0082 MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
0083 
0084 static const struct acpi_device_id ahci_qoriq_acpi_match[] = {
0085     {"NXP0004", .driver_data = (kernel_ulong_t)AHCI_LX2160A},
0086     { }
0087 };
0088 MODULE_DEVICE_TABLE(acpi, ahci_qoriq_acpi_match);
0089 
0090 static int ahci_qoriq_hardreset(struct ata_link *link, unsigned int *class,
0091               unsigned long deadline)
0092 {
0093     const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
0094     void __iomem *port_mmio = ahci_port_base(link->ap);
0095     u32 px_cmd, px_is, px_val;
0096     struct ata_port *ap = link->ap;
0097     struct ahci_port_priv *pp = ap->private_data;
0098     struct ahci_host_priv *hpriv = ap->host->private_data;
0099     struct ahci_qoriq_priv *qoriq_priv = hpriv->plat_data;
0100     u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
0101     struct ata_taskfile tf;
0102     bool online;
0103     int rc;
0104     bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
0105 
0106     hpriv->stop_engine(ap);
0107 
0108     /*
0109      * There is a errata on ls1021a Rev1.0 and Rev2.0 which is:
0110      * A-009042: The device detection initialization sequence
0111      * mistakenly resets some registers.
0112      *
0113      * Workaround for this is:
0114      * The software should read and store PxCMD and PxIS values
0115      * before issuing the device detection initialization sequence.
0116      * After the sequence is complete, software should restore the
0117      * PxCMD and PxIS with the stored values.
0118      */
0119     if (ls1021a_workaround) {
0120         px_cmd = readl(port_mmio + PORT_CMD);
0121         px_is = readl(port_mmio + PORT_IRQ_STAT);
0122     }
0123 
0124     /* clear D2H reception area to properly wait for D2H FIS */
0125     ata_tf_init(link->device, &tf);
0126     tf.status = ATA_BUSY;
0127     ata_tf_to_fis(&tf, 0, 0, d2h_fis);
0128 
0129     rc = sata_link_hardreset(link, timing, deadline, &online,
0130                  ahci_check_ready);
0131 
0132     /* restore the PxCMD and PxIS on ls1021 */
0133     if (ls1021a_workaround) {
0134         px_val = readl(port_mmio + PORT_CMD);
0135         if (px_val != px_cmd)
0136             writel(px_cmd, port_mmio + PORT_CMD);
0137 
0138         px_val = readl(port_mmio + PORT_IRQ_STAT);
0139         if (px_val != px_is)
0140             writel(px_is, port_mmio + PORT_IRQ_STAT);
0141     }
0142 
0143     hpriv->start_engine(ap);
0144 
0145     if (online)
0146         *class = ahci_dev_classify(ap);
0147     return rc;
0148 }
0149 
0150 static struct ata_port_operations ahci_qoriq_ops = {
0151     .inherits   = &ahci_ops,
0152     .hardreset  = ahci_qoriq_hardreset,
0153 };
0154 
0155 static const struct ata_port_info ahci_qoriq_port_info = {
0156     .flags      = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
0157     .pio_mask   = ATA_PIO4,
0158     .udma_mask  = ATA_UDMA6,
0159     .port_ops   = &ahci_qoriq_ops,
0160 };
0161 
0162 static struct scsi_host_template ahci_qoriq_sht = {
0163     AHCI_SHT(DRV_NAME),
0164 };
0165 
0166 static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
0167 {
0168     struct ahci_qoriq_priv *qpriv = hpriv->plat_data;
0169     void __iomem *reg_base = hpriv->mmio;
0170 
0171     switch (qpriv->type) {
0172     case AHCI_LS1021A:
0173         if (!(qpriv->ecc_addr || ecc_initialized))
0174             return -EINVAL;
0175         else if (qpriv->ecc_addr && !ecc_initialized)
0176             writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
0177         writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
0178         writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
0179         writel(LS1021A_PORT_PHY3, reg_base + PORT_PHY3);
0180         writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
0181         writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
0182         writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
0183         if (qpriv->is_dmacoherent)
0184             writel(AHCI_PORT_AXICC_CFG,
0185                     reg_base + LS1021A_AXICC_ADDR);
0186         break;
0187 
0188     case AHCI_LS1043A:
0189         if (!(qpriv->ecc_addr || ecc_initialized))
0190             return -EINVAL;
0191         else if (qpriv->ecc_addr && !ecc_initialized)
0192             writel(readl(qpriv->ecc_addr) |
0193                    ECC_DIS_ARMV8_CH2,
0194                    qpriv->ecc_addr);
0195         writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
0196         writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
0197         writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
0198         writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
0199         if (qpriv->is_dmacoherent)
0200             writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
0201         break;
0202 
0203     case AHCI_LS2080A:
0204         writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
0205         writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
0206         writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
0207         writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
0208         if (qpriv->is_dmacoherent)
0209             writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
0210         break;
0211 
0212     case AHCI_LS1046A:
0213         if (!(qpriv->ecc_addr || ecc_initialized))
0214             return -EINVAL;
0215         else if (qpriv->ecc_addr && !ecc_initialized)
0216             writel(readl(qpriv->ecc_addr) |
0217                    ECC_DIS_ARMV8_CH2,
0218                    qpriv->ecc_addr);
0219         writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
0220         writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
0221         writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
0222         writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
0223         if (qpriv->is_dmacoherent)
0224             writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
0225         break;
0226 
0227     case AHCI_LS1028A:
0228     case AHCI_LS1088A:
0229     case AHCI_LX2160A:
0230         if (!(qpriv->ecc_addr || ecc_initialized))
0231             return -EINVAL;
0232         else if (qpriv->ecc_addr && !ecc_initialized)
0233             writel(readl(qpriv->ecc_addr) |
0234                    ECC_DIS_LS1088A,
0235                    qpriv->ecc_addr);
0236         writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
0237         writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
0238         writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
0239         writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
0240         if (qpriv->is_dmacoherent)
0241             writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
0242         break;
0243 
0244     case AHCI_LS2088A:
0245         writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
0246         writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
0247         writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
0248         writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
0249         if (qpriv->is_dmacoherent)
0250             writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
0251         break;
0252     }
0253 
0254     ecc_initialized = true;
0255     return 0;
0256 }
0257 
0258 static int ahci_qoriq_probe(struct platform_device *pdev)
0259 {
0260     struct device_node *np = pdev->dev.of_node;
0261     const struct acpi_device_id *acpi_id;
0262     struct device *dev = &pdev->dev;
0263     struct ahci_host_priv *hpriv;
0264     struct ahci_qoriq_priv *qoriq_priv;
0265     const struct of_device_id *of_id;
0266     struct resource *res;
0267     int rc;
0268 
0269     hpriv = ahci_platform_get_resources(pdev, 0);
0270     if (IS_ERR(hpriv))
0271         return PTR_ERR(hpriv);
0272 
0273     of_id = of_match_node(ahci_qoriq_of_match, np);
0274     acpi_id = acpi_match_device(ahci_qoriq_acpi_match, &pdev->dev);
0275     if (!(of_id || acpi_id))
0276         return -ENODEV;
0277 
0278     qoriq_priv = devm_kzalloc(dev, sizeof(*qoriq_priv), GFP_KERNEL);
0279     if (!qoriq_priv)
0280         return -ENOMEM;
0281 
0282     if (of_id)
0283         qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
0284     else
0285         qoriq_priv->type = (enum ahci_qoriq_type)acpi_id->driver_data;
0286 
0287     if (unlikely(!ecc_initialized)) {
0288         res = platform_get_resource_byname(pdev,
0289                            IORESOURCE_MEM,
0290                            "sata-ecc");
0291         if (res) {
0292             qoriq_priv->ecc_addr =
0293                 devm_ioremap_resource(dev, res);
0294             if (IS_ERR(qoriq_priv->ecc_addr))
0295                 return PTR_ERR(qoriq_priv->ecc_addr);
0296         }
0297     }
0298 
0299     if (device_get_dma_attr(&pdev->dev) == DEV_DMA_COHERENT)
0300         qoriq_priv->is_dmacoherent = true;
0301 
0302     rc = ahci_platform_enable_resources(hpriv);
0303     if (rc)
0304         return rc;
0305 
0306     hpriv->plat_data = qoriq_priv;
0307     rc = ahci_qoriq_phy_init(hpriv);
0308     if (rc)
0309         goto disable_resources;
0310 
0311     rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
0312                      &ahci_qoriq_sht);
0313     if (rc)
0314         goto disable_resources;
0315 
0316     return 0;
0317 
0318 disable_resources:
0319     ahci_platform_disable_resources(hpriv);
0320 
0321     return rc;
0322 }
0323 
0324 #ifdef CONFIG_PM_SLEEP
0325 static int ahci_qoriq_resume(struct device *dev)
0326 {
0327     struct ata_host *host = dev_get_drvdata(dev);
0328     struct ahci_host_priv *hpriv = host->private_data;
0329     int rc;
0330 
0331     rc = ahci_platform_enable_resources(hpriv);
0332     if (rc)
0333         return rc;
0334 
0335     rc = ahci_qoriq_phy_init(hpriv);
0336     if (rc)
0337         goto disable_resources;
0338 
0339     rc = ahci_platform_resume_host(dev);
0340     if (rc)
0341         goto disable_resources;
0342 
0343     /* We resumed so update PM runtime state */
0344     pm_runtime_disable(dev);
0345     pm_runtime_set_active(dev);
0346     pm_runtime_enable(dev);
0347 
0348     return 0;
0349 
0350 disable_resources:
0351     ahci_platform_disable_resources(hpriv);
0352 
0353     return rc;
0354 }
0355 #endif
0356 
0357 static SIMPLE_DEV_PM_OPS(ahci_qoriq_pm_ops, ahci_platform_suspend,
0358              ahci_qoriq_resume);
0359 
0360 static struct platform_driver ahci_qoriq_driver = {
0361     .probe = ahci_qoriq_probe,
0362     .remove = ata_platform_remove_one,
0363     .driver = {
0364         .name = DRV_NAME,
0365         .of_match_table = ahci_qoriq_of_match,
0366         .acpi_match_table = ahci_qoriq_acpi_match,
0367         .pm = &ahci_qoriq_pm_ops,
0368     },
0369 };
0370 module_platform_driver(ahci_qoriq_driver);
0371 
0372 MODULE_DESCRIPTION("Freescale QorIQ AHCI SATA platform driver");
0373 MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
0374 MODULE_LICENSE("GPL");
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