drivers/ata/ahci_mvebu.c

0001 /*
0002  * AHCI glue platform driver for Marvell EBU SOCs
0003  *
0004  * Copyright (C) 2014 Marvell
0005  *
0006  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0007  * Marcin Wojtas <mw@semihalf.com>
0008  *
0009  * This file is licensed under the terms of the GNU General Public
0010  * License version 2.  This program is licensed "as is" without any
0011  * warranty of any kind, whether express or implied.
0012  */
0013
0014 #include <linux/ahci_platform.h>
0015 #include <linux/kernel.h>
0016 #include <linux/mbus.h>
0017 #include <linux/module.h>
0018 #include <linux/of_device.h>
0019 #include <linux/platform_device.h>
0020 #include "ahci.h"
0021
0022 #define DRV_NAME "ahci-mvebu"
0023
0024 #define AHCI_VENDOR_SPECIFIC_0_ADDR  0xa0
0025 #define AHCI_VENDOR_SPECIFIC_0_DATA  0xa4
0026
0027 #define AHCI_WINDOW_CTRL(win)   (0x60 + ((win) << 4))
0028 #define AHCI_WINDOW_BASE(win)   (0x64 + ((win) << 4))
0029 #define AHCI_WINDOW_SIZE(win)   (0x68 + ((win) << 4))
0030
0031 struct ahci_mvebu_plat_data {
0032     int (*plat_config)(struct ahci_host_priv *hpriv);
0033     unsigned int flags;
0034 };
0035
0036 static void ahci_mvebu_mbus_config(struct ahci_host_priv *hpriv,
0037                    const struct mbus_dram_target_info *dram)
0038 {
0039     int i;
0040
0041     for (i = 0; i < 4; i++) {
0042         writel(0, hpriv->mmio + AHCI_WINDOW_CTRL(i));
0043         writel(0, hpriv->mmio + AHCI_WINDOW_BASE(i));
0044         writel(0, hpriv->mmio + AHCI_WINDOW_SIZE(i));
0045     }
0046
0047     for (i = 0; i < dram->num_cs; i++) {
0048         const struct mbus_dram_window *cs = dram->cs + i;
0049
0050         writel((cs->mbus_attr << 8) |
0051                (dram->mbus_dram_target_id << 4) | 1,
0052                hpriv->mmio + AHCI_WINDOW_CTRL(i));
0053         writel(cs->base >> 16, hpriv->mmio + AHCI_WINDOW_BASE(i));
0054         writel(((cs->size - 1) & 0xffff0000),
0055                hpriv->mmio + AHCI_WINDOW_SIZE(i));
0056     }
0057 }
0058
0059 static void ahci_mvebu_regret_option(struct ahci_host_priv *hpriv)
0060 {
0061     /*
0062      * Enable the regret bit to allow the SATA unit to regret a
0063      * request that didn't receive an acknowlegde and avoid a
0064      * deadlock
0065      */
0066     writel(0x4, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_ADDR);
0067     writel(0x80, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA);
0068 }
0069
0070 static int ahci_mvebu_armada_380_config(struct ahci_host_priv *hpriv)
0071 {
0072     const struct mbus_dram_target_info *dram;
0073     int rc = 0;
0074
0075     dram = mv_mbus_dram_info();
0076     if (dram)
0077         ahci_mvebu_mbus_config(hpriv, dram);
0078     else
0079         rc = -ENODEV;
0080
0081     ahci_mvebu_regret_option(hpriv);
0082
0083     return rc;
0084 }
0085
0086 static int ahci_mvebu_armada_3700_config(struct ahci_host_priv *hpriv)
0087 {
0088     u32 reg;
0089
0090     writel(0, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_ADDR);
0091
0092     reg = readl(hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA);
0093     reg |= BIT(6);
0094     writel(reg, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA);
0095
0096     return 0;
0097 }
0098
0099 /**
0100  * ahci_mvebu_stop_engine
0101  *
0102  * @ap: Target ata port
0103  *
0104  * Errata Ref#226 - SATA Disk HOT swap issue when connected through
0105  * Port Multiplier in FIS-based Switching mode.
0106  *
0107  * To avoid the issue, according to design, the bits[11:8, 0] of
0108  * register PxFBS are cleared when Port Command and Status (0x18) bit[0]
0109  * changes its value from 1 to 0, i.e. falling edge of Port
0110  * Command and Status bit[0] sends PULSE that resets PxFBS
0111  * bits[11:8; 0].
0112  *
0113  * This function is used to override function of "ahci_stop_engine"
0114  * from libahci.c by adding the mvebu work around(WA) to save PxFBS
0115  * value before the PxCMD ST write of 0, then restore PxFBS value.
0116  *
0117  * Return: 0 on success; Error code otherwise.
0118  */
0119 static int ahci_mvebu_stop_engine(struct ata_port *ap)
0120 {
0121     void __iomem *port_mmio = ahci_port_base(ap);
0122     u32 tmp, port_fbs;
0123
0124     tmp = readl(port_mmio + PORT_CMD);
0125
0126     /* check if the HBA is idle */
0127     if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
0128         return 0;
0129
0130     /* save the port PxFBS register for later restore */
0131     port_fbs = readl(port_mmio + PORT_FBS);
0132
0133     /* setting HBA to idle */
0134     tmp &= ~PORT_CMD_START;
0135     writel(tmp, port_mmio + PORT_CMD);
0136
0137     /*
0138      * bit #15 PxCMD signal doesn't clear PxFBS,
0139      * restore the PxFBS register right after clearing the PxCMD ST,
0140      * no need to wait for the PxCMD bit #15.
0141      */
0142     writel(port_fbs, port_mmio + PORT_FBS);
0143
0144     /* wait for engine to stop. This could be as long as 500 msec */
0145     tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
0146                 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
0147     if (tmp & PORT_CMD_LIST_ON)
0148         return -EIO;
0149
0150     return 0;
0151 }
0152
0153 #ifdef CONFIG_PM_SLEEP
0154 static int ahci_mvebu_suspend(struct platform_device *pdev, pm_message_t state)
0155 {
0156     return ahci_platform_suspend_host(&pdev->dev);
0157 }
0158
0159 static int ahci_mvebu_resume(struct platform_device *pdev)
0160 {
0161     struct ata_host *host = platform_get_drvdata(pdev);
0162     struct ahci_host_priv *hpriv = host->private_data;
0163     const struct ahci_mvebu_plat_data *pdata = hpriv->plat_data;
0164
0165     pdata->plat_config(hpriv);
0166
0167     return ahci_platform_resume_host(&pdev->dev);
0168 }
0169 #else
0170 #define ahci_mvebu_suspend NULL
0171 #define ahci_mvebu_resume NULL
0172 #endif
0173
0174 static const struct ata_port_info ahci_mvebu_port_info = {
0175     .flags     = AHCI_FLAG_COMMON,
0176     .pio_mask  = ATA_PIO4,
0177     .udma_mask = ATA_UDMA6,
0178     .port_ops  = &ahci_platform_ops,
0179 };
0180
0181 static struct scsi_host_template ahci_platform_sht = {
0182     AHCI_SHT(DRV_NAME),
0183 };
0184
0185 static int ahci_mvebu_probe(struct platform_device *pdev)
0186 {
0187     const struct ahci_mvebu_plat_data *pdata;
0188     struct ahci_host_priv *hpriv;
0189     int rc;
0190
0191     pdata = of_device_get_match_data(&pdev->dev);
0192     if (!pdata)
0193         return -EINVAL;
0194
0195     hpriv = ahci_platform_get_resources(pdev, 0);
0196     if (IS_ERR(hpriv))
0197         return PTR_ERR(hpriv);
0198
0199     hpriv->flags |= pdata->flags;
0200     hpriv->plat_data = (void *)pdata;
0201
0202     rc = ahci_platform_enable_resources(hpriv);
0203     if (rc)
0204         return rc;
0205
0206     hpriv->stop_engine = ahci_mvebu_stop_engine;
0207
0208     rc = pdata->plat_config(hpriv);
0209     if (rc)
0210         goto disable_resources;
0211
0212     rc = ahci_platform_init_host(pdev, hpriv, &ahci_mvebu_port_info,
0213                      &ahci_platform_sht);
0214     if (rc)
0215         goto disable_resources;
0216
0217     return 0;
0218
0219 disable_resources:
0220     ahci_platform_disable_resources(hpriv);
0221     return rc;
0222 }
0223
0224 static const struct ahci_mvebu_plat_data ahci_mvebu_armada_380_plat_data = {
0225     .plat_config = ahci_mvebu_armada_380_config,
0226 };
0227
0228 static const struct ahci_mvebu_plat_data ahci_mvebu_armada_3700_plat_data = {
0229     .plat_config = ahci_mvebu_armada_3700_config,
0230     .flags = AHCI_HFLAG_SUSPEND_PHYS,
0231 };
0232
0233 static const struct of_device_id ahci_mvebu_of_match[] = {
0234     {
0235         .compatible = "marvell,armada-380-ahci",
0236         .data = &ahci_mvebu_armada_380_plat_data,
0237     },
0238     {
0239         .compatible = "marvell,armada-3700-ahci",
0240         .data = &ahci_mvebu_armada_3700_plat_data,
0241     },
0242     { /* sentinel */ }
0243 };
0244 MODULE_DEVICE_TABLE(of, ahci_mvebu_of_match);
0245
0246 static struct platform_driver ahci_mvebu_driver = {
0247     .probe = ahci_mvebu_probe,
0248     .remove = ata_platform_remove_one,
0249     .suspend = ahci_mvebu_suspend,
0250     .resume = ahci_mvebu_resume,
0251     .driver = {
0252         .name = DRV_NAME,
0253         .of_match_table = ahci_mvebu_of_match,
0254     },
0255 };
0256 module_platform_driver(ahci_mvebu_driver);
0257
0258 MODULE_DESCRIPTION("Marvell EBU AHCI SATA driver");
0259 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>, Marcin Wojtas <mw@semihalf.com>");
0260 MODULE_LICENSE("GPL");
0261 MODULE_ALIAS("platform:ahci_mvebu");