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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * copyright (c) 2013 Freescale Semiconductor, Inc.
0004  * Freescale IMX AHCI SATA platform driver
0005  *
0006  * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
0007  */
0008 
0009 #include <linux/kernel.h>
0010 #include <linux/module.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/regmap.h>
0013 #include <linux/ahci_platform.h>
0014 #include <linux/gpio/consumer.h>
0015 #include <linux/of_device.h>
0016 #include <linux/mfd/syscon.h>
0017 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
0018 #include <linux/libata.h>
0019 #include <linux/hwmon.h>
0020 #include <linux/hwmon-sysfs.h>
0021 #include <linux/thermal.h>
0022 #include "ahci.h"
0023 
0024 #define DRV_NAME "ahci-imx"
0025 
0026 enum {
0027     /* Timer 1-ms Register */
0028     IMX_TIMER1MS                = 0x00e0,
0029     /* Port0 PHY Control Register */
0030     IMX_P0PHYCR             = 0x0178,
0031     IMX_P0PHYCR_TEST_PDDQ           = 1 << 20,
0032     IMX_P0PHYCR_CR_READ         = 1 << 19,
0033     IMX_P0PHYCR_CR_WRITE            = 1 << 18,
0034     IMX_P0PHYCR_CR_CAP_DATA         = 1 << 17,
0035     IMX_P0PHYCR_CR_CAP_ADDR         = 1 << 16,
0036     /* Port0 PHY Status Register */
0037     IMX_P0PHYSR             = 0x017c,
0038     IMX_P0PHYSR_CR_ACK          = 1 << 18,
0039     IMX_P0PHYSR_CR_DATA_OUT         = 0xffff << 0,
0040     /* Lane0 Output Status Register */
0041     IMX_LANE0_OUT_STAT          = 0x2003,
0042     IMX_LANE0_OUT_STAT_RX_PLL_STATE     = 1 << 1,
0043     /* Clock Reset Register */
0044     IMX_CLOCK_RESET             = 0x7f3f,
0045     IMX_CLOCK_RESET_RESET           = 1 << 0,
0046     /* IMX8QM HSIO AHCI definitions */
0047     IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET   = 0x03,
0048     IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET   = 0x09,
0049     IMX8QM_SATA_PHY_IMPED_RATIO_85OHM   = 0x6c,
0050     IMX8QM_LPCG_PHYX2_OFFSET        = 0x00000,
0051     IMX8QM_CSR_PHYX2_OFFSET         = 0x90000,
0052     IMX8QM_CSR_PHYX1_OFFSET         = 0xa0000,
0053     IMX8QM_CSR_PHYX_STTS0_OFFSET        = 0x4,
0054     IMX8QM_CSR_PCIEA_OFFSET         = 0xb0000,
0055     IMX8QM_CSR_PCIEB_OFFSET         = 0xc0000,
0056     IMX8QM_CSR_SATA_OFFSET          = 0xd0000,
0057     IMX8QM_CSR_PCIE_CTRL2_OFFSET        = 0x8,
0058     IMX8QM_CSR_MISC_OFFSET          = 0xe0000,
0059 
0060     IMX8QM_LPCG_PHYX2_PCLK0_MASK        = (0x3 << 16),
0061     IMX8QM_LPCG_PHYX2_PCLK1_MASK        = (0x3 << 20),
0062     IMX8QM_PHY_APB_RSTN_0           = BIT(0),
0063     IMX8QM_PHY_MODE_SATA            = BIT(19),
0064     IMX8QM_PHY_MODE_MASK            = (0xf << 17),
0065     IMX8QM_PHY_PIPE_RSTN_0          = BIT(24),
0066     IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0     = BIT(25),
0067     IMX8QM_PHY_PIPE_RSTN_1          = BIT(26),
0068     IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1     = BIT(27),
0069     IMX8QM_STTS0_LANE0_TX_PLL_LOCK      = BIT(4),
0070     IMX8QM_MISC_IOB_RXENA           = BIT(0),
0071     IMX8QM_MISC_IOB_TXENA           = BIT(1),
0072     IMX8QM_MISC_PHYX1_EPCS_SEL      = BIT(12),
0073     IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1  = BIT(24),
0074     IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0  = BIT(25),
0075     IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1   = BIT(28),
0076     IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0   = BIT(29),
0077     IMX8QM_SATA_CTRL_RESET_N        = BIT(12),
0078     IMX8QM_SATA_CTRL_EPCS_PHYRESET_N    = BIT(7),
0079     IMX8QM_CTRL_BUTTON_RST_N        = BIT(21),
0080     IMX8QM_CTRL_POWER_UP_RST_N      = BIT(23),
0081     IMX8QM_CTRL_LTSSM_ENABLE        = BIT(4),
0082 };
0083 
0084 enum ahci_imx_type {
0085     AHCI_IMX53,
0086     AHCI_IMX6Q,
0087     AHCI_IMX6QP,
0088     AHCI_IMX8QM,
0089 };
0090 
0091 struct imx_ahci_priv {
0092     struct platform_device *ahci_pdev;
0093     enum ahci_imx_type type;
0094     struct clk *sata_clk;
0095     struct clk *sata_ref_clk;
0096     struct clk *ahb_clk;
0097     struct clk *epcs_tx_clk;
0098     struct clk *epcs_rx_clk;
0099     struct clk *phy_apbclk;
0100     struct clk *phy_pclk0;
0101     struct clk *phy_pclk1;
0102     void __iomem *phy_base;
0103     struct gpio_desc *clkreq_gpiod;
0104     struct regmap *gpr;
0105     bool no_device;
0106     bool first_time;
0107     u32 phy_params;
0108     u32 imped_ratio;
0109 };
0110 
0111 static int ahci_imx_hotplug;
0112 module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
0113 MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
0114 
0115 static void ahci_imx_host_stop(struct ata_host *host);
0116 
0117 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert)
0118 {
0119     int timeout = 10;
0120     u32 crval;
0121     u32 srval;
0122 
0123     /* Assert or deassert the bit */
0124     crval = readl(mmio + IMX_P0PHYCR);
0125     if (assert)
0126         crval |= bit;
0127     else
0128         crval &= ~bit;
0129     writel(crval, mmio + IMX_P0PHYCR);
0130 
0131     /* Wait for the cr_ack signal */
0132     do {
0133         srval = readl(mmio + IMX_P0PHYSR);
0134         if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK)
0135             break;
0136         usleep_range(100, 200);
0137     } while (--timeout);
0138 
0139     return timeout ? 0 : -ETIMEDOUT;
0140 }
0141 
0142 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio)
0143 {
0144     u32 crval = addr;
0145     int ret;
0146 
0147     /* Supply the address on cr_data_in */
0148     writel(crval, mmio + IMX_P0PHYCR);
0149 
0150     /* Assert the cr_cap_addr signal */
0151     ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true);
0152     if (ret)
0153         return ret;
0154 
0155     /* Deassert cr_cap_addr */
0156     ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false);
0157     if (ret)
0158         return ret;
0159 
0160     return 0;
0161 }
0162 
0163 static int imx_phy_reg_write(u16 val, void __iomem *mmio)
0164 {
0165     u32 crval = val;
0166     int ret;
0167 
0168     /* Supply the data on cr_data_in */
0169     writel(crval, mmio + IMX_P0PHYCR);
0170 
0171     /* Assert the cr_cap_data signal */
0172     ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true);
0173     if (ret)
0174         return ret;
0175 
0176     /* Deassert cr_cap_data */
0177     ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false);
0178     if (ret)
0179         return ret;
0180 
0181     if (val & IMX_CLOCK_RESET_RESET) {
0182         /*
0183          * In case we're resetting the phy, it's unable to acknowledge,
0184          * so we return immediately here.
0185          */
0186         crval |= IMX_P0PHYCR_CR_WRITE;
0187         writel(crval, mmio + IMX_P0PHYCR);
0188         goto out;
0189     }
0190 
0191     /* Assert the cr_write signal */
0192     ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true);
0193     if (ret)
0194         return ret;
0195 
0196     /* Deassert cr_write */
0197     ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false);
0198     if (ret)
0199         return ret;
0200 
0201 out:
0202     return 0;
0203 }
0204 
0205 static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
0206 {
0207     int ret;
0208 
0209     /* Assert the cr_read signal */
0210     ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true);
0211     if (ret)
0212         return ret;
0213 
0214     /* Capture the data from cr_data_out[] */
0215     *val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT;
0216 
0217     /* Deassert cr_read */
0218     ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false);
0219     if (ret)
0220         return ret;
0221 
0222     return 0;
0223 }
0224 
0225 static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
0226 {
0227     struct imx_ahci_priv *imxpriv = hpriv->plat_data;
0228     void __iomem *mmio = hpriv->mmio;
0229     int timeout = 10;
0230     u16 val;
0231     int ret;
0232 
0233     if (imxpriv->type == AHCI_IMX6QP) {
0234         /* 6qp adds the sata reset mechanism, use it for 6qp sata */
0235         regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
0236                    IMX6Q_GPR5_SATA_SW_PD, 0);
0237 
0238         regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
0239                    IMX6Q_GPR5_SATA_SW_RST, 0);
0240         udelay(50);
0241         regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
0242                    IMX6Q_GPR5_SATA_SW_RST,
0243                    IMX6Q_GPR5_SATA_SW_RST);
0244         return 0;
0245     }
0246 
0247     /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
0248     ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
0249     if (ret)
0250         return ret;
0251     ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio);
0252     if (ret)
0253         return ret;
0254 
0255     /* Wait for PHY RX_PLL to be stable */
0256     do {
0257         usleep_range(100, 200);
0258         ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio);
0259         if (ret)
0260             return ret;
0261         ret = imx_phy_reg_read(&val, mmio);
0262         if (ret)
0263             return ret;
0264         if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE)
0265             break;
0266     } while (--timeout);
0267 
0268     return timeout ? 0 : -ETIMEDOUT;
0269 }
0270 
0271 enum {
0272     /* SATA PHY Register */
0273     SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT = 0x0001,
0274     SATA_PHY_CR_CLOCK_DAC_CTL = 0x0008,
0275     SATA_PHY_CR_CLOCK_RTUNE_CTL = 0x0009,
0276     SATA_PHY_CR_CLOCK_ADC_OUT = 0x000A,
0277     SATA_PHY_CR_CLOCK_MPLL_TST = 0x0017,
0278 };
0279 
0280 static int read_adc_sum(void *dev, u16 rtune_ctl_reg, void __iomem * mmio)
0281 {
0282     u16 adc_out_reg, read_sum;
0283     u32 index, read_attempt;
0284     const u32 attempt_limit = 200;
0285 
0286     imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
0287     imx_phy_reg_write(rtune_ctl_reg, mmio);
0288 
0289     /* two dummy read */
0290     index = 0;
0291     read_attempt = 0;
0292     adc_out_reg = 0;
0293     imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_ADC_OUT, mmio);
0294     while (index < 2) {
0295         imx_phy_reg_read(&adc_out_reg, mmio);
0296         /* check if valid */
0297         if (adc_out_reg & 0x400)
0298             index++;
0299 
0300         read_attempt++;
0301         if (read_attempt > attempt_limit) {
0302             dev_err(dev, "Read REG more than %d times!\n",
0303                 attempt_limit);
0304             break;
0305         }
0306     }
0307 
0308     index = 0;
0309     read_attempt = 0;
0310     read_sum = 0;
0311     while (index < 80) {
0312         imx_phy_reg_read(&adc_out_reg, mmio);
0313         if (adc_out_reg & 0x400) {
0314             read_sum = read_sum + (adc_out_reg & 0x3FF);
0315             index++;
0316         }
0317         read_attempt++;
0318         if (read_attempt > attempt_limit) {
0319             dev_err(dev, "Read REG more than %d times!\n",
0320                 attempt_limit);
0321             break;
0322         }
0323     }
0324 
0325     /* Use the U32 to make 1000 precision */
0326     return (read_sum * 1000) / 80;
0327 }
0328 
0329 /* SATA AHCI temperature monitor */
0330 static int sata_ahci_read_temperature(void *dev, int *temp)
0331 {
0332     u16 mpll_test_reg, rtune_ctl_reg, dac_ctl_reg, read_sum;
0333     u32 str1, str2, str3, str4;
0334     int m1, m2, a;
0335     struct ahci_host_priv *hpriv = dev_get_drvdata(dev);
0336     void __iomem *mmio = hpriv->mmio;
0337 
0338     /* check rd-wr to reg */
0339     read_sum = 0;
0340     imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_CRCMP_LT_LIMIT, mmio);
0341     imx_phy_reg_write(read_sum, mmio);
0342     imx_phy_reg_read(&read_sum, mmio);
0343     if ((read_sum & 0xffff) != 0)
0344         dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
0345 
0346     imx_phy_reg_write(0x5A5A, mmio);
0347     imx_phy_reg_read(&read_sum, mmio);
0348     if ((read_sum & 0xffff) != 0x5A5A)
0349         dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
0350 
0351     imx_phy_reg_write(0x1234, mmio);
0352     imx_phy_reg_read(&read_sum, mmio);
0353     if ((read_sum & 0xffff) != 0x1234)
0354         dev_err(dev, "Read/Write REG error, 0x%x!\n", read_sum);
0355 
0356     /* start temperature test */
0357     imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
0358     imx_phy_reg_read(&mpll_test_reg, mmio);
0359     imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
0360     imx_phy_reg_read(&rtune_ctl_reg, mmio);
0361     imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
0362     imx_phy_reg_read(&dac_ctl_reg, mmio);
0363 
0364     /* mpll_tst.meas_iv   ([12:2]) */
0365     str1 = (mpll_test_reg >> 2) & 0x7FF;
0366     /* rtune_ctl.mode     ([1:0]) */
0367     str2 = (rtune_ctl_reg) & 0x3;
0368     /* dac_ctl.dac_mode   ([14:12]) */
0369     str3 = (dac_ctl_reg >> 12)  & 0x7;
0370     /* rtune_ctl.sel_atbp ([4]) */
0371     str4 = (rtune_ctl_reg >> 4);
0372 
0373     /* Calculate the m1 */
0374     /* mpll_tst.meas_iv */
0375     mpll_test_reg = (mpll_test_reg & 0xE03) | (512) << 2;
0376     /* rtune_ctl.mode */
0377     rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (1);
0378     /* dac_ctl.dac_mode */
0379     dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (4) << 12;
0380     /* rtune_ctl.sel_atbp */
0381     rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (0) << 4;
0382     imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
0383     imx_phy_reg_write(mpll_test_reg, mmio);
0384     imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
0385     imx_phy_reg_write(dac_ctl_reg, mmio);
0386     m1 = read_adc_sum(dev, rtune_ctl_reg, mmio);
0387 
0388     /* Calculate the m2 */
0389     /* rtune_ctl.sel_atbp */
0390     rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (1) << 4;
0391     m2 = read_adc_sum(dev, rtune_ctl_reg, mmio);
0392 
0393     /* restore the status  */
0394     /* mpll_tst.meas_iv */
0395     mpll_test_reg = (mpll_test_reg & 0xE03) | (str1) << 2;
0396     /* rtune_ctl.mode */
0397     rtune_ctl_reg = (rtune_ctl_reg & 0xFFC) | (str2);
0398     /* dac_ctl.dac_mode */
0399     dac_ctl_reg = (dac_ctl_reg & 0x8FF) | (str3) << 12;
0400     /* rtune_ctl.sel_atbp */
0401     rtune_ctl_reg = (rtune_ctl_reg & 0xFEF) | (str4) << 4;
0402 
0403     imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_MPLL_TST, mmio);
0404     imx_phy_reg_write(mpll_test_reg, mmio);
0405     imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_DAC_CTL, mmio);
0406     imx_phy_reg_write(dac_ctl_reg, mmio);
0407     imx_phy_reg_addressing(SATA_PHY_CR_CLOCK_RTUNE_CTL, mmio);
0408     imx_phy_reg_write(rtune_ctl_reg, mmio);
0409 
0410     /* Compute temperature */
0411     if (!(m2 / 1000))
0412         m2 = 1000;
0413     a = (m2 - m1) / (m2/1000);
0414     *temp = ((-559) * a * a) / 1000 + (1379) * a + (-458000);
0415 
0416     return 0;
0417 }
0418 
0419 static ssize_t sata_ahci_show_temp(struct device *dev,
0420                    struct device_attribute *da,
0421                    char *buf)
0422 {
0423     unsigned int temp = 0;
0424     int err;
0425 
0426     err = sata_ahci_read_temperature(dev, &temp);
0427     if (err < 0)
0428         return err;
0429 
0430     return sprintf(buf, "%u\n", temp);
0431 }
0432 
0433 static const struct thermal_zone_of_device_ops fsl_sata_ahci_of_thermal_ops = {
0434     .get_temp = sata_ahci_read_temperature,
0435 };
0436 
0437 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, sata_ahci_show_temp, NULL, 0);
0438 
0439 static struct attribute *fsl_sata_ahci_attrs[] = {
0440     &sensor_dev_attr_temp1_input.dev_attr.attr,
0441     NULL
0442 };
0443 ATTRIBUTE_GROUPS(fsl_sata_ahci);
0444 
0445 static int imx8_sata_enable(struct ahci_host_priv *hpriv)
0446 {
0447     u32 val, reg;
0448     int i, ret;
0449     struct imx_ahci_priv *imxpriv = hpriv->plat_data;
0450     struct device *dev = &imxpriv->ahci_pdev->dev;
0451 
0452     /* configure the hsio for sata */
0453     ret = clk_prepare_enable(imxpriv->phy_pclk0);
0454     if (ret < 0) {
0455         dev_err(dev, "can't enable phy_pclk0.\n");
0456         return ret;
0457     }
0458     ret = clk_prepare_enable(imxpriv->phy_pclk1);
0459     if (ret < 0) {
0460         dev_err(dev, "can't enable phy_pclk1.\n");
0461         goto disable_phy_pclk0;
0462     }
0463     ret = clk_prepare_enable(imxpriv->epcs_tx_clk);
0464     if (ret < 0) {
0465         dev_err(dev, "can't enable epcs_tx_clk.\n");
0466         goto disable_phy_pclk1;
0467     }
0468     ret = clk_prepare_enable(imxpriv->epcs_rx_clk);
0469     if (ret < 0) {
0470         dev_err(dev, "can't enable epcs_rx_clk.\n");
0471         goto disable_epcs_tx_clk;
0472     }
0473     ret = clk_prepare_enable(imxpriv->phy_apbclk);
0474     if (ret < 0) {
0475         dev_err(dev, "can't enable phy_apbclk.\n");
0476         goto disable_epcs_rx_clk;
0477     }
0478     /* Configure PHYx2 PIPE_RSTN */
0479     regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET +
0480             IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val);
0481     if ((val & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
0482         /* The link of the PCIEA of HSIO is down */
0483         regmap_update_bits(imxpriv->gpr,
0484                 IMX8QM_CSR_PHYX2_OFFSET,
0485                 IMX8QM_PHY_PIPE_RSTN_0 |
0486                 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0,
0487                 IMX8QM_PHY_PIPE_RSTN_0 |
0488                 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0);
0489     }
0490     regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEB_OFFSET +
0491             IMX8QM_CSR_PCIE_CTRL2_OFFSET, &reg);
0492     if ((reg & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
0493         /* The link of the PCIEB of HSIO is down */
0494         regmap_update_bits(imxpriv->gpr,
0495                 IMX8QM_CSR_PHYX2_OFFSET,
0496                 IMX8QM_PHY_PIPE_RSTN_1 |
0497                 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1,
0498                 IMX8QM_PHY_PIPE_RSTN_1 |
0499                 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1);
0500     }
0501     if (((reg | val) & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
0502         /* The links of both PCIA and PCIEB of HSIO are down */
0503         regmap_update_bits(imxpriv->gpr,
0504                 IMX8QM_LPCG_PHYX2_OFFSET,
0505                 IMX8QM_LPCG_PHYX2_PCLK0_MASK |
0506                 IMX8QM_LPCG_PHYX2_PCLK1_MASK,
0507                 0);
0508     }
0509 
0510     /* set PWR_RST and BT_RST of csr_pciea */
0511     val = IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET;
0512     regmap_update_bits(imxpriv->gpr,
0513             val,
0514             IMX8QM_CTRL_BUTTON_RST_N,
0515             IMX8QM_CTRL_BUTTON_RST_N);
0516     regmap_update_bits(imxpriv->gpr,
0517             val,
0518             IMX8QM_CTRL_POWER_UP_RST_N,
0519             IMX8QM_CTRL_POWER_UP_RST_N);
0520 
0521     /* PHYX1_MODE to SATA */
0522     regmap_update_bits(imxpriv->gpr,
0523             IMX8QM_CSR_PHYX1_OFFSET,
0524             IMX8QM_PHY_MODE_MASK,
0525             IMX8QM_PHY_MODE_SATA);
0526 
0527     /*
0528      * BIT0 RXENA 1, BIT1 TXENA 0
0529      * BIT12 PHY_X1_EPCS_SEL 1.
0530      */
0531     regmap_update_bits(imxpriv->gpr,
0532             IMX8QM_CSR_MISC_OFFSET,
0533             IMX8QM_MISC_IOB_RXENA,
0534             IMX8QM_MISC_IOB_RXENA);
0535     regmap_update_bits(imxpriv->gpr,
0536             IMX8QM_CSR_MISC_OFFSET,
0537             IMX8QM_MISC_IOB_TXENA,
0538             0);
0539     regmap_update_bits(imxpriv->gpr,
0540             IMX8QM_CSR_MISC_OFFSET,
0541             IMX8QM_MISC_PHYX1_EPCS_SEL,
0542             IMX8QM_MISC_PHYX1_EPCS_SEL);
0543     /*
0544      * It is possible, for PCIe and SATA are sharing
0545      * the same clock source, HPLL or external oscillator.
0546      * When PCIe is in low power modes (L1.X or L2 etc),
0547      * the clock source can be turned off. In this case,
0548      * if this clock source is required to be toggling by
0549      * SATA, then SATA functions will be abnormal.
0550      * Set the override here to avoid it.
0551      */
0552     regmap_update_bits(imxpriv->gpr,
0553             IMX8QM_CSR_MISC_OFFSET,
0554             IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
0555             IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
0556             IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
0557             IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0,
0558             IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
0559             IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
0560             IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
0561             IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0);
0562 
0563     /* clear PHY RST, then set it */
0564     regmap_update_bits(imxpriv->gpr,
0565             IMX8QM_CSR_SATA_OFFSET,
0566             IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
0567             0);
0568 
0569     regmap_update_bits(imxpriv->gpr,
0570             IMX8QM_CSR_SATA_OFFSET,
0571             IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
0572             IMX8QM_SATA_CTRL_EPCS_PHYRESET_N);
0573 
0574     /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
0575     regmap_update_bits(imxpriv->gpr,
0576             IMX8QM_CSR_SATA_OFFSET,
0577             IMX8QM_SATA_CTRL_RESET_N,
0578             IMX8QM_SATA_CTRL_RESET_N);
0579     udelay(1);
0580     regmap_update_bits(imxpriv->gpr,
0581             IMX8QM_CSR_SATA_OFFSET,
0582             IMX8QM_SATA_CTRL_RESET_N,
0583             0);
0584     regmap_update_bits(imxpriv->gpr,
0585             IMX8QM_CSR_SATA_OFFSET,
0586             IMX8QM_SATA_CTRL_RESET_N,
0587             IMX8QM_SATA_CTRL_RESET_N);
0588 
0589     /* APB reset */
0590     regmap_update_bits(imxpriv->gpr,
0591             IMX8QM_CSR_PHYX1_OFFSET,
0592             IMX8QM_PHY_APB_RSTN_0,
0593             IMX8QM_PHY_APB_RSTN_0);
0594 
0595     for (i = 0; i < 100; i++) {
0596         reg = IMX8QM_CSR_PHYX1_OFFSET +
0597             IMX8QM_CSR_PHYX_STTS0_OFFSET;
0598         regmap_read(imxpriv->gpr, reg, &val);
0599         val &= IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
0600         if (val == IMX8QM_STTS0_LANE0_TX_PLL_LOCK)
0601             break;
0602         udelay(1);
0603     }
0604 
0605     if (val != IMX8QM_STTS0_LANE0_TX_PLL_LOCK) {
0606         dev_err(dev, "TX PLL of the PHY is not locked\n");
0607         ret = -ENODEV;
0608     } else {
0609         writeb(imxpriv->imped_ratio, imxpriv->phy_base +
0610                 IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
0611         writeb(imxpriv->imped_ratio, imxpriv->phy_base +
0612                 IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
0613         reg = readb(imxpriv->phy_base +
0614                 IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
0615         if (unlikely(reg != imxpriv->imped_ratio))
0616             dev_info(dev, "Can't set PHY RX impedance ratio.\n");
0617         reg = readb(imxpriv->phy_base +
0618                 IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
0619         if (unlikely(reg != imxpriv->imped_ratio))
0620             dev_info(dev, "Can't set PHY TX impedance ratio.\n");
0621         usleep_range(50, 100);
0622 
0623         /*
0624          * To reduce the power consumption, gate off
0625          * the PHY clks
0626          */
0627         clk_disable_unprepare(imxpriv->phy_apbclk);
0628         clk_disable_unprepare(imxpriv->phy_pclk1);
0629         clk_disable_unprepare(imxpriv->phy_pclk0);
0630         return ret;
0631     }
0632 
0633     clk_disable_unprepare(imxpriv->phy_apbclk);
0634 disable_epcs_rx_clk:
0635     clk_disable_unprepare(imxpriv->epcs_rx_clk);
0636 disable_epcs_tx_clk:
0637     clk_disable_unprepare(imxpriv->epcs_tx_clk);
0638 disable_phy_pclk1:
0639     clk_disable_unprepare(imxpriv->phy_pclk1);
0640 disable_phy_pclk0:
0641     clk_disable_unprepare(imxpriv->phy_pclk0);
0642 
0643     return ret;
0644 }
0645 
0646 static int imx_sata_enable(struct ahci_host_priv *hpriv)
0647 {
0648     struct imx_ahci_priv *imxpriv = hpriv->plat_data;
0649     struct device *dev = &imxpriv->ahci_pdev->dev;
0650     int ret;
0651 
0652     if (imxpriv->no_device)
0653         return 0;
0654 
0655     ret = ahci_platform_enable_regulators(hpriv);
0656     if (ret)
0657         return ret;
0658 
0659     ret = clk_prepare_enable(imxpriv->sata_ref_clk);
0660     if (ret < 0)
0661         goto disable_regulator;
0662 
0663     if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
0664         /*
0665          * set PHY Paremeters, two steps to configure the GPR13,
0666          * one write for rest of parameters, mask of first write
0667          * is 0x07ffffff, and the other one write for setting
0668          * the mpll_clk_en.
0669          */
0670         regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
0671                    IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
0672                    IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
0673                    IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
0674                    IMX6Q_GPR13_SATA_SPD_MODE_MASK |
0675                    IMX6Q_GPR13_SATA_MPLL_SS_EN |
0676                    IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
0677                    IMX6Q_GPR13_SATA_TX_BOOST_MASK |
0678                    IMX6Q_GPR13_SATA_TX_LVL_MASK |
0679                    IMX6Q_GPR13_SATA_MPLL_CLK_EN |
0680                    IMX6Q_GPR13_SATA_TX_EDGE_RATE,
0681                    imxpriv->phy_params);
0682         regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
0683                    IMX6Q_GPR13_SATA_MPLL_CLK_EN,
0684                    IMX6Q_GPR13_SATA_MPLL_CLK_EN);
0685 
0686         usleep_range(100, 200);
0687 
0688         ret = imx_sata_phy_reset(hpriv);
0689         if (ret) {
0690             dev_err(dev, "failed to reset phy: %d\n", ret);
0691             goto disable_clk;
0692         }
0693     } else if (imxpriv->type == AHCI_IMX8QM) {
0694         ret = imx8_sata_enable(hpriv);
0695     }
0696 
0697     usleep_range(1000, 2000);
0698 
0699     return 0;
0700 
0701 disable_clk:
0702     clk_disable_unprepare(imxpriv->sata_ref_clk);
0703 disable_regulator:
0704     ahci_platform_disable_regulators(hpriv);
0705 
0706     return ret;
0707 }
0708 
0709 static void imx_sata_disable(struct ahci_host_priv *hpriv)
0710 {
0711     struct imx_ahci_priv *imxpriv = hpriv->plat_data;
0712 
0713     if (imxpriv->no_device)
0714         return;
0715 
0716     switch (imxpriv->type) {
0717     case AHCI_IMX6QP:
0718         regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
0719                    IMX6Q_GPR5_SATA_SW_PD,
0720                    IMX6Q_GPR5_SATA_SW_PD);
0721         regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
0722                    IMX6Q_GPR13_SATA_MPLL_CLK_EN,
0723                    !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
0724         break;
0725 
0726     case AHCI_IMX6Q:
0727         regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
0728                    IMX6Q_GPR13_SATA_MPLL_CLK_EN,
0729                    !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
0730         break;
0731 
0732     case AHCI_IMX8QM:
0733         clk_disable_unprepare(imxpriv->epcs_rx_clk);
0734         clk_disable_unprepare(imxpriv->epcs_tx_clk);
0735         break;
0736 
0737     default:
0738         break;
0739     }
0740 
0741     clk_disable_unprepare(imxpriv->sata_ref_clk);
0742 
0743     ahci_platform_disable_regulators(hpriv);
0744 }
0745 
0746 static void ahci_imx_error_handler(struct ata_port *ap)
0747 {
0748     u32 reg_val;
0749     struct ata_device *dev;
0750     struct ata_host *host = dev_get_drvdata(ap->dev);
0751     struct ahci_host_priv *hpriv = host->private_data;
0752     void __iomem *mmio = hpriv->mmio;
0753     struct imx_ahci_priv *imxpriv = hpriv->plat_data;
0754 
0755     ahci_error_handler(ap);
0756 
0757     if (!(imxpriv->first_time) || ahci_imx_hotplug)
0758         return;
0759 
0760     imxpriv->first_time = false;
0761 
0762     ata_for_each_dev(dev, &ap->link, ENABLED)
0763         return;
0764     /*
0765      * Disable link to save power.  An imx ahci port can't be recovered
0766      * without full reset once the pddq mode is enabled making it
0767      * impossible to use as part of libata LPM.
0768      */
0769     reg_val = readl(mmio + IMX_P0PHYCR);
0770     writel(reg_val | IMX_P0PHYCR_TEST_PDDQ, mmio + IMX_P0PHYCR);
0771     imx_sata_disable(hpriv);
0772     imxpriv->no_device = true;
0773 
0774     dev_info(ap->dev, "no device found, disabling link.\n");
0775     dev_info(ap->dev, "pass " MODULE_PARAM_PREFIX ".hotplug=1 to enable hotplug\n");
0776 }
0777 
0778 static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
0779                unsigned long deadline)
0780 {
0781     struct ata_port *ap = link->ap;
0782     struct ata_host *host = dev_get_drvdata(ap->dev);
0783     struct ahci_host_priv *hpriv = host->private_data;
0784     struct imx_ahci_priv *imxpriv = hpriv->plat_data;
0785     int ret;
0786 
0787     if (imxpriv->type == AHCI_IMX53)
0788         ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
0789     else
0790         ret = ahci_ops.softreset(link, class, deadline);
0791 
0792     return ret;
0793 }
0794 
0795 static struct ata_port_operations ahci_imx_ops = {
0796     .inherits   = &ahci_ops,
0797     .host_stop  = ahci_imx_host_stop,
0798     .error_handler  = ahci_imx_error_handler,
0799     .softreset  = ahci_imx_softreset,
0800 };
0801 
0802 static const struct ata_port_info ahci_imx_port_info = {
0803     .flags      = AHCI_FLAG_COMMON,
0804     .pio_mask   = ATA_PIO4,
0805     .udma_mask  = ATA_UDMA6,
0806     .port_ops   = &ahci_imx_ops,
0807 };
0808 
0809 static const struct of_device_id imx_ahci_of_match[] = {
0810     { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
0811     { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
0812     { .compatible = "fsl,imx6qp-ahci", .data = (void *)AHCI_IMX6QP },
0813     { .compatible = "fsl,imx8qm-ahci", .data = (void *)AHCI_IMX8QM },
0814     { /* sentinel */ }
0815 };
0816 MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
0817 
0818 struct reg_value {
0819     u32 of_value;
0820     u32 reg_value;
0821 };
0822 
0823 struct reg_property {
0824     const char *name;
0825     const struct reg_value *values;
0826     size_t num_values;
0827     u32 def_value;
0828     u32 set_value;
0829 };
0830 
0831 static const struct reg_value gpr13_tx_level[] = {
0832     {  937, IMX6Q_GPR13_SATA_TX_LVL_0_937_V },
0833     {  947, IMX6Q_GPR13_SATA_TX_LVL_0_947_V },
0834     {  957, IMX6Q_GPR13_SATA_TX_LVL_0_957_V },
0835     {  966, IMX6Q_GPR13_SATA_TX_LVL_0_966_V },
0836     {  976, IMX6Q_GPR13_SATA_TX_LVL_0_976_V },
0837     {  986, IMX6Q_GPR13_SATA_TX_LVL_0_986_V },
0838     {  996, IMX6Q_GPR13_SATA_TX_LVL_0_996_V },
0839     { 1005, IMX6Q_GPR13_SATA_TX_LVL_1_005_V },
0840     { 1015, IMX6Q_GPR13_SATA_TX_LVL_1_015_V },
0841     { 1025, IMX6Q_GPR13_SATA_TX_LVL_1_025_V },
0842     { 1035, IMX6Q_GPR13_SATA_TX_LVL_1_035_V },
0843     { 1045, IMX6Q_GPR13_SATA_TX_LVL_1_045_V },
0844     { 1054, IMX6Q_GPR13_SATA_TX_LVL_1_054_V },
0845     { 1064, IMX6Q_GPR13_SATA_TX_LVL_1_064_V },
0846     { 1074, IMX6Q_GPR13_SATA_TX_LVL_1_074_V },
0847     { 1084, IMX6Q_GPR13_SATA_TX_LVL_1_084_V },
0848     { 1094, IMX6Q_GPR13_SATA_TX_LVL_1_094_V },
0849     { 1104, IMX6Q_GPR13_SATA_TX_LVL_1_104_V },
0850     { 1113, IMX6Q_GPR13_SATA_TX_LVL_1_113_V },
0851     { 1123, IMX6Q_GPR13_SATA_TX_LVL_1_123_V },
0852     { 1133, IMX6Q_GPR13_SATA_TX_LVL_1_133_V },
0853     { 1143, IMX6Q_GPR13_SATA_TX_LVL_1_143_V },
0854     { 1152, IMX6Q_GPR13_SATA_TX_LVL_1_152_V },
0855     { 1162, IMX6Q_GPR13_SATA_TX_LVL_1_162_V },
0856     { 1172, IMX6Q_GPR13_SATA_TX_LVL_1_172_V },
0857     { 1182, IMX6Q_GPR13_SATA_TX_LVL_1_182_V },
0858     { 1191, IMX6Q_GPR13_SATA_TX_LVL_1_191_V },
0859     { 1201, IMX6Q_GPR13_SATA_TX_LVL_1_201_V },
0860     { 1211, IMX6Q_GPR13_SATA_TX_LVL_1_211_V },
0861     { 1221, IMX6Q_GPR13_SATA_TX_LVL_1_221_V },
0862     { 1230, IMX6Q_GPR13_SATA_TX_LVL_1_230_V },
0863     { 1240, IMX6Q_GPR13_SATA_TX_LVL_1_240_V }
0864 };
0865 
0866 static const struct reg_value gpr13_tx_boost[] = {
0867     {    0, IMX6Q_GPR13_SATA_TX_BOOST_0_00_DB },
0868     {  370, IMX6Q_GPR13_SATA_TX_BOOST_0_37_DB },
0869     {  740, IMX6Q_GPR13_SATA_TX_BOOST_0_74_DB },
0870     { 1110, IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB },
0871     { 1480, IMX6Q_GPR13_SATA_TX_BOOST_1_48_DB },
0872     { 1850, IMX6Q_GPR13_SATA_TX_BOOST_1_85_DB },
0873     { 2220, IMX6Q_GPR13_SATA_TX_BOOST_2_22_DB },
0874     { 2590, IMX6Q_GPR13_SATA_TX_BOOST_2_59_DB },
0875     { 2960, IMX6Q_GPR13_SATA_TX_BOOST_2_96_DB },
0876     { 3330, IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB },
0877     { 3700, IMX6Q_GPR13_SATA_TX_BOOST_3_70_DB },
0878     { 4070, IMX6Q_GPR13_SATA_TX_BOOST_4_07_DB },
0879     { 4440, IMX6Q_GPR13_SATA_TX_BOOST_4_44_DB },
0880     { 4810, IMX6Q_GPR13_SATA_TX_BOOST_4_81_DB },
0881     { 5280, IMX6Q_GPR13_SATA_TX_BOOST_5_28_DB },
0882     { 5750, IMX6Q_GPR13_SATA_TX_BOOST_5_75_DB }
0883 };
0884 
0885 static const struct reg_value gpr13_tx_atten[] = {
0886     {  8, IMX6Q_GPR13_SATA_TX_ATTEN_8_16 },
0887     {  9, IMX6Q_GPR13_SATA_TX_ATTEN_9_16 },
0888     { 10, IMX6Q_GPR13_SATA_TX_ATTEN_10_16 },
0889     { 12, IMX6Q_GPR13_SATA_TX_ATTEN_12_16 },
0890     { 14, IMX6Q_GPR13_SATA_TX_ATTEN_14_16 },
0891     { 16, IMX6Q_GPR13_SATA_TX_ATTEN_16_16 },
0892 };
0893 
0894 static const struct reg_value gpr13_rx_eq[] = {
0895     {  500, IMX6Q_GPR13_SATA_RX_EQ_VAL_0_5_DB },
0896     { 1000, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_0_DB },
0897     { 1500, IMX6Q_GPR13_SATA_RX_EQ_VAL_1_5_DB },
0898     { 2000, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB },
0899     { 2500, IMX6Q_GPR13_SATA_RX_EQ_VAL_2_5_DB },
0900     { 3000, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB },
0901     { 3500, IMX6Q_GPR13_SATA_RX_EQ_VAL_3_5_DB },
0902     { 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB },
0903 };
0904 
0905 static const struct reg_property gpr13_props[] = {
0906     {
0907         .name = "fsl,transmit-level-mV",
0908         .values = gpr13_tx_level,
0909         .num_values = ARRAY_SIZE(gpr13_tx_level),
0910         .def_value = IMX6Q_GPR13_SATA_TX_LVL_1_025_V,
0911     }, {
0912         .name = "fsl,transmit-boost-mdB",
0913         .values = gpr13_tx_boost,
0914         .num_values = ARRAY_SIZE(gpr13_tx_boost),
0915         .def_value = IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB,
0916     }, {
0917         .name = "fsl,transmit-atten-16ths",
0918         .values = gpr13_tx_atten,
0919         .num_values = ARRAY_SIZE(gpr13_tx_atten),
0920         .def_value = IMX6Q_GPR13_SATA_TX_ATTEN_9_16,
0921     }, {
0922         .name = "fsl,receive-eq-mdB",
0923         .values = gpr13_rx_eq,
0924         .num_values = ARRAY_SIZE(gpr13_rx_eq),
0925         .def_value = IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB,
0926     }, {
0927         .name = "fsl,no-spread-spectrum",
0928         .def_value = IMX6Q_GPR13_SATA_MPLL_SS_EN,
0929         .set_value = 0,
0930     },
0931 };
0932 
0933 static u32 imx_ahci_parse_props(struct device *dev,
0934                 const struct reg_property *prop, size_t num)
0935 {
0936     struct device_node *np = dev->of_node;
0937     u32 reg_value = 0;
0938     int i, j;
0939 
0940     for (i = 0; i < num; i++, prop++) {
0941         u32 of_val;
0942 
0943         if (prop->num_values == 0) {
0944             if (of_property_read_bool(np, prop->name))
0945                 reg_value |= prop->set_value;
0946             else
0947                 reg_value |= prop->def_value;
0948             continue;
0949         }
0950 
0951         if (of_property_read_u32(np, prop->name, &of_val)) {
0952             dev_info(dev, "%s not specified, using %08x\n",
0953                 prop->name, prop->def_value);
0954             reg_value |= prop->def_value;
0955             continue;
0956         }
0957 
0958         for (j = 0; j < prop->num_values; j++) {
0959             if (prop->values[j].of_value == of_val) {
0960                 dev_info(dev, "%s value %u, using %08x\n",
0961                     prop->name, of_val, prop->values[j].reg_value);
0962                 reg_value |= prop->values[j].reg_value;
0963                 break;
0964             }
0965         }
0966 
0967         if (j == prop->num_values) {
0968             dev_err(dev, "DT property %s is not a valid value\n",
0969                 prop->name);
0970             reg_value |= prop->def_value;
0971         }
0972     }
0973 
0974     return reg_value;
0975 }
0976 
0977 static struct scsi_host_template ahci_platform_sht = {
0978     AHCI_SHT(DRV_NAME),
0979 };
0980 
0981 static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv)
0982 {
0983     struct resource *phy_res;
0984     struct platform_device *pdev = imxpriv->ahci_pdev;
0985     struct device_node *np = dev->of_node;
0986 
0987     if (of_property_read_u32(np, "fsl,phy-imp", &imxpriv->imped_ratio))
0988         imxpriv->imped_ratio = IMX8QM_SATA_PHY_IMPED_RATIO_85OHM;
0989     phy_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
0990     if (phy_res) {
0991         imxpriv->phy_base = devm_ioremap(dev, phy_res->start,
0992                     resource_size(phy_res));
0993         if (!imxpriv->phy_base) {
0994             dev_err(dev, "error with ioremap\n");
0995             return -ENOMEM;
0996         }
0997     } else {
0998         dev_err(dev, "missing *phy* reg region.\n");
0999         return -ENOMEM;
1000     }
1001     imxpriv->gpr =
1002          syscon_regmap_lookup_by_phandle(np, "hsio");
1003     if (IS_ERR(imxpriv->gpr)) {
1004         dev_err(dev, "unable to find gpr registers\n");
1005         return PTR_ERR(imxpriv->gpr);
1006     }
1007 
1008     imxpriv->epcs_tx_clk = devm_clk_get(dev, "epcs_tx");
1009     if (IS_ERR(imxpriv->epcs_tx_clk)) {
1010         dev_err(dev, "can't get epcs_tx_clk clock.\n");
1011         return PTR_ERR(imxpriv->epcs_tx_clk);
1012     }
1013     imxpriv->epcs_rx_clk = devm_clk_get(dev, "epcs_rx");
1014     if (IS_ERR(imxpriv->epcs_rx_clk)) {
1015         dev_err(dev, "can't get epcs_rx_clk clock.\n");
1016         return PTR_ERR(imxpriv->epcs_rx_clk);
1017     }
1018     imxpriv->phy_pclk0 = devm_clk_get(dev, "phy_pclk0");
1019     if (IS_ERR(imxpriv->phy_pclk0)) {
1020         dev_err(dev, "can't get phy_pclk0 clock.\n");
1021         return PTR_ERR(imxpriv->phy_pclk0);
1022     }
1023     imxpriv->phy_pclk1 = devm_clk_get(dev, "phy_pclk1");
1024     if (IS_ERR(imxpriv->phy_pclk1)) {
1025         dev_err(dev, "can't get phy_pclk1 clock.\n");
1026         return PTR_ERR(imxpriv->phy_pclk1);
1027     }
1028     imxpriv->phy_apbclk = devm_clk_get(dev, "phy_apbclk");
1029     if (IS_ERR(imxpriv->phy_apbclk)) {
1030         dev_err(dev, "can't get phy_apbclk clock.\n");
1031         return PTR_ERR(imxpriv->phy_apbclk);
1032     }
1033 
1034     /* Fetch GPIO, then enable the external OSC */
1035     imxpriv->clkreq_gpiod = devm_gpiod_get_optional(dev, "clkreq",
1036                 GPIOD_OUT_LOW | GPIOD_FLAGS_BIT_NONEXCLUSIVE);
1037     if (IS_ERR(imxpriv->clkreq_gpiod))
1038         return PTR_ERR(imxpriv->clkreq_gpiod);
1039     if (imxpriv->clkreq_gpiod)
1040         gpiod_set_consumer_name(imxpriv->clkreq_gpiod, "SATA CLKREQ");
1041 
1042     return 0;
1043 }
1044 
1045 static int imx_ahci_probe(struct platform_device *pdev)
1046 {
1047     struct device *dev = &pdev->dev;
1048     const struct of_device_id *of_id;
1049     struct ahci_host_priv *hpriv;
1050     struct imx_ahci_priv *imxpriv;
1051     unsigned int reg_val;
1052     int ret;
1053 
1054     of_id = of_match_device(imx_ahci_of_match, dev);
1055     if (!of_id)
1056         return -EINVAL;
1057 
1058     imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
1059     if (!imxpriv)
1060         return -ENOMEM;
1061 
1062     imxpriv->ahci_pdev = pdev;
1063     imxpriv->no_device = false;
1064     imxpriv->first_time = true;
1065     imxpriv->type = (enum ahci_imx_type)of_id->data;
1066 
1067     imxpriv->sata_clk = devm_clk_get(dev, "sata");
1068     if (IS_ERR(imxpriv->sata_clk)) {
1069         dev_err(dev, "can't get sata clock.\n");
1070         return PTR_ERR(imxpriv->sata_clk);
1071     }
1072 
1073     imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
1074     if (IS_ERR(imxpriv->sata_ref_clk)) {
1075         dev_err(dev, "can't get sata_ref clock.\n");
1076         return PTR_ERR(imxpriv->sata_ref_clk);
1077     }
1078 
1079     imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
1080     if (IS_ERR(imxpriv->ahb_clk)) {
1081         dev_err(dev, "can't get ahb clock.\n");
1082         return PTR_ERR(imxpriv->ahb_clk);
1083     }
1084 
1085     if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
1086         u32 reg_value;
1087 
1088         imxpriv->gpr = syscon_regmap_lookup_by_compatible(
1089                             "fsl,imx6q-iomuxc-gpr");
1090         if (IS_ERR(imxpriv->gpr)) {
1091             dev_err(dev,
1092                 "failed to find fsl,imx6q-iomux-gpr regmap\n");
1093             return PTR_ERR(imxpriv->gpr);
1094         }
1095 
1096         reg_value = imx_ahci_parse_props(dev, gpr13_props,
1097                          ARRAY_SIZE(gpr13_props));
1098 
1099         imxpriv->phy_params =
1100                    IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
1101                    IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
1102                    IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
1103                    reg_value;
1104     } else if (imxpriv->type == AHCI_IMX8QM) {
1105         ret =  imx8_sata_probe(dev, imxpriv);
1106         if (ret)
1107             return ret;
1108     }
1109 
1110     hpriv = ahci_platform_get_resources(pdev, 0);
1111     if (IS_ERR(hpriv))
1112         return PTR_ERR(hpriv);
1113 
1114     hpriv->plat_data = imxpriv;
1115 
1116     ret = clk_prepare_enable(imxpriv->sata_clk);
1117     if (ret)
1118         return ret;
1119 
1120     if (imxpriv->type == AHCI_IMX53 &&
1121         IS_ENABLED(CONFIG_HWMON)) {
1122         /* Add the temperature monitor */
1123         struct device *hwmon_dev;
1124 
1125         hwmon_dev =
1126             devm_hwmon_device_register_with_groups(dev,
1127                             "sata_ahci",
1128                             hpriv,
1129                             fsl_sata_ahci_groups);
1130         if (IS_ERR(hwmon_dev)) {
1131             ret = PTR_ERR(hwmon_dev);
1132             goto disable_clk;
1133         }
1134         devm_thermal_zone_of_sensor_register(hwmon_dev, 0, hwmon_dev,
1135                          &fsl_sata_ahci_of_thermal_ops);
1136         dev_info(dev, "%s: sensor 'sata_ahci'\n", dev_name(hwmon_dev));
1137     }
1138 
1139     ret = imx_sata_enable(hpriv);
1140     if (ret)
1141         goto disable_clk;
1142 
1143     /*
1144      * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
1145      * and IP vendor specific register IMX_TIMER1MS.
1146      * Configure CAP_SSS (support stagered spin up).
1147      * Implement the port0.
1148      * Get the ahb clock rate, and configure the TIMER1MS register.
1149      */
1150     reg_val = readl(hpriv->mmio + HOST_CAP);
1151     if (!(reg_val & HOST_CAP_SSS)) {
1152         reg_val |= HOST_CAP_SSS;
1153         writel(reg_val, hpriv->mmio + HOST_CAP);
1154     }
1155     reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
1156     if (!(reg_val & 0x1)) {
1157         reg_val |= 0x1;
1158         writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
1159     }
1160 
1161     reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
1162     writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
1163 
1164     ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info,
1165                       &ahci_platform_sht);
1166     if (ret)
1167         goto disable_sata;
1168 
1169     return 0;
1170 
1171 disable_sata:
1172     imx_sata_disable(hpriv);
1173 disable_clk:
1174     clk_disable_unprepare(imxpriv->sata_clk);
1175     return ret;
1176 }
1177 
1178 static void ahci_imx_host_stop(struct ata_host *host)
1179 {
1180     struct ahci_host_priv *hpriv = host->private_data;
1181     struct imx_ahci_priv *imxpriv = hpriv->plat_data;
1182 
1183     imx_sata_disable(hpriv);
1184     clk_disable_unprepare(imxpriv->sata_clk);
1185 }
1186 
1187 #ifdef CONFIG_PM_SLEEP
1188 static int imx_ahci_suspend(struct device *dev)
1189 {
1190     struct ata_host *host = dev_get_drvdata(dev);
1191     struct ahci_host_priv *hpriv = host->private_data;
1192     int ret;
1193 
1194     ret = ahci_platform_suspend_host(dev);
1195     if (ret)
1196         return ret;
1197 
1198     imx_sata_disable(hpriv);
1199 
1200     return 0;
1201 }
1202 
1203 static int imx_ahci_resume(struct device *dev)
1204 {
1205     struct ata_host *host = dev_get_drvdata(dev);
1206     struct ahci_host_priv *hpriv = host->private_data;
1207     int ret;
1208 
1209     ret = imx_sata_enable(hpriv);
1210     if (ret)
1211         return ret;
1212 
1213     return ahci_platform_resume_host(dev);
1214 }
1215 #endif
1216 
1217 static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
1218 
1219 static struct platform_driver imx_ahci_driver = {
1220     .probe = imx_ahci_probe,
1221     .remove = ata_platform_remove_one,
1222     .driver = {
1223         .name = DRV_NAME,
1224         .of_match_table = imx_ahci_of_match,
1225         .pm = &ahci_imx_pm_ops,
1226     },
1227 };
1228 module_platform_driver(imx_ahci_driver);
1229 
1230 MODULE_DESCRIPTION("Freescale i.MX AHCI SATA platform driver");
1231 MODULE_AUTHOR("Richard Zhu <Hong-Xing.Zhu@freescale.com>");
1232 MODULE_LICENSE("GPL");
1233 MODULE_ALIAS("ahci:imx");
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