drivers/ata/ahci.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  ahci.h - Common AHCI SATA definitions and declarations
0004  *
0005  *  Maintained by:  Tejun Heo <tj@kernel.org>
0006  *              Please ALWAYS copy linux-ide@vger.kernel.org
0007  *          on emails.
0008  *
0009  *  Copyright 2004-2005 Red Hat, Inc.
0010  *
0011  * libata documentation is available via 'make {ps|pdf}docs',
0012  * as Documentation/driver-api/libata.rst
0013  *
0014  * AHCI hardware documentation:
0015  * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
0016  * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
0017  */
0018
0019 #ifndef _AHCI_H
0020 #define _AHCI_H
0021
0022 #include <linux/pci.h>
0023 #include <linux/clk.h>
0024 #include <linux/libata.h>
0025 #include <linux/phy/phy.h>
0026 #include <linux/regulator/consumer.h>
0027
0028 /* Enclosure Management Control */
0029 #define EM_CTRL_MSG_TYPE              0x000f0000
0030
0031 /* Enclosure Management LED Message Type */
0032 #define EM_MSG_LED_HBA_PORT           0x0000000f
0033 #define EM_MSG_LED_PMP_SLOT           0x0000ff00
0034 #define EM_MSG_LED_VALUE              0xffff0000
0035 #define EM_MSG_LED_VALUE_ACTIVITY     0x00070000
0036 #define EM_MSG_LED_VALUE_OFF          0xfff80000
0037 #define EM_MSG_LED_VALUE_ON           0x00010000
0038
0039 enum {
0040     AHCI_MAX_PORTS      = 32,
0041     AHCI_MAX_CLKS       = 5,
0042     AHCI_MAX_SG     = 168, /* hardware max is 64K */
0043     AHCI_DMA_BOUNDARY   = 0xffffffff,
0044     AHCI_MAX_CMDS       = 32,
0045     AHCI_CMD_SZ     = 32,
0046     AHCI_CMD_SLOT_SZ    = AHCI_MAX_CMDS * AHCI_CMD_SZ,
0047     AHCI_RX_FIS_SZ      = 256,
0048     AHCI_CMD_TBL_CDB    = 0x40,
0049     AHCI_CMD_TBL_HDR_SZ = 0x80,
0050     AHCI_CMD_TBL_SZ     = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
0051     AHCI_CMD_TBL_AR_SZ  = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
0052     AHCI_PORT_PRIV_DMA_SZ   = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
0053                   AHCI_RX_FIS_SZ,
0054     AHCI_PORT_PRIV_FBS_DMA_SZ   = AHCI_CMD_SLOT_SZ +
0055                       AHCI_CMD_TBL_AR_SZ +
0056                       (AHCI_RX_FIS_SZ * 16),
0057     AHCI_IRQ_ON_SG      = (1 << 31),
0058     AHCI_CMD_ATAPI      = (1 << 5),
0059     AHCI_CMD_WRITE      = (1 << 6),
0060     AHCI_CMD_PREFETCH   = (1 << 7),
0061     AHCI_CMD_RESET      = (1 << 8),
0062     AHCI_CMD_CLR_BUSY   = (1 << 10),
0063
0064     RX_FIS_PIO_SETUP    = 0x20, /* offset of PIO Setup FIS data */
0065     RX_FIS_D2H_REG      = 0x40, /* offset of D2H Register FIS data */
0066     RX_FIS_SDB      = 0x58, /* offset of SDB FIS data */
0067     RX_FIS_UNK      = 0x60, /* offset of Unknown FIS data */
0068
0069     /* global controller registers */
0070     HOST_CAP        = 0x00, /* host capabilities */
0071     HOST_CTL        = 0x04, /* global host control */
0072     HOST_IRQ_STAT       = 0x08, /* interrupt status */
0073     HOST_PORTS_IMPL     = 0x0c, /* bitmap of implemented ports */
0074     HOST_VERSION        = 0x10, /* AHCI spec. version compliancy */
0075     HOST_EM_LOC     = 0x1c, /* Enclosure Management location */
0076     HOST_EM_CTL     = 0x20, /* Enclosure Management Control */
0077     HOST_CAP2       = 0x24, /* host capabilities, extended */
0078
0079     /* HOST_CTL bits */
0080     HOST_RESET      = (1 << 0),  /* reset controller; self-clear */
0081     HOST_IRQ_EN     = (1 << 1),  /* global IRQ enable */
0082     HOST_MRSM       = (1 << 2),  /* MSI Revert to Single Message */
0083     HOST_AHCI_EN        = (1 << 31), /* AHCI enabled */
0084
0085     /* HOST_CAP bits */
0086     HOST_CAP_SXS        = (1 << 5),  /* Supports External SATA */
0087     HOST_CAP_EMS        = (1 << 6),  /* Enclosure Management support */
0088     HOST_CAP_CCC        = (1 << 7),  /* Command Completion Coalescing */
0089     HOST_CAP_PART       = (1 << 13), /* Partial state capable */
0090     HOST_CAP_SSC        = (1 << 14), /* Slumber state capable */
0091     HOST_CAP_PIO_MULTI  = (1 << 15), /* PIO multiple DRQ support */
0092     HOST_CAP_FBS        = (1 << 16), /* FIS-based switching support */
0093     HOST_CAP_PMP        = (1 << 17), /* Port Multiplier support */
0094     HOST_CAP_ONLY       = (1 << 18), /* Supports AHCI mode only */
0095     HOST_CAP_CLO        = (1 << 24), /* Command List Override support */
0096     HOST_CAP_LED        = (1 << 25), /* Supports activity LED */
0097     HOST_CAP_ALPM       = (1 << 26), /* Aggressive Link PM support */
0098     HOST_CAP_SSS        = (1 << 27), /* Staggered Spin-up */
0099     HOST_CAP_MPS        = (1 << 28), /* Mechanical presence switch */
0100     HOST_CAP_SNTF       = (1 << 29), /* SNotification register */
0101     HOST_CAP_NCQ        = (1 << 30), /* Native Command Queueing */
0102     HOST_CAP_64     = (1 << 31), /* PCI DAC (64-bit DMA) support */
0103
0104     /* HOST_CAP2 bits */
0105     HOST_CAP2_BOH       = (1 << 0),  /* BIOS/OS handoff supported */
0106     HOST_CAP2_NVMHCI    = (1 << 1),  /* NVMHCI supported */
0107     HOST_CAP2_APST      = (1 << 2),  /* Automatic partial to slumber */
0108     HOST_CAP2_SDS       = (1 << 3),  /* Support device sleep */
0109     HOST_CAP2_SADM      = (1 << 4),  /* Support aggressive DevSlp */
0110     HOST_CAP2_DESO      = (1 << 5),  /* DevSlp from slumber only */
0111
0112     /* registers for each SATA port */
0113     PORT_LST_ADDR       = 0x00, /* command list DMA addr */
0114     PORT_LST_ADDR_HI    = 0x04, /* command list DMA addr hi */
0115     PORT_FIS_ADDR       = 0x08, /* FIS rx buf addr */
0116     PORT_FIS_ADDR_HI    = 0x0c, /* FIS rx buf addr hi */
0117     PORT_IRQ_STAT       = 0x10, /* interrupt status */
0118     PORT_IRQ_MASK       = 0x14, /* interrupt enable/disable mask */
0119     PORT_CMD        = 0x18, /* port command */
0120     PORT_TFDATA     = 0x20, /* taskfile data */
0121     PORT_SIG        = 0x24, /* device TF signature */
0122     PORT_CMD_ISSUE      = 0x38, /* command issue */
0123     PORT_SCR_STAT       = 0x28, /* SATA phy register: SStatus */
0124     PORT_SCR_CTL        = 0x2c, /* SATA phy register: SControl */
0125     PORT_SCR_ERR        = 0x30, /* SATA phy register: SError */
0126     PORT_SCR_ACT        = 0x34, /* SATA phy register: SActive */
0127     PORT_SCR_NTF        = 0x3c, /* SATA phy register: SNotification */
0128     PORT_FBS        = 0x40, /* FIS-based Switching */
0129     PORT_DEVSLP     = 0x44, /* device sleep */
0130
0131     /* PORT_IRQ_{STAT,MASK} bits */
0132     PORT_IRQ_COLD_PRES  = (1 << 31), /* cold presence detect */
0133     PORT_IRQ_TF_ERR     = (1 << 30), /* task file error */
0134     PORT_IRQ_HBUS_ERR   = (1 << 29), /* host bus fatal error */
0135     PORT_IRQ_HBUS_DATA_ERR  = (1 << 28), /* host bus data error */
0136     PORT_IRQ_IF_ERR     = (1 << 27), /* interface fatal error */
0137     PORT_IRQ_IF_NONFATAL    = (1 << 26), /* interface non-fatal error */
0138     PORT_IRQ_OVERFLOW   = (1 << 24), /* xfer exhausted available S/G */
0139     PORT_IRQ_BAD_PMP    = (1 << 23), /* incorrect port multiplier */
0140
0141     PORT_IRQ_PHYRDY     = (1 << 22), /* PhyRdy changed */
0142     PORT_IRQ_DEV_ILCK   = (1 << 7), /* device interlock */
0143     PORT_IRQ_CONNECT    = (1 << 6), /* port connect change status */
0144     PORT_IRQ_SG_DONE    = (1 << 5), /* descriptor processed */
0145     PORT_IRQ_UNK_FIS    = (1 << 4), /* unknown FIS rx'd */
0146     PORT_IRQ_SDB_FIS    = (1 << 3), /* Set Device Bits FIS rx'd */
0147     PORT_IRQ_DMAS_FIS   = (1 << 2), /* DMA Setup FIS rx'd */
0148     PORT_IRQ_PIOS_FIS   = (1 << 1), /* PIO Setup FIS rx'd */
0149     PORT_IRQ_D2H_REG_FIS    = (1 << 0), /* D2H Register FIS rx'd */
0150
0151     PORT_IRQ_FREEZE     = PORT_IRQ_HBUS_ERR |
0152                   PORT_IRQ_IF_ERR |
0153                   PORT_IRQ_CONNECT |
0154                   PORT_IRQ_PHYRDY |
0155                   PORT_IRQ_UNK_FIS |
0156                   PORT_IRQ_BAD_PMP,
0157     PORT_IRQ_ERROR      = PORT_IRQ_FREEZE |
0158                   PORT_IRQ_TF_ERR |
0159                   PORT_IRQ_HBUS_DATA_ERR,
0160     DEF_PORT_IRQ        = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
0161                   PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
0162                   PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
0163
0164     /* PORT_CMD bits */
0165     PORT_CMD_ASP        = (1 << 27), /* Aggressive Slumber/Partial */
0166     PORT_CMD_ALPE       = (1 << 26), /* Aggressive Link PM enable */
0167     PORT_CMD_ATAPI      = (1 << 24), /* Device is ATAPI */
0168     PORT_CMD_FBSCP      = (1 << 22), /* FBS Capable Port */
0169     PORT_CMD_ESP        = (1 << 21), /* External Sata Port */
0170     PORT_CMD_HPCP       = (1 << 18), /* HotPlug Capable Port */
0171     PORT_CMD_PMP        = (1 << 17), /* PMP attached */
0172     PORT_CMD_LIST_ON    = (1 << 15), /* cmd list DMA engine running */
0173     PORT_CMD_FIS_ON     = (1 << 14), /* FIS DMA engine running */
0174     PORT_CMD_FIS_RX     = (1 << 4), /* Enable FIS receive DMA engine */
0175     PORT_CMD_CLO        = (1 << 3), /* Command list override */
0176     PORT_CMD_POWER_ON   = (1 << 2), /* Power up device */
0177     PORT_CMD_SPIN_UP    = (1 << 1), /* Spin up device */
0178     PORT_CMD_START      = (1 << 0), /* Enable port DMA engine */
0179
0180     PORT_CMD_ICC_MASK   = (0xf << 28), /* i/f ICC state mask */
0181     PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
0182     PORT_CMD_ICC_PARTIAL    = (0x2 << 28), /* Put i/f in partial state */
0183     PORT_CMD_ICC_SLUMBER    = (0x6 << 28), /* Put i/f in slumber state */
0184
0185     /* PORT_FBS bits */
0186     PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */
0187     PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
0188     PORT_FBS_DEV_OFFSET = 8,  /* FBS device to issue offset */
0189     PORT_FBS_DEV_MASK   = (0xf << PORT_FBS_DEV_OFFSET),  /* FBS.DEV */
0190     PORT_FBS_SDE        = (1 << 2), /* FBS single device error */
0191     PORT_FBS_DEC        = (1 << 1), /* FBS device error clear */
0192     PORT_FBS_EN     = (1 << 0), /* Enable FBS */
0193
0194     /* PORT_DEVSLP bits */
0195     PORT_DEVSLP_DM_OFFSET   = 25,             /* DITO multiplier offset */
0196     PORT_DEVSLP_DM_MASK = (0xf << 25),    /* DITO multiplier mask */
0197     PORT_DEVSLP_DITO_OFFSET = 15,             /* DITO offset */
0198     PORT_DEVSLP_MDAT_OFFSET = 10,             /* Minimum assertion time */
0199     PORT_DEVSLP_DETO_OFFSET = 2,              /* DevSlp exit timeout */
0200     PORT_DEVSLP_DSP     = (1 << 1),       /* DevSlp present */
0201     PORT_DEVSLP_ADSE    = (1 << 0),       /* Aggressive DevSlp enable */
0202
0203     /* hpriv->flags bits */
0204
0205 #define AHCI_HFLAGS(flags)      .private_data   = (void *)(flags)
0206
0207     AHCI_HFLAG_NO_NCQ       = (1 << 0),
0208     AHCI_HFLAG_IGN_IRQ_IF_ERR   = (1 << 1), /* ignore IRQ_IF_ERR */
0209     AHCI_HFLAG_IGN_SERR_INTERNAL    = (1 << 2), /* ignore SERR_INTERNAL */
0210     AHCI_HFLAG_32BIT_ONLY       = (1 << 3), /* force 32bit */
0211     AHCI_HFLAG_MV_PATA      = (1 << 4), /* PATA port */
0212     AHCI_HFLAG_NO_MSI       = (1 << 5), /* no PCI MSI */
0213     AHCI_HFLAG_NO_PMP       = (1 << 6), /* no PMP */
0214     AHCI_HFLAG_SECT255      = (1 << 8), /* max 255 sectors */
0215     AHCI_HFLAG_YES_NCQ      = (1 << 9), /* force NCQ cap on */
0216     AHCI_HFLAG_NO_SUSPEND       = (1 << 10), /* don't suspend */
0217     AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
0218                             link offline */
0219     AHCI_HFLAG_NO_SNTF      = (1 << 12), /* no sntf */
0220     AHCI_HFLAG_NO_FPDMA_AA      = (1 << 13), /* no FPDMA AA */
0221     AHCI_HFLAG_YES_FBS      = (1 << 14), /* force FBS cap on */
0222     AHCI_HFLAG_DELAY_ENGINE     = (1 << 15), /* do not start engine on
0223                                 port start (wait until
0224                                 error-handling stage) */
0225     AHCI_HFLAG_NO_DEVSLP        = (1 << 17), /* no device sleep */
0226     AHCI_HFLAG_NO_FBS       = (1 << 18), /* no FBS */
0227
0228 #ifdef CONFIG_PCI_MSI
0229     AHCI_HFLAG_MULTI_MSI        = (1 << 20), /* per-port MSI(-X) */
0230 #else
0231     /* compile out MSI infrastructure */
0232     AHCI_HFLAG_MULTI_MSI        = 0,
0233 #endif
0234     AHCI_HFLAG_WAKE_BEFORE_STOP = (1 << 22), /* wake before DMA stop */
0235     AHCI_HFLAG_YES_ALPM     = (1 << 23), /* force ALPM cap on */
0236     AHCI_HFLAG_NO_WRITE_TO_RO   = (1 << 24), /* don't write to read
0237                             only registers */
0238     AHCI_HFLAG_USE_LPM_POLICY   = (1 << 25), /* chipset that should use
0239                             SATA_MOBILE_LPM_POLICY
0240                             as default lpm_policy */
0241     AHCI_HFLAG_SUSPEND_PHYS     = (1 << 26), /* handle PHYs during
0242                             suspend/resume */
0243     AHCI_HFLAG_NO_SXS       = (1 << 28), /* SXS not supported */
0244
0245     /* ap->flags bits */
0246
0247     AHCI_FLAG_COMMON        = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
0248                       ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
0249
0250     ICH_MAP             = 0x90, /* ICH MAP register */
0251     PCS_6               = 0x92, /* 6 port PCS */
0252     PCS_7               = 0x94, /* 7+ port PCS (Denverton) */
0253
0254     /* em constants */
0255     EM_MAX_SLOTS            = 8,
0256     EM_MAX_RETRY            = 5,
0257
0258     /* em_ctl bits */
0259     EM_CTL_RST      = (1 << 9), /* Reset */
0260     EM_CTL_TM       = (1 << 8), /* Transmit Message */
0261     EM_CTL_MR       = (1 << 0), /* Message Received */
0262     EM_CTL_ALHD     = (1 << 26), /* Activity LED */
0263     EM_CTL_XMT      = (1 << 25), /* Transmit Only */
0264     EM_CTL_SMB      = (1 << 24), /* Single Message Buffer */
0265     EM_CTL_SGPIO        = (1 << 19), /* SGPIO messages supported */
0266     EM_CTL_SES      = (1 << 18), /* SES-2 messages supported */
0267     EM_CTL_SAFTE        = (1 << 17), /* SAF-TE messages supported */
0268     EM_CTL_LED      = (1 << 16), /* LED messages supported */
0269
0270     /* em message type */
0271     EM_MSG_TYPE_LED     = (1 << 0), /* LED */
0272     EM_MSG_TYPE_SAFTE   = (1 << 1), /* SAF-TE */
0273     EM_MSG_TYPE_SES2    = (1 << 2), /* SES-2 */
0274     EM_MSG_TYPE_SGPIO   = (1 << 3), /* SGPIO */
0275 };
0276
0277 struct ahci_cmd_hdr {
0278     __le32          opts;
0279     __le32          status;
0280     __le32          tbl_addr;
0281     __le32          tbl_addr_hi;
0282     __le32          reserved[4];
0283 };
0284
0285 struct ahci_sg {
0286     __le32          addr;
0287     __le32          addr_hi;
0288     __le32          reserved;
0289     __le32          flags_size;
0290 };
0291
0292 struct ahci_em_priv {
0293     enum sw_activity blink_policy;
0294     struct timer_list timer;
0295     unsigned long saved_activity;
0296     unsigned long activity;
0297     unsigned long led_state;
0298     struct ata_link *link;
0299 };
0300
0301 struct ahci_port_priv {
0302     struct ata_link     *active_link;
0303     struct ahci_cmd_hdr *cmd_slot;
0304     dma_addr_t      cmd_slot_dma;
0305     void            *cmd_tbl;
0306     dma_addr_t      cmd_tbl_dma;
0307     void            *rx_fis;
0308     dma_addr_t      rx_fis_dma;
0309     /* for NCQ spurious interrupt analysis */
0310     unsigned int        ncq_saw_d2h:1;
0311     unsigned int        ncq_saw_dmas:1;
0312     unsigned int        ncq_saw_sdb:1;
0313     spinlock_t      lock;       /* protects parent ata_port */
0314     u32             intr_mask;  /* interrupts to enable */
0315     bool            fbs_supported;  /* set iff FBS is supported */
0316     bool            fbs_enabled;    /* set iff FBS is enabled */
0317     int         fbs_last_dev;   /* save FBS.DEV of last FIS */
0318     /* enclosure management info per PM slot */
0319     struct ahci_em_priv em_priv[EM_MAX_SLOTS];
0320     char            *irq_desc;  /* desc in /proc/interrupts */
0321 };
0322
0323 struct ahci_host_priv {
0324     /* Input fields */
0325     unsigned int        flags;      /* AHCI_HFLAG_* */
0326     u32         force_port_map; /* force port map */
0327     u32         mask_port_map;  /* mask out particular bits */
0328
0329     void __iomem *      mmio;       /* bus-independent mem map */
0330     u32         cap;        /* cap to use */
0331     u32         cap2;       /* cap2 to use */
0332     u32         version;    /* cached version */
0333     u32         port_map;   /* port map to use */
0334     u32         saved_cap;  /* saved initial cap */
0335     u32         saved_cap2; /* saved initial cap2 */
0336     u32         saved_port_map; /* saved initial port_map */
0337     u32             em_loc; /* enclosure management location */
0338     u32         em_buf_sz;  /* EM buffer size in byte */
0339     u32         em_msg_type;    /* EM message type */
0340     u32         remapped_nvme;  /* NVMe remapped device count */
0341     bool            got_runtime_pm; /* Did we do pm_runtime_get? */
0342     struct clk      *clks[AHCI_MAX_CLKS]; /* Optional */
0343     struct reset_control    *rsts;      /* Optional */
0344     struct regulator    **target_pwrs;  /* Optional */
0345     struct regulator    *ahci_regulator;/* Optional */
0346     struct regulator    *phy_regulator;/* Optional */
0347     /*
0348      * If platform uses PHYs. There is a 1:1 relation between the port number and
0349      * the PHY position in this array.
0350      */
0351     struct phy      **phys;
0352     unsigned        nports;     /* Number of ports */
0353     void            *plat_data; /* Other platform data */
0354     unsigned int        irq;        /* interrupt line */
0355     /*
0356      * Optional ahci_start_engine override, if not set this gets set to the
0357      * default ahci_start_engine during ahci_save_initial_config, this can
0358      * be overridden anytime before the host is activated.
0359      */
0360     void            (*start_engine)(struct ata_port *ap);
0361     /*
0362      * Optional ahci_stop_engine override, if not set this gets set to the
0363      * default ahci_stop_engine during ahci_save_initial_config, this can
0364      * be overridden anytime before the host is activated.
0365      */
0366     int         (*stop_engine)(struct ata_port *ap);
0367
0368     irqreturn_t         (*irq_handler)(int irq, void *dev_instance);
0369
0370     /* only required for per-port MSI(-X) support */
0371     int         (*get_irq_vector)(struct ata_host *host,
0372                           int port);
0373 };
0374
0375 extern int ahci_ignore_sss;
0376
0377 extern const struct attribute_group *ahci_shost_groups[];
0378 extern const struct attribute_group *ahci_sdev_groups[];
0379
0380 /*
0381  * This must be instantiated by the edge drivers.  Read the comments
0382  * for ATA_BASE_SHT
0383  */
0384 #define AHCI_SHT(drv_name)                      \
0385     __ATA_BASE_SHT(drv_name),                   \
0386     .can_queue      = AHCI_MAX_CMDS,            \
0387     .sg_tablesize       = AHCI_MAX_SG,              \
0388     .dma_boundary       = AHCI_DMA_BOUNDARY,            \
0389     .shost_groups       = ahci_shost_groups,            \
0390     .sdev_groups        = ahci_sdev_groups,         \
0391     .change_queue_depth     = ata_scsi_change_queue_depth,      \
0392     .tag_alloc_policy       = BLK_TAG_ALLOC_RR,                 \
0393     .slave_configure        = ata_scsi_slave_config
0394
0395 extern struct ata_port_operations ahci_ops;
0396 extern struct ata_port_operations ahci_platform_ops;
0397 extern struct ata_port_operations ahci_pmp_retry_srst_ops;
0398
0399 unsigned int ahci_dev_classify(struct ata_port *ap);
0400 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
0401             u32 opts);
0402 void ahci_save_initial_config(struct device *dev,
0403                   struct ahci_host_priv *hpriv);
0404 void ahci_init_controller(struct ata_host *host);
0405 int ahci_reset_controller(struct ata_host *host);
0406
0407 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
0408               int pmp, unsigned long deadline,
0409               int (*check_ready)(struct ata_link *link));
0410
0411 int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
0412               unsigned long deadline, bool *online);
0413
0414 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
0415 int ahci_stop_engine(struct ata_port *ap);
0416 void ahci_start_fis_rx(struct ata_port *ap);
0417 void ahci_start_engine(struct ata_port *ap);
0418 int ahci_check_ready(struct ata_link *link);
0419 int ahci_kick_engine(struct ata_port *ap);
0420 int ahci_port_resume(struct ata_port *ap);
0421 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
0422               struct ata_port_info *pi);
0423 int ahci_reset_em(struct ata_host *host);
0424 void ahci_print_info(struct ata_host *host, const char *scc_s);
0425 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht);
0426 void ahci_error_handler(struct ata_port *ap);
0427 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked);
0428
0429 static inline void __iomem *__ahci_port_base(struct ata_host *host,
0430                          unsigned int port_no)
0431 {
0432     struct ahci_host_priv *hpriv = host->private_data;
0433     void __iomem *mmio = hpriv->mmio;
0434
0435     return mmio + 0x100 + (port_no * 0x80);
0436 }
0437
0438 static inline void __iomem *ahci_port_base(struct ata_port *ap)
0439 {
0440     return __ahci_port_base(ap->host, ap->port_no);
0441 }
0442
0443 static inline int ahci_nr_ports(u32 cap)
0444 {
0445     return (cap & 0x1f) + 1;
0446 }
0447
0448 #endif /* _AHCI_H */