drivers/ata/ahci.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  ahci.c - AHCI SATA support
0004  *
0005  *  Maintained by:  Tejun Heo <tj@kernel.org>
0006  *              Please ALWAYS copy linux-ide@vger.kernel.org
0007  *          on emails.
0008  *
0009  *  Copyright 2004-2005 Red Hat, Inc.
0010  *
0011  * libata documentation is available via 'make {ps|pdf}docs',
0012  * as Documentation/driver-api/libata.rst
0013  *
0014  * AHCI hardware documentation:
0015  * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
0016  * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
0017  */
0018
0019 #include <linux/kernel.h>
0020 #include <linux/module.h>
0021 #include <linux/pci.h>
0022 #include <linux/blkdev.h>
0023 #include <linux/delay.h>
0024 #include <linux/interrupt.h>
0025 #include <linux/dma-mapping.h>
0026 #include <linux/device.h>
0027 #include <linux/dmi.h>
0028 #include <linux/gfp.h>
0029 #include <linux/msi.h>
0030 #include <scsi/scsi_host.h>
0031 #include <scsi/scsi_cmnd.h>
0032 #include <linux/libata.h>
0033 #include <linux/ahci-remap.h>
0034 #include <linux/io-64-nonatomic-lo-hi.h>
0035 #include "ahci.h"
0036
0037 #define DRV_NAME    "ahci"
0038 #define DRV_VERSION "3.0"
0039
0040 enum {
0041     AHCI_PCI_BAR_STA2X11    = 0,
0042     AHCI_PCI_BAR_CAVIUM = 0,
0043     AHCI_PCI_BAR_LOONGSON   = 0,
0044     AHCI_PCI_BAR_ENMOTUS    = 2,
0045     AHCI_PCI_BAR_CAVIUM_GEN5    = 4,
0046     AHCI_PCI_BAR_STANDARD   = 5,
0047 };
0048
0049 enum board_ids {
0050     /* board IDs by feature in alphabetical order */
0051     board_ahci,
0052     board_ahci_ign_iferr,
0053     board_ahci_low_power,
0054     board_ahci_no_debounce_delay,
0055     board_ahci_nomsi,
0056     board_ahci_noncq,
0057     board_ahci_nosntf,
0058     board_ahci_yes_fbs,
0059
0060     /* board IDs for specific chipsets in alphabetical order */
0061     board_ahci_al,
0062     board_ahci_avn,
0063     board_ahci_mcp65,
0064     board_ahci_mcp77,
0065     board_ahci_mcp89,
0066     board_ahci_mv,
0067     board_ahci_sb600,
0068     board_ahci_sb700,   /* for SB700 and SB800 */
0069     board_ahci_vt8251,
0070
0071     /*
0072      * board IDs for Intel chipsets that support more than 6 ports
0073      * *and* end up needing the PCS quirk.
0074      */
0075     board_ahci_pcs7,
0076
0077     /* aliases */
0078     board_ahci_mcp_linux    = board_ahci_mcp65,
0079     board_ahci_mcp67    = board_ahci_mcp65,
0080     board_ahci_mcp73    = board_ahci_mcp65,
0081     board_ahci_mcp79    = board_ahci_mcp77,
0082 };
0083
0084 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
0085 static void ahci_remove_one(struct pci_dev *dev);
0086 static void ahci_shutdown_one(struct pci_dev *dev);
0087 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
0088                  unsigned long deadline);
0089 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
0090                   unsigned long deadline);
0091 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
0092 static bool is_mcp89_apple(struct pci_dev *pdev);
0093 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
0094                 unsigned long deadline);
0095 #ifdef CONFIG_PM
0096 static int ahci_pci_device_runtime_suspend(struct device *dev);
0097 static int ahci_pci_device_runtime_resume(struct device *dev);
0098 #ifdef CONFIG_PM_SLEEP
0099 static int ahci_pci_device_suspend(struct device *dev);
0100 static int ahci_pci_device_resume(struct device *dev);
0101 #endif
0102 #endif /* CONFIG_PM */
0103
0104 static struct scsi_host_template ahci_sht = {
0105     AHCI_SHT("ahci"),
0106 };
0107
0108 static struct ata_port_operations ahci_vt8251_ops = {
0109     .inherits       = &ahci_ops,
0110     .hardreset      = ahci_vt8251_hardreset,
0111 };
0112
0113 static struct ata_port_operations ahci_p5wdh_ops = {
0114     .inherits       = &ahci_ops,
0115     .hardreset      = ahci_p5wdh_hardreset,
0116 };
0117
0118 static struct ata_port_operations ahci_avn_ops = {
0119     .inherits       = &ahci_ops,
0120     .hardreset      = ahci_avn_hardreset,
0121 };
0122
0123 static const struct ata_port_info ahci_port_info[] = {
0124     /* by features */
0125     [board_ahci] = {
0126         .flags      = AHCI_FLAG_COMMON,
0127         .pio_mask   = ATA_PIO4,
0128         .udma_mask  = ATA_UDMA6,
0129         .port_ops   = &ahci_ops,
0130     },
0131     [board_ahci_ign_iferr] = {
0132         AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
0133         .flags      = AHCI_FLAG_COMMON,
0134         .pio_mask   = ATA_PIO4,
0135         .udma_mask  = ATA_UDMA6,
0136         .port_ops   = &ahci_ops,
0137     },
0138     [board_ahci_low_power] = {
0139         AHCI_HFLAGS (AHCI_HFLAG_USE_LPM_POLICY),
0140         .flags      = AHCI_FLAG_COMMON,
0141         .pio_mask   = ATA_PIO4,
0142         .udma_mask  = ATA_UDMA6,
0143         .port_ops   = &ahci_ops,
0144     },
0145     [board_ahci_no_debounce_delay] = {
0146         .flags      = AHCI_FLAG_COMMON,
0147         .link_flags = ATA_LFLAG_NO_DEBOUNCE_DELAY,
0148         .pio_mask   = ATA_PIO4,
0149         .udma_mask  = ATA_UDMA6,
0150         .port_ops   = &ahci_ops,
0151     },
0152     [board_ahci_nomsi] = {
0153         AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
0154         .flags      = AHCI_FLAG_COMMON,
0155         .pio_mask   = ATA_PIO4,
0156         .udma_mask  = ATA_UDMA6,
0157         .port_ops   = &ahci_ops,
0158     },
0159     [board_ahci_noncq] = {
0160         AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
0161         .flags      = AHCI_FLAG_COMMON,
0162         .pio_mask   = ATA_PIO4,
0163         .udma_mask  = ATA_UDMA6,
0164         .port_ops   = &ahci_ops,
0165     },
0166     [board_ahci_nosntf] = {
0167         AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
0168         .flags      = AHCI_FLAG_COMMON,
0169         .pio_mask   = ATA_PIO4,
0170         .udma_mask  = ATA_UDMA6,
0171         .port_ops   = &ahci_ops,
0172     },
0173     [board_ahci_yes_fbs] = {
0174         AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
0175         .flags      = AHCI_FLAG_COMMON,
0176         .pio_mask   = ATA_PIO4,
0177         .udma_mask  = ATA_UDMA6,
0178         .port_ops   = &ahci_ops,
0179     },
0180     /* by chipsets */
0181     [board_ahci_al] = {
0182         AHCI_HFLAGS (AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_MSI),
0183         .flags      = AHCI_FLAG_COMMON,
0184         .pio_mask   = ATA_PIO4,
0185         .udma_mask  = ATA_UDMA6,
0186         .port_ops   = &ahci_ops,
0187     },
0188     [board_ahci_avn] = {
0189         .flags      = AHCI_FLAG_COMMON,
0190         .pio_mask   = ATA_PIO4,
0191         .udma_mask  = ATA_UDMA6,
0192         .port_ops   = &ahci_avn_ops,
0193     },
0194     [board_ahci_mcp65] = {
0195         AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
0196                  AHCI_HFLAG_YES_NCQ),
0197         .flags      = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
0198         .pio_mask   = ATA_PIO4,
0199         .udma_mask  = ATA_UDMA6,
0200         .port_ops   = &ahci_ops,
0201     },
0202     [board_ahci_mcp77] = {
0203         AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
0204         .flags      = AHCI_FLAG_COMMON,
0205         .pio_mask   = ATA_PIO4,
0206         .udma_mask  = ATA_UDMA6,
0207         .port_ops   = &ahci_ops,
0208     },
0209     [board_ahci_mcp89] = {
0210         AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
0211         .flags      = AHCI_FLAG_COMMON,
0212         .pio_mask   = ATA_PIO4,
0213         .udma_mask  = ATA_UDMA6,
0214         .port_ops   = &ahci_ops,
0215     },
0216     [board_ahci_mv] = {
0217         AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
0218                  AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
0219         .flags      = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
0220         .pio_mask   = ATA_PIO4,
0221         .udma_mask  = ATA_UDMA6,
0222         .port_ops   = &ahci_ops,
0223     },
0224     [board_ahci_sb600] = {
0225         AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
0226                  AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
0227                  AHCI_HFLAG_32BIT_ONLY),
0228         .flags      = AHCI_FLAG_COMMON,
0229         .pio_mask   = ATA_PIO4,
0230         .udma_mask  = ATA_UDMA6,
0231         .port_ops   = &ahci_pmp_retry_srst_ops,
0232     },
0233     [board_ahci_sb700] = {  /* for SB700 and SB800 */
0234         AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
0235         .flags      = AHCI_FLAG_COMMON,
0236         .pio_mask   = ATA_PIO4,
0237         .udma_mask  = ATA_UDMA6,
0238         .port_ops   = &ahci_pmp_retry_srst_ops,
0239     },
0240     [board_ahci_vt8251] = {
0241         AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
0242         .flags      = AHCI_FLAG_COMMON,
0243         .pio_mask   = ATA_PIO4,
0244         .udma_mask  = ATA_UDMA6,
0245         .port_ops   = &ahci_vt8251_ops,
0246     },
0247     [board_ahci_pcs7] = {
0248         .flags      = AHCI_FLAG_COMMON,
0249         .pio_mask   = ATA_PIO4,
0250         .udma_mask  = ATA_UDMA6,
0251         .port_ops   = &ahci_ops,
0252     },
0253 };
0254
0255 static const struct pci_device_id ahci_pci_tbl[] = {
0256     /* Intel */
0257     { PCI_VDEVICE(INTEL, 0x06d6), board_ahci }, /* Comet Lake PCH-H RAID */
0258     { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
0259     { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
0260     { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
0261     { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
0262     { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
0263     { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
0264     { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
0265     { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
0266     { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
0267     { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
0268     { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
0269     { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8/Lewisburg RAID*/
0270     { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
0271     { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
0272     { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
0273     { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
0274     { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
0275     { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
0276     { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
0277     { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
0278     { PCI_VDEVICE(INTEL, 0x2929), board_ahci_low_power }, /* ICH9M */
0279     { PCI_VDEVICE(INTEL, 0x292a), board_ahci_low_power }, /* ICH9M */
0280     { PCI_VDEVICE(INTEL, 0x292b), board_ahci_low_power }, /* ICH9M */
0281     { PCI_VDEVICE(INTEL, 0x292c), board_ahci_low_power }, /* ICH9M */
0282     { PCI_VDEVICE(INTEL, 0x292f), board_ahci_low_power }, /* ICH9M */
0283     { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
0284     { PCI_VDEVICE(INTEL, 0x294e), board_ahci_low_power }, /* ICH9M */
0285     { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
0286     { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
0287     { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
0288     { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
0289     { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
0290     { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
0291     { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
0292     { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
0293     { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
0294     { PCI_VDEVICE(INTEL, 0x3b29), board_ahci_low_power }, /* PCH M AHCI */
0295     { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
0296     { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci_low_power }, /* PCH M RAID */
0297     { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
0298     { PCI_VDEVICE(INTEL, 0x19b0), board_ahci_pcs7 }, /* DNV AHCI */
0299     { PCI_VDEVICE(INTEL, 0x19b1), board_ahci_pcs7 }, /* DNV AHCI */
0300     { PCI_VDEVICE(INTEL, 0x19b2), board_ahci_pcs7 }, /* DNV AHCI */
0301     { PCI_VDEVICE(INTEL, 0x19b3), board_ahci_pcs7 }, /* DNV AHCI */
0302     { PCI_VDEVICE(INTEL, 0x19b4), board_ahci_pcs7 }, /* DNV AHCI */
0303     { PCI_VDEVICE(INTEL, 0x19b5), board_ahci_pcs7 }, /* DNV AHCI */
0304     { PCI_VDEVICE(INTEL, 0x19b6), board_ahci_pcs7 }, /* DNV AHCI */
0305     { PCI_VDEVICE(INTEL, 0x19b7), board_ahci_pcs7 }, /* DNV AHCI */
0306     { PCI_VDEVICE(INTEL, 0x19bE), board_ahci_pcs7 }, /* DNV AHCI */
0307     { PCI_VDEVICE(INTEL, 0x19bF), board_ahci_pcs7 }, /* DNV AHCI */
0308     { PCI_VDEVICE(INTEL, 0x19c0), board_ahci_pcs7 }, /* DNV AHCI */
0309     { PCI_VDEVICE(INTEL, 0x19c1), board_ahci_pcs7 }, /* DNV AHCI */
0310     { PCI_VDEVICE(INTEL, 0x19c2), board_ahci_pcs7 }, /* DNV AHCI */
0311     { PCI_VDEVICE(INTEL, 0x19c3), board_ahci_pcs7 }, /* DNV AHCI */
0312     { PCI_VDEVICE(INTEL, 0x19c4), board_ahci_pcs7 }, /* DNV AHCI */
0313     { PCI_VDEVICE(INTEL, 0x19c5), board_ahci_pcs7 }, /* DNV AHCI */
0314     { PCI_VDEVICE(INTEL, 0x19c6), board_ahci_pcs7 }, /* DNV AHCI */
0315     { PCI_VDEVICE(INTEL, 0x19c7), board_ahci_pcs7 }, /* DNV AHCI */
0316     { PCI_VDEVICE(INTEL, 0x19cE), board_ahci_pcs7 }, /* DNV AHCI */
0317     { PCI_VDEVICE(INTEL, 0x19cF), board_ahci_pcs7 }, /* DNV AHCI */
0318     { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
0319     { PCI_VDEVICE(INTEL, 0x1c03), board_ahci_low_power }, /* CPT M AHCI */
0320     { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
0321     { PCI_VDEVICE(INTEL, 0x1c05), board_ahci_low_power }, /* CPT M RAID */
0322     { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
0323     { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
0324     { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
0325     { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
0326     { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
0327     { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
0328     { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
0329     { PCI_VDEVICE(INTEL, 0x1e03), board_ahci_low_power }, /* Panther M AHCI */
0330     { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
0331     { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
0332     { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
0333     { PCI_VDEVICE(INTEL, 0x1e07), board_ahci_low_power }, /* Panther M RAID */
0334     { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
0335     { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
0336     { PCI_VDEVICE(INTEL, 0x8c03), board_ahci_low_power }, /* Lynx M AHCI */
0337     { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
0338     { PCI_VDEVICE(INTEL, 0x8c05), board_ahci_low_power }, /* Lynx M RAID */
0339     { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
0340     { PCI_VDEVICE(INTEL, 0x8c07), board_ahci_low_power }, /* Lynx M RAID */
0341     { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
0342     { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci_low_power }, /* Lynx M RAID */
0343     { PCI_VDEVICE(INTEL, 0x9c02), board_ahci_low_power }, /* Lynx LP AHCI */
0344     { PCI_VDEVICE(INTEL, 0x9c03), board_ahci_low_power }, /* Lynx LP AHCI */
0345     { PCI_VDEVICE(INTEL, 0x9c04), board_ahci_low_power }, /* Lynx LP RAID */
0346     { PCI_VDEVICE(INTEL, 0x9c05), board_ahci_low_power }, /* Lynx LP RAID */
0347     { PCI_VDEVICE(INTEL, 0x9c06), board_ahci_low_power }, /* Lynx LP RAID */
0348     { PCI_VDEVICE(INTEL, 0x9c07), board_ahci_low_power }, /* Lynx LP RAID */
0349     { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci_low_power }, /* Lynx LP RAID */
0350     { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci_low_power }, /* Lynx LP RAID */
0351     { PCI_VDEVICE(INTEL, 0x9dd3), board_ahci_low_power }, /* Cannon Lake PCH-LP AHCI */
0352     { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
0353     { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
0354     { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
0355     { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
0356     { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
0357     { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
0358     { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
0359     { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
0360     { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
0361     { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
0362     { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
0363     { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
0364     { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
0365     { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
0366     { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
0367     { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
0368     { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg/Lewisburg AHCI*/
0369     { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* *burg SATA0 'RAID' */
0370     { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* *burg SATA1 'RAID' */
0371     { PCI_VDEVICE(INTEL, 0x282f), board_ahci }, /* *burg SATA2 'RAID' */
0372     { PCI_VDEVICE(INTEL, 0x43d4), board_ahci }, /* Rocket Lake PCH-H RAID */
0373     { PCI_VDEVICE(INTEL, 0x43d5), board_ahci }, /* Rocket Lake PCH-H RAID */
0374     { PCI_VDEVICE(INTEL, 0x43d6), board_ahci }, /* Rocket Lake PCH-H RAID */
0375     { PCI_VDEVICE(INTEL, 0x43d7), board_ahci }, /* Rocket Lake PCH-H RAID */
0376     { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
0377     { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
0378     { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
0379     { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
0380     { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
0381     { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
0382     { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
0383     { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
0384     { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
0385     { PCI_VDEVICE(INTEL, 0x9c83), board_ahci_low_power }, /* Wildcat LP AHCI */
0386     { PCI_VDEVICE(INTEL, 0x9c85), board_ahci_low_power }, /* Wildcat LP RAID */
0387     { PCI_VDEVICE(INTEL, 0x9c87), board_ahci_low_power }, /* Wildcat LP RAID */
0388     { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci_low_power }, /* Wildcat LP RAID */
0389     { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
0390     { PCI_VDEVICE(INTEL, 0x8c83), board_ahci_low_power }, /* 9 Series M AHCI */
0391     { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
0392     { PCI_VDEVICE(INTEL, 0x8c85), board_ahci_low_power }, /* 9 Series M RAID */
0393     { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
0394     { PCI_VDEVICE(INTEL, 0x8c87), board_ahci_low_power }, /* 9 Series M RAID */
0395     { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
0396     { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci_low_power }, /* 9 Series M RAID */
0397     { PCI_VDEVICE(INTEL, 0x9d03), board_ahci_low_power }, /* Sunrise LP AHCI */
0398     { PCI_VDEVICE(INTEL, 0x9d05), board_ahci_low_power }, /* Sunrise LP RAID */
0399     { PCI_VDEVICE(INTEL, 0x9d07), board_ahci_low_power }, /* Sunrise LP RAID */
0400     { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
0401     { PCI_VDEVICE(INTEL, 0xa103), board_ahci_low_power }, /* Sunrise M AHCI */
0402     { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
0403     { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
0404     { PCI_VDEVICE(INTEL, 0xa107), board_ahci_low_power }, /* Sunrise M RAID */
0405     { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
0406     { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
0407     { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
0408     { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
0409     { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
0410     { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
0411     { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
0412     { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
0413     { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
0414     { PCI_VDEVICE(INTEL, 0xa356), board_ahci }, /* Cannon Lake PCH-H RAID */
0415     { PCI_VDEVICE(INTEL, 0x06d7), board_ahci }, /* Comet Lake-H RAID */
0416     { PCI_VDEVICE(INTEL, 0xa386), board_ahci }, /* Comet Lake PCH-V RAID */
0417     { PCI_VDEVICE(INTEL, 0x0f22), board_ahci_low_power }, /* Bay Trail AHCI */
0418     { PCI_VDEVICE(INTEL, 0x0f23), board_ahci_low_power }, /* Bay Trail AHCI */
0419     { PCI_VDEVICE(INTEL, 0x22a3), board_ahci_low_power }, /* Cherry Tr. AHCI */
0420     { PCI_VDEVICE(INTEL, 0x5ae3), board_ahci_low_power }, /* ApolloLake AHCI */
0421     { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */
0422     { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */
0423     { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */
0424
0425     /* JMicron 360/1/3/5/6, match class to avoid IDE function */
0426     { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
0427       PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
0428     /* JMicron 362B and 362C have an AHCI function with IDE class code */
0429     { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
0430     { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
0431     /* May need to update quirk_jmicron_async_suspend() for additions */
0432
0433     /* ATI */
0434     { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
0435     { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
0436     { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
0437     { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
0438     { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
0439     { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
0440     { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
0441
0442     /* Amazon's Annapurna Labs support */
0443     { PCI_DEVICE(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031),
0444         .class = PCI_CLASS_STORAGE_SATA_AHCI,
0445         .class_mask = 0xffffff,
0446         board_ahci_al },
0447     /* AMD */
0448     { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
0449     { PCI_VDEVICE(AMD, 0x7801), board_ahci_no_debounce_delay }, /* AMD Hudson-2 (AHCI mode) */
0450     { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
0451     { PCI_VDEVICE(AMD, 0x7901), board_ahci_low_power }, /* AMD Green Sardine */
0452     /* AMD is using RAID class only for ahci controllers */
0453     { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
0454       PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
0455
0456     /* Dell S140/S150 */
0457     { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_SUBVENDOR_ID_DELL, PCI_ANY_ID,
0458       PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
0459
0460     /* VIA */
0461     { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
0462     { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
0463
0464     /* NVIDIA */
0465     { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },  /* MCP65 */
0466     { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },  /* MCP65 */
0467     { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },  /* MCP65 */
0468     { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },  /* MCP65 */
0469     { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },  /* MCP65 */
0470     { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },  /* MCP65 */
0471     { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },  /* MCP65 */
0472     { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },  /* MCP65 */
0473     { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },  /* MCP67 */
0474     { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },  /* MCP67 */
0475     { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },  /* MCP67 */
0476     { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },  /* MCP67 */
0477     { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },  /* MCP67 */
0478     { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },  /* MCP67 */
0479     { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },  /* MCP67 */
0480     { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },  /* MCP67 */
0481     { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },  /* MCP67 */
0482     { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },  /* MCP67 */
0483     { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },  /* MCP67 */
0484     { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },  /* MCP67 */
0485     { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },  /* Linux ID */
0486     { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },  /* Linux ID */
0487     { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },  /* Linux ID */
0488     { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },  /* Linux ID */
0489     { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },  /* Linux ID */
0490     { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },  /* Linux ID */
0491     { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },  /* Linux ID */
0492     { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },  /* Linux ID */
0493     { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },  /* Linux ID */
0494     { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },  /* Linux ID */
0495     { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },  /* Linux ID */
0496     { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },  /* Linux ID */
0497     { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },  /* Linux ID */
0498     { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },  /* Linux ID */
0499     { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },  /* Linux ID */
0500     { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },  /* Linux ID */
0501     { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },  /* MCP73 */
0502     { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },  /* MCP73 */
0503     { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },  /* MCP73 */
0504     { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },  /* MCP73 */
0505     { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },  /* MCP73 */
0506     { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },  /* MCP73 */
0507     { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },  /* MCP73 */
0508     { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },  /* MCP73 */
0509     { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },  /* MCP73 */
0510     { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },  /* MCP73 */
0511     { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },  /* MCP73 */
0512     { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },  /* MCP73 */
0513     { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },  /* MCP77 */
0514     { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },  /* MCP77 */
0515     { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },  /* MCP77 */
0516     { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },  /* MCP77 */
0517     { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },  /* MCP77 */
0518     { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },  /* MCP77 */
0519     { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },  /* MCP77 */
0520     { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },  /* MCP77 */
0521     { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },  /* MCP77 */
0522     { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },  /* MCP77 */
0523     { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },  /* MCP77 */
0524     { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },  /* MCP77 */
0525     { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },  /* MCP79 */
0526     { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },  /* MCP79 */
0527     { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },  /* MCP79 */
0528     { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },  /* MCP79 */
0529     { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },  /* MCP79 */
0530     { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },  /* MCP79 */
0531     { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },  /* MCP79 */
0532     { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },  /* MCP79 */
0533     { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },  /* MCP79 */
0534     { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },  /* MCP79 */
0535     { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },  /* MCP79 */
0536     { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },  /* MCP79 */
0537     { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },  /* MCP89 */
0538     { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },  /* MCP89 */
0539     { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },  /* MCP89 */
0540     { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },  /* MCP89 */
0541     { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },  /* MCP89 */
0542     { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },  /* MCP89 */
0543     { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },  /* MCP89 */
0544     { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },  /* MCP89 */
0545     { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },  /* MCP89 */
0546     { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },  /* MCP89 */
0547     { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },  /* MCP89 */
0548     { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },  /* MCP89 */
0549
0550     /* SiS */
0551     { PCI_VDEVICE(SI, 0x1184), board_ahci },        /* SiS 966 */
0552     { PCI_VDEVICE(SI, 0x1185), board_ahci },        /* SiS 968 */
0553     { PCI_VDEVICE(SI, 0x0186), board_ahci },        /* SiS 968 */
0554
0555     /* ST Microelectronics */
0556     { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci },       /* ST ConneXt */
0557
0558     /* Marvell */
0559     { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },    /* 6145 */
0560     { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },    /* 6121 */
0561     { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
0562       .class = PCI_CLASS_STORAGE_SATA_AHCI,
0563       .class_mask = 0xffffff,
0564       .driver_data = board_ahci_yes_fbs },          /* 88se9128 */
0565     { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
0566       .driver_data = board_ahci_yes_fbs },          /* 88se9125 */
0567     { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
0568              PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
0569       .driver_data = board_ahci_yes_fbs },          /* 88se9170 */
0570     { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
0571       .driver_data = board_ahci_yes_fbs },          /* 88se9172 */
0572     { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
0573       .driver_data = board_ahci_yes_fbs },          /* 88se9182 */
0574     { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
0575       .driver_data = board_ahci_yes_fbs },          /* 88se9172 */
0576     { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
0577       .driver_data = board_ahci_yes_fbs },          /* 88se9172 on some Gigabyte */
0578     { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
0579       .driver_data = board_ahci_yes_fbs },
0580     { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2),    /* 88se91a2 */
0581       .driver_data = board_ahci_yes_fbs },
0582     { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
0583       .driver_data = board_ahci_yes_fbs },
0584     { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
0585       .driver_data = board_ahci_yes_fbs },
0586     { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9235),
0587       .driver_data = board_ahci_no_debounce_delay },
0588     { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642), /* highpoint rocketraid 642L */
0589       .driver_data = board_ahci_yes_fbs },
0590     { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0645), /* highpoint rocketraid 644L */
0591       .driver_data = board_ahci_yes_fbs },
0592
0593     /* Promise */
0594     { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },   /* PDC42819 */
0595     { PCI_VDEVICE(PROMISE, 0x3781), board_ahci },   /* FastTrak TX8660 ahci-mode */
0596
0597     /* Asmedia */
0598     { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci },   /* ASM1060 */
0599     { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci },   /* ASM1060 */
0600     { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci },   /* ASM1061 */
0601     { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci },   /* ASM1062 */
0602     { PCI_VDEVICE(ASMEDIA, 0x0621), board_ahci },   /* ASM1061R */
0603     { PCI_VDEVICE(ASMEDIA, 0x0622), board_ahci },   /* ASM1062R */
0604     { PCI_VDEVICE(ASMEDIA, 0x0624), board_ahci },   /* ASM1062+JMB575 */
0605
0606     /*
0607      * Samsung SSDs found on some macbooks.  NCQ times out if MSI is
0608      * enabled.  https://bugzilla.kernel.org/show_bug.cgi?id=60731
0609      */
0610     { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
0611     { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
0612
0613     /* Enmotus */
0614     { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
0615
0616     /* Loongson */
0617     { PCI_VDEVICE(LOONGSON, 0x7a08), board_ahci },
0618
0619     /* Generic, PCI class code for AHCI */
0620     { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
0621       PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
0622
0623     { } /* terminate list */
0624 };
0625
0626 static const struct dev_pm_ops ahci_pci_pm_ops = {
0627     SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
0628     SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
0629                ahci_pci_device_runtime_resume, NULL)
0630 };
0631
0632 static struct pci_driver ahci_pci_driver = {
0633     .name           = DRV_NAME,
0634     .id_table       = ahci_pci_tbl,
0635     .probe          = ahci_init_one,
0636     .remove         = ahci_remove_one,
0637     .shutdown       = ahci_shutdown_one,
0638     .driver = {
0639         .pm     = &ahci_pci_pm_ops,
0640     },
0641 };
0642
0643 #if IS_ENABLED(CONFIG_PATA_MARVELL)
0644 static int marvell_enable;
0645 #else
0646 static int marvell_enable = 1;
0647 #endif
0648 module_param(marvell_enable, int, 0644);
0649 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
0650
0651 static int mobile_lpm_policy = -1;
0652 module_param(mobile_lpm_policy, int, 0644);
0653 MODULE_PARM_DESC(mobile_lpm_policy, "Default LPM policy for mobile chipsets");
0654
0655 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
0656                      struct ahci_host_priv *hpriv)
0657 {
0658     if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
0659         dev_info(&pdev->dev, "JMB361 has only one port\n");
0660         hpriv->force_port_map = 1;
0661     }
0662
0663     /*
0664      * Temporary Marvell 6145 hack: PATA port presence
0665      * is asserted through the standard AHCI port
0666      * presence register, as bit 4 (counting from 0)
0667      */
0668     if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
0669         if (pdev->device == 0x6121)
0670             hpriv->mask_port_map = 0x3;
0671         else
0672             hpriv->mask_port_map = 0xf;
0673         dev_info(&pdev->dev,
0674               "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
0675     }
0676
0677     ahci_save_initial_config(&pdev->dev, hpriv);
0678 }
0679
0680 static void ahci_pci_init_controller(struct ata_host *host)
0681 {
0682     struct ahci_host_priv *hpriv = host->private_data;
0683     struct pci_dev *pdev = to_pci_dev(host->dev);
0684     void __iomem *port_mmio;
0685     u32 tmp;
0686     int mv;
0687
0688     if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
0689         if (pdev->device == 0x6121)
0690             mv = 2;
0691         else
0692             mv = 4;
0693         port_mmio = __ahci_port_base(host, mv);
0694
0695         writel(0, port_mmio + PORT_IRQ_MASK);
0696
0697         /* clear port IRQ */
0698         tmp = readl(port_mmio + PORT_IRQ_STAT);
0699         dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
0700         if (tmp)
0701             writel(tmp, port_mmio + PORT_IRQ_STAT);
0702     }
0703
0704     ahci_init_controller(host);
0705 }
0706
0707 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
0708                  unsigned long deadline)
0709 {
0710     struct ata_port *ap = link->ap;
0711     struct ahci_host_priv *hpriv = ap->host->private_data;
0712     bool online;
0713     int rc;
0714
0715     hpriv->stop_engine(ap);
0716
0717     rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
0718                  deadline, &online, NULL);
0719
0720     hpriv->start_engine(ap);
0721
0722     /* vt8251 doesn't clear BSY on signature FIS reception,
0723      * request follow-up softreset.
0724      */
0725     return online ? -EAGAIN : rc;
0726 }
0727
0728 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
0729                 unsigned long deadline)
0730 {
0731     struct ata_port *ap = link->ap;
0732     struct ahci_port_priv *pp = ap->private_data;
0733     struct ahci_host_priv *hpriv = ap->host->private_data;
0734     u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
0735     struct ata_taskfile tf;
0736     bool online;
0737     int rc;
0738
0739     hpriv->stop_engine(ap);
0740
0741     /* clear D2H reception area to properly wait for D2H FIS */
0742     ata_tf_init(link->device, &tf);
0743     tf.status = ATA_BUSY;
0744     ata_tf_to_fis(&tf, 0, 0, d2h_fis);
0745
0746     rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
0747                  deadline, &online, NULL);
0748
0749     hpriv->start_engine(ap);
0750
0751     /* The pseudo configuration device on SIMG4726 attached to
0752      * ASUS P5W-DH Deluxe doesn't send signature FIS after
0753      * hardreset if no device is attached to the first downstream
0754      * port && the pseudo device locks up on SRST w/ PMP==0.  To
0755      * work around this, wait for !BSY only briefly.  If BSY isn't
0756      * cleared, perform CLO and proceed to IDENTIFY (achieved by
0757      * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
0758      *
0759      * Wait for two seconds.  Devices attached to downstream port
0760      * which can't process the following IDENTIFY after this will
0761      * have to be reset again.  For most cases, this should
0762      * suffice while making probing snappish enough.
0763      */
0764     if (online) {
0765         rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
0766                       ahci_check_ready);
0767         if (rc)
0768             ahci_kick_engine(ap);
0769     }
0770     return rc;
0771 }
0772
0773 /*
0774  * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
0775  *
0776  * It has been observed with some SSDs that the timing of events in the
0777  * link synchronization phase can leave the port in a state that can not
0778  * be recovered by a SATA-hard-reset alone.  The failing signature is
0779  * SStatus.DET stuck at 1 ("Device presence detected but Phy
0780  * communication not established").  It was found that unloading and
0781  * reloading the driver when this problem occurs allows the drive
0782  * connection to be recovered (DET advanced to 0x3).  The critical
0783  * component of reloading the driver is that the port state machines are
0784  * reset by bouncing "port enable" in the AHCI PCS configuration
0785  * register.  So, reproduce that effect by bouncing a port whenever we
0786  * see DET==1 after a reset.
0787  */
0788 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
0789                   unsigned long deadline)
0790 {
0791     const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
0792     struct ata_port *ap = link->ap;
0793     struct ahci_port_priv *pp = ap->private_data;
0794     struct ahci_host_priv *hpriv = ap->host->private_data;
0795     u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
0796     unsigned long tmo = deadline - jiffies;
0797     struct ata_taskfile tf;
0798     bool online;
0799     int rc, i;
0800
0801     hpriv->stop_engine(ap);
0802
0803     for (i = 0; i < 2; i++) {
0804         u16 val;
0805         u32 sstatus;
0806         int port = ap->port_no;
0807         struct ata_host *host = ap->host;
0808         struct pci_dev *pdev = to_pci_dev(host->dev);
0809
0810         /* clear D2H reception area to properly wait for D2H FIS */
0811         ata_tf_init(link->device, &tf);
0812         tf.status = ATA_BUSY;
0813         ata_tf_to_fis(&tf, 0, 0, d2h_fis);
0814
0815         rc = sata_link_hardreset(link, timing, deadline, &online,
0816                 ahci_check_ready);
0817
0818         if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
0819                 (sstatus & 0xf) != 1)
0820             break;
0821
0822         ata_link_info(link,  "avn bounce port%d\n", port);
0823
0824         pci_read_config_word(pdev, 0x92, &val);
0825         val &= ~(1 << port);
0826         pci_write_config_word(pdev, 0x92, val);
0827         ata_msleep(ap, 1000);
0828         val |= 1 << port;
0829         pci_write_config_word(pdev, 0x92, val);
0830         deadline += tmo;
0831     }
0832
0833     hpriv->start_engine(ap);
0834
0835     if (online)
0836         *class = ahci_dev_classify(ap);
0837
0838     return rc;
0839 }
0840
0841
0842 #ifdef CONFIG_PM
0843 static void ahci_pci_disable_interrupts(struct ata_host *host)
0844 {
0845     struct ahci_host_priv *hpriv = host->private_data;
0846     void __iomem *mmio = hpriv->mmio;
0847     u32 ctl;
0848
0849     /* AHCI spec rev1.1 section 8.3.3:
0850      * Software must disable interrupts prior to requesting a
0851      * transition of the HBA to D3 state.
0852      */
0853     ctl = readl(mmio + HOST_CTL);
0854     ctl &= ~HOST_IRQ_EN;
0855     writel(ctl, mmio + HOST_CTL);
0856     readl(mmio + HOST_CTL); /* flush */
0857 }
0858
0859 static int ahci_pci_device_runtime_suspend(struct device *dev)
0860 {
0861     struct pci_dev *pdev = to_pci_dev(dev);
0862     struct ata_host *host = pci_get_drvdata(pdev);
0863
0864     ahci_pci_disable_interrupts(host);
0865     return 0;
0866 }
0867
0868 static int ahci_pci_device_runtime_resume(struct device *dev)
0869 {
0870     struct pci_dev *pdev = to_pci_dev(dev);
0871     struct ata_host *host = pci_get_drvdata(pdev);
0872     int rc;
0873
0874     rc = ahci_reset_controller(host);
0875     if (rc)
0876         return rc;
0877     ahci_pci_init_controller(host);
0878     return 0;
0879 }
0880
0881 #ifdef CONFIG_PM_SLEEP
0882 static int ahci_pci_device_suspend(struct device *dev)
0883 {
0884     struct pci_dev *pdev = to_pci_dev(dev);
0885     struct ata_host *host = pci_get_drvdata(pdev);
0886     struct ahci_host_priv *hpriv = host->private_data;
0887
0888     if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
0889         dev_err(&pdev->dev,
0890             "BIOS update required for suspend/resume\n");
0891         return -EIO;
0892     }
0893
0894     ahci_pci_disable_interrupts(host);
0895     ata_host_suspend(host, PMSG_SUSPEND);
0896     return 0;
0897 }
0898
0899 static int ahci_pci_device_resume(struct device *dev)
0900 {
0901     struct pci_dev *pdev = to_pci_dev(dev);
0902     struct ata_host *host = pci_get_drvdata(pdev);
0903     int rc;
0904
0905     /* Apple BIOS helpfully mangles the registers on resume */
0906     if (is_mcp89_apple(pdev))
0907         ahci_mcp89_apple_enable(pdev);
0908
0909     if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
0910         rc = ahci_reset_controller(host);
0911         if (rc)
0912             return rc;
0913
0914         ahci_pci_init_controller(host);
0915     }
0916
0917     ata_host_resume(host);
0918
0919     return 0;
0920 }
0921 #endif
0922
0923 #endif /* CONFIG_PM */
0924
0925 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
0926 {
0927     const int dma_bits = using_dac ? 64 : 32;
0928     int rc;
0929
0930     /*
0931      * If the device fixup already set the dma_mask to some non-standard
0932      * value, don't extend it here. This happens on STA2X11, for example.
0933      *
0934      * XXX: manipulating the DMA mask from platform code is completely
0935      * bogus, platform code should use dev->bus_dma_limit instead..
0936      */
0937     if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
0938         return 0;
0939
0940     rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits));
0941     if (rc)
0942         dev_err(&pdev->dev, "DMA enable failed\n");
0943     return rc;
0944 }
0945
0946 static void ahci_pci_print_info(struct ata_host *host)
0947 {
0948     struct pci_dev *pdev = to_pci_dev(host->dev);
0949     u16 cc;
0950     const char *scc_s;
0951
0952     pci_read_config_word(pdev, 0x0a, &cc);
0953     if (cc == PCI_CLASS_STORAGE_IDE)
0954         scc_s = "IDE";
0955     else if (cc == PCI_CLASS_STORAGE_SATA)
0956         scc_s = "SATA";
0957     else if (cc == PCI_CLASS_STORAGE_RAID)
0958         scc_s = "RAID";
0959     else
0960         scc_s = "unknown";
0961
0962     ahci_print_info(host, scc_s);
0963 }
0964
0965 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
0966  * hardwired to on-board SIMG 4726.  The chipset is ICH8 and doesn't
0967  * support PMP and the 4726 either directly exports the device
0968  * attached to the first downstream port or acts as a hardware storage
0969  * controller and emulate a single ATA device (can be RAID 0/1 or some
0970  * other configuration).
0971  *
0972  * When there's no device attached to the first downstream port of the
0973  * 4726, "Config Disk" appears, which is a pseudo ATA device to
0974  * configure the 4726.  However, ATA emulation of the device is very
0975  * lame.  It doesn't send signature D2H Reg FIS after the initial
0976  * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
0977  *
0978  * The following function works around the problem by always using
0979  * hardreset on the port and not depending on receiving signature FIS
0980  * afterward.  If signature FIS isn't received soon, ATA class is
0981  * assumed without follow-up softreset.
0982  */
0983 static void ahci_p5wdh_workaround(struct ata_host *host)
0984 {
0985     static const struct dmi_system_id sysids[] = {
0986         {
0987             .ident = "P5W DH Deluxe",
0988             .matches = {
0989                 DMI_MATCH(DMI_SYS_VENDOR,
0990                       "ASUSTEK COMPUTER INC"),
0991                 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
0992             },
0993         },
0994         { }
0995     };
0996     struct pci_dev *pdev = to_pci_dev(host->dev);
0997
0998     if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
0999         dmi_check_system(sysids)) {
1000         struct ata_port *ap = host->ports[1];
1001
1002         dev_info(&pdev->dev,
1003              "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
1004
1005         ap->ops = &ahci_p5wdh_ops;
1006         ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
1007     }
1008 }
1009
1010 /*
1011  * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
1012  * booting in BIOS compatibility mode.  We restore the registers but not ID.
1013  */
1014 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
1015 {
1016     u32 val;
1017
1018     printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1019
1020     pci_read_config_dword(pdev, 0xf8, &val);
1021     val |= 1 << 0x1b;
1022     /* the following changes the device ID, but appears not to affect function */
1023     /* val = (val & ~0xf0000000) | 0x80000000; */
1024     pci_write_config_dword(pdev, 0xf8, val);
1025
1026     pci_read_config_dword(pdev, 0x54c, &val);
1027     val |= 1 << 0xc;
1028     pci_write_config_dword(pdev, 0x54c, val);
1029
1030     pci_read_config_dword(pdev, 0x4a4, &val);
1031     val &= 0xff;
1032     val |= 0x01060100;
1033     pci_write_config_dword(pdev, 0x4a4, val);
1034
1035     pci_read_config_dword(pdev, 0x54c, &val);
1036     val &= ~(1 << 0xc);
1037     pci_write_config_dword(pdev, 0x54c, val);
1038
1039     pci_read_config_dword(pdev, 0xf8, &val);
1040     val &= ~(1 << 0x1b);
1041     pci_write_config_dword(pdev, 0xf8, val);
1042 }
1043
1044 static bool is_mcp89_apple(struct pci_dev *pdev)
1045 {
1046     return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1047         pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1048         pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1049         pdev->subsystem_device == 0xcb89;
1050 }
1051
1052 /* only some SB600 ahci controllers can do 64bit DMA */
1053 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1054 {
1055     static const struct dmi_system_id sysids[] = {
1056         /*
1057          * The oldest version known to be broken is 0901 and
1058          * working is 1501 which was released on 2007-10-26.
1059          * Enable 64bit DMA on 1501 and anything newer.
1060          *
1061          * Please read bko#9412 for more info.
1062          */
1063         {
1064             .ident = "ASUS M2A-VM",
1065             .matches = {
1066                 DMI_MATCH(DMI_BOARD_VENDOR,
1067                       "ASUSTeK Computer INC."),
1068                 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1069             },
1070             .driver_data = "20071026",  /* yyyymmdd */
1071         },
1072         /*
1073          * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1074          * support 64bit DMA.
1075          *
1076          * BIOS versions earlier than 1.5 had the Manufacturer DMI
1077          * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1078          * This spelling mistake was fixed in BIOS version 1.5, so
1079          * 1.5 and later have the Manufacturer as
1080          * "MICRO-STAR INTERNATIONAL CO.,LTD".
1081          * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1082          *
1083          * BIOS versions earlier than 1.9 had a Board Product Name
1084          * DMI field of "MS-7376". This was changed to be
1085          * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1086          * match on DMI_BOARD_NAME of "MS-7376".
1087          */
1088         {
1089             .ident = "MSI K9A2 Platinum",
1090             .matches = {
1091                 DMI_MATCH(DMI_BOARD_VENDOR,
1092                       "MICRO-STAR INTER"),
1093                 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1094             },
1095         },
1096         /*
1097          * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1098          * 64bit DMA.
1099          *
1100          * This board also had the typo mentioned above in the
1101          * Manufacturer DMI field (fixed in BIOS version 1.5), so
1102          * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1103          */
1104         {
1105             .ident = "MSI K9AGM2",
1106             .matches = {
1107                 DMI_MATCH(DMI_BOARD_VENDOR,
1108                       "MICRO-STAR INTER"),
1109                 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1110             },
1111         },
1112         /*
1113          * All BIOS versions for the Asus M3A support 64bit DMA.
1114          * (all release versions from 0301 to 1206 were tested)
1115          */
1116         {
1117             .ident = "ASUS M3A",
1118             .matches = {
1119                 DMI_MATCH(DMI_BOARD_VENDOR,
1120                       "ASUSTeK Computer INC."),
1121                 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1122             },
1123         },
1124         { }
1125     };
1126     const struct dmi_system_id *match;
1127     int year, month, date;
1128     char buf[9];
1129
1130     match = dmi_first_match(sysids);
1131     if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1132         !match)
1133         return false;
1134
1135     if (!match->driver_data)
1136         goto enable_64bit;
1137
1138     dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1139     snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1140
1141     if (strcmp(buf, match->driver_data) >= 0)
1142         goto enable_64bit;
1143     else {
1144         dev_warn(&pdev->dev,
1145              "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1146              match->ident);
1147         return false;
1148     }
1149
1150 enable_64bit:
1151     dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1152     return true;
1153 }
1154
1155 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1156 {
1157     static const struct dmi_system_id broken_systems[] = {
1158         {
1159             .ident = "HP Compaq nx6310",
1160             .matches = {
1161                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1162                 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1163             },
1164             /* PCI slot number of the controller */
1165             .driver_data = (void *)0x1FUL,
1166         },
1167         {
1168             .ident = "HP Compaq 6720s",
1169             .matches = {
1170                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1171                 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1172             },
1173             /* PCI slot number of the controller */
1174             .driver_data = (void *)0x1FUL,
1175         },
1176
1177         { } /* terminate list */
1178     };
1179     const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1180
1181     if (dmi) {
1182         unsigned long slot = (unsigned long)dmi->driver_data;
1183         /* apply the quirk only to on-board controllers */
1184         return slot == PCI_SLOT(pdev->devfn);
1185     }
1186
1187     return false;
1188 }
1189
1190 static bool ahci_broken_suspend(struct pci_dev *pdev)
1191 {
1192     static const struct dmi_system_id sysids[] = {
1193         /*
1194          * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1195          * to the harddisk doesn't become online after
1196          * resuming from STR.  Warn and fail suspend.
1197          *
1198          * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1199          *
1200          * Use dates instead of versions to match as HP is
1201          * apparently recycling both product and version
1202          * strings.
1203          *
1204          * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1205          */
1206         {
1207             .ident = "dv4",
1208             .matches = {
1209                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1210                 DMI_MATCH(DMI_PRODUCT_NAME,
1211                       "HP Pavilion dv4 Notebook PC"),
1212             },
1213             .driver_data = "20090105",  /* F.30 */
1214         },
1215         {
1216             .ident = "dv5",
1217             .matches = {
1218                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1219                 DMI_MATCH(DMI_PRODUCT_NAME,
1220                       "HP Pavilion dv5 Notebook PC"),
1221             },
1222             .driver_data = "20090506",  /* F.16 */
1223         },
1224         {
1225             .ident = "dv6",
1226             .matches = {
1227                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1228                 DMI_MATCH(DMI_PRODUCT_NAME,
1229                       "HP Pavilion dv6 Notebook PC"),
1230             },
1231             .driver_data = "20090423",  /* F.21 */
1232         },
1233         {
1234             .ident = "HDX18",
1235             .matches = {
1236                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1237                 DMI_MATCH(DMI_PRODUCT_NAME,
1238                       "HP HDX18 Notebook PC"),
1239             },
1240             .driver_data = "20090430",  /* F.23 */
1241         },
1242         /*
1243          * Acer eMachines G725 has the same problem.  BIOS
1244          * V1.03 is known to be broken.  V3.04 is known to
1245          * work.  Between, there are V1.06, V2.06 and V3.03
1246          * that we don't have much idea about.  For now,
1247          * blacklist anything older than V3.04.
1248          *
1249          * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1250          */
1251         {
1252             .ident = "G725",
1253             .matches = {
1254                 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1255                 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1256             },
1257             .driver_data = "20091216",  /* V3.04 */
1258         },
1259         { } /* terminate list */
1260     };
1261     const struct dmi_system_id *dmi = dmi_first_match(sysids);
1262     int year, month, date;
1263     char buf[9];
1264
1265     if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1266         return false;
1267
1268     dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1269     snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1270
1271     return strcmp(buf, dmi->driver_data) < 0;
1272 }
1273
1274 static bool ahci_broken_lpm(struct pci_dev *pdev)
1275 {
1276     static const struct dmi_system_id sysids[] = {
1277         /* Various Lenovo 50 series have LPM issues with older BIOSen */
1278         {
1279             .matches = {
1280                 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1281                 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X250"),
1282             },
1283             .driver_data = "20180406", /* 1.31 */
1284         },
1285         {
1286             .matches = {
1287                 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1288                 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L450"),
1289             },
1290             .driver_data = "20180420", /* 1.28 */
1291         },
1292         {
1293             .matches = {
1294                 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1295                 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T450s"),
1296             },
1297             .driver_data = "20180315", /* 1.33 */
1298         },
1299         {
1300             .matches = {
1301                 DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
1302                 DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad W541"),
1303             },
1304             /*
1305              * Note date based on release notes, 2.35 has been
1306              * reported to be good, but I've been unable to get
1307              * a hold of the reporter to get the DMI BIOS date.
1308              * TODO: fix this.
1309              */
1310             .driver_data = "20180310", /* 2.35 */
1311         },
1312         { } /* terminate list */
1313     };
1314     const struct dmi_system_id *dmi = dmi_first_match(sysids);
1315     int year, month, date;
1316     char buf[9];
1317
1318     if (!dmi)
1319         return false;
1320
1321     dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1322     snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1323
1324     return strcmp(buf, dmi->driver_data) < 0;
1325 }
1326
1327 static bool ahci_broken_online(struct pci_dev *pdev)
1328 {
1329 #define ENCODE_BUSDEVFN(bus, slot, func)            \
1330     (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1331     static const struct dmi_system_id sysids[] = {
1332         /*
1333          * There are several gigabyte boards which use
1334          * SIMG5723s configured as hardware RAID.  Certain
1335          * 5723 firmware revisions shipped there keep the link
1336          * online but fail to answer properly to SRST or
1337          * IDENTIFY when no device is attached downstream
1338          * causing libata to retry quite a few times leading
1339          * to excessive detection delay.
1340          *
1341          * As these firmwares respond to the second reset try
1342          * with invalid device signature, considering unknown
1343          * sig as offline works around the problem acceptably.
1344          */
1345         {
1346             .ident = "EP45-DQ6",
1347             .matches = {
1348                 DMI_MATCH(DMI_BOARD_VENDOR,
1349                       "Gigabyte Technology Co., Ltd."),
1350                 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1351             },
1352             .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1353         },
1354         {
1355             .ident = "EP45-DS5",
1356             .matches = {
1357                 DMI_MATCH(DMI_BOARD_VENDOR,
1358                       "Gigabyte Technology Co., Ltd."),
1359                 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1360             },
1361             .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1362         },
1363         { } /* terminate list */
1364     };
1365 #undef ENCODE_BUSDEVFN
1366     const struct dmi_system_id *dmi = dmi_first_match(sysids);
1367     unsigned int val;
1368
1369     if (!dmi)
1370         return false;
1371
1372     val = (unsigned long)dmi->driver_data;
1373
1374     return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1375 }
1376
1377 static bool ahci_broken_devslp(struct pci_dev *pdev)
1378 {
1379     /* device with broken DEVSLP but still showing SDS capability */
1380     static const struct pci_device_id ids[] = {
1381         { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1382         {}
1383     };
1384
1385     return pci_match_id(ids, pdev);
1386 }
1387
1388 #ifdef CONFIG_ATA_ACPI
1389 static void ahci_gtf_filter_workaround(struct ata_host *host)
1390 {
1391     static const struct dmi_system_id sysids[] = {
1392         /*
1393          * Aspire 3810T issues a bunch of SATA enable commands
1394          * via _GTF including an invalid one and one which is
1395          * rejected by the device.  Among the successful ones
1396          * is FPDMA non-zero offset enable which when enabled
1397          * only on the drive side leads to NCQ command
1398          * failures.  Filter it out.
1399          */
1400         {
1401             .ident = "Aspire 3810T",
1402             .matches = {
1403                 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1404                 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1405             },
1406             .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1407         },
1408         { }
1409     };
1410     const struct dmi_system_id *dmi = dmi_first_match(sysids);
1411     unsigned int filter;
1412     int i;
1413
1414     if (!dmi)
1415         return;
1416
1417     filter = (unsigned long)dmi->driver_data;
1418     dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1419          filter, dmi->ident);
1420
1421     for (i = 0; i < host->n_ports; i++) {
1422         struct ata_port *ap = host->ports[i];
1423         struct ata_link *link;
1424         struct ata_device *dev;
1425
1426         ata_for_each_link(link, ap, EDGE)
1427             ata_for_each_dev(dev, link, ALL)
1428                 dev->gtf_filter |= filter;
1429     }
1430 }
1431 #else
1432 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1433 {}
1434 #endif
1435
1436 /*
1437  * On the Acer Aspire Switch Alpha 12, sometimes all SATA ports are detected
1438  * as DUMMY, or detected but eventually get a "link down" and never get up
1439  * again. When this happens, CAP.NP may hold a value of 0x00 or 0x01, and the
1440  * port_map may hold a value of 0x00.
1441  *
1442  * Overriding CAP.NP to 0x02 and the port_map to 0x7 will reveal all 3 ports
1443  * and can significantly reduce the occurrence of the problem.
1444  *
1445  * https://bugzilla.kernel.org/show_bug.cgi?id=189471
1446  */
1447 static void acer_sa5_271_workaround(struct ahci_host_priv *hpriv,
1448                     struct pci_dev *pdev)
1449 {
1450     static const struct dmi_system_id sysids[] = {
1451         {
1452             .ident = "Acer Switch Alpha 12",
1453             .matches = {
1454                 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1455                 DMI_MATCH(DMI_PRODUCT_NAME, "Switch SA5-271")
1456             },
1457         },
1458         { }
1459     };
1460
1461     if (dmi_check_system(sysids)) {
1462         dev_info(&pdev->dev, "enabling Acer Switch Alpha 12 workaround\n");
1463         if ((hpriv->saved_cap & 0xC734FF00) == 0xC734FF00) {
1464             hpriv->port_map = 0x7;
1465             hpriv->cap = 0xC734FF02;
1466         }
1467     }
1468 }
1469
1470 #ifdef CONFIG_ARM64
1471 /*
1472  * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1473  * Workaround is to make sure all pending IRQs are served before leaving
1474  * handler.
1475  */
1476 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1477 {
1478     struct ata_host *host = dev_instance;
1479     struct ahci_host_priv *hpriv;
1480     unsigned int rc = 0;
1481     void __iomem *mmio;
1482     u32 irq_stat, irq_masked;
1483     unsigned int handled = 1;
1484
1485     hpriv = host->private_data;
1486     mmio = hpriv->mmio;
1487     irq_stat = readl(mmio + HOST_IRQ_STAT);
1488     if (!irq_stat)
1489         return IRQ_NONE;
1490
1491     do {
1492         irq_masked = irq_stat & hpriv->port_map;
1493         spin_lock(&host->lock);
1494         rc = ahci_handle_port_intr(host, irq_masked);
1495         if (!rc)
1496             handled = 0;
1497         writel(irq_stat, mmio + HOST_IRQ_STAT);
1498         irq_stat = readl(mmio + HOST_IRQ_STAT);
1499         spin_unlock(&host->lock);
1500     } while (irq_stat);
1501
1502     return IRQ_RETVAL(handled);
1503 }
1504 #endif
1505
1506 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1507         struct ahci_host_priv *hpriv)
1508 {
1509     int i;
1510     u32 cap;
1511
1512     /*
1513      * Check if this device might have remapped nvme devices.
1514      */
1515     if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1516         pci_resource_len(pdev, bar) < SZ_512K ||
1517         bar != AHCI_PCI_BAR_STANDARD ||
1518         !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1519         return;
1520
1521     cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1522     for (i = 0; i < AHCI_MAX_REMAP; i++) {
1523         if ((cap & (1 << i)) == 0)
1524             continue;
1525         if (readl(hpriv->mmio + ahci_remap_dcc(i))
1526                 != PCI_CLASS_STORAGE_EXPRESS)
1527             continue;
1528
1529         /* We've found a remapped device */
1530         hpriv->remapped_nvme++;
1531     }
1532
1533     if (!hpriv->remapped_nvme)
1534         return;
1535
1536     dev_warn(&pdev->dev, "Found %u remapped NVMe devices.\n",
1537          hpriv->remapped_nvme);
1538     dev_warn(&pdev->dev,
1539          "Switch your BIOS from RAID to AHCI mode to use them.\n");
1540
1541     /*
1542      * Don't rely on the msi-x capability in the remap case,
1543      * share the legacy interrupt across ahci and remapped devices.
1544      */
1545     hpriv->flags |= AHCI_HFLAG_NO_MSI;
1546 }
1547
1548 static int ahci_get_irq_vector(struct ata_host *host, int port)
1549 {
1550     return pci_irq_vector(to_pci_dev(host->dev), port);
1551 }
1552
1553 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1554             struct ahci_host_priv *hpriv)
1555 {
1556     int nvec;
1557
1558     if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1559         return -ENODEV;
1560
1561     /*
1562      * If number of MSIs is less than number of ports then Sharing Last
1563      * Message mode could be enforced. In this case assume that advantage
1564      * of multipe MSIs is negated and use single MSI mode instead.
1565      */
1566     if (n_ports > 1) {
1567         nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1568                 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1569         if (nvec > 0) {
1570             if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1571                 hpriv->get_irq_vector = ahci_get_irq_vector;
1572                 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1573                 return nvec;
1574             }
1575
1576             /*
1577              * Fallback to single MSI mode if the controller
1578              * enforced MRSM mode.
1579              */
1580             printk(KERN_INFO
1581                 "ahci: MRSM is on, fallback to single MSI\n");
1582             pci_free_irq_vectors(pdev);
1583         }
1584     }
1585
1586     /*
1587      * If the host is not capable of supporting per-port vectors, fall
1588      * back to single MSI before finally attempting single MSI-X.
1589      */
1590     nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1591     if (nvec == 1)
1592         return nvec;
1593     return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1594 }
1595
1596 static void ahci_update_initial_lpm_policy(struct ata_port *ap,
1597                        struct ahci_host_priv *hpriv)
1598 {
1599     int policy = CONFIG_SATA_MOBILE_LPM_POLICY;
1600
1601
1602     /* Ignore processing for chipsets that don't use policy */
1603     if (!(hpriv->flags & AHCI_HFLAG_USE_LPM_POLICY))
1604         return;
1605
1606     /* user modified policy via module param */
1607     if (mobile_lpm_policy != -1) {
1608         policy = mobile_lpm_policy;
1609         goto update_policy;
1610     }
1611
1612 #ifdef CONFIG_ACPI
1613     if (policy > ATA_LPM_MED_POWER &&
1614         (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0)) {
1615         if (hpriv->cap & HOST_CAP_PART)
1616             policy = ATA_LPM_MIN_POWER_WITH_PARTIAL;
1617         else if (hpriv->cap & HOST_CAP_SSC)
1618             policy = ATA_LPM_MIN_POWER;
1619     }
1620 #endif
1621
1622 update_policy:
1623     if (policy >= ATA_LPM_UNKNOWN && policy <= ATA_LPM_MIN_POWER)
1624         ap->target_lpm_policy = policy;
1625 }
1626
1627 static void ahci_intel_pcs_quirk(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1628 {
1629     const struct pci_device_id *id = pci_match_id(ahci_pci_tbl, pdev);
1630     u16 tmp16;
1631
1632     /*
1633      * Only apply the 6-port PCS quirk for known legacy platforms.
1634      */
1635     if (!id || id->vendor != PCI_VENDOR_ID_INTEL)
1636         return;
1637
1638     /* Skip applying the quirk on Denverton and beyond */
1639     if (((enum board_ids) id->driver_data) >= board_ahci_pcs7)
1640         return;
1641
1642     /*
1643      * port_map is determined from PORTS_IMPL PCI register which is
1644      * implemented as write or write-once register.  If the register
1645      * isn't programmed, ahci automatically generates it from number
1646      * of ports, which is good enough for PCS programming. It is
1647      * otherwise expected that platform firmware enables the ports
1648      * before the OS boots.
1649      */
1650     pci_read_config_word(pdev, PCS_6, &tmp16);
1651     if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1652         tmp16 |= hpriv->port_map;
1653         pci_write_config_word(pdev, PCS_6, tmp16);
1654     }
1655 }
1656
1657 static ssize_t remapped_nvme_show(struct device *dev,
1658                   struct device_attribute *attr,
1659                   char *buf)
1660 {
1661     struct ata_host *host = dev_get_drvdata(dev);
1662     struct ahci_host_priv *hpriv = host->private_data;
1663
1664     return sysfs_emit(buf, "%u\n", hpriv->remapped_nvme);
1665 }
1666
1667 static DEVICE_ATTR_RO(remapped_nvme);
1668
1669 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1670 {
1671     unsigned int board_id = ent->driver_data;
1672     struct ata_port_info pi = ahci_port_info[board_id];
1673     const struct ata_port_info *ppi[] = { &pi, NULL };
1674     struct device *dev = &pdev->dev;
1675     struct ahci_host_priv *hpriv;
1676     struct ata_host *host;
1677     int n_ports, i, rc;
1678     int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1679
1680     WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1681
1682     ata_print_version_once(&pdev->dev, DRV_VERSION);
1683
1684     /* The AHCI driver can only drive the SATA ports, the PATA driver
1685        can drive them all so if both drivers are selected make sure
1686        AHCI stays out of the way */
1687     if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1688         return -ENODEV;
1689
1690     /* Apple BIOS on MCP89 prevents us using AHCI */
1691     if (is_mcp89_apple(pdev))
1692         ahci_mcp89_apple_enable(pdev);
1693
1694     /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1695      * At the moment, we can only use the AHCI mode. Let the users know
1696      * that for SAS drives they're out of luck.
1697      */
1698     if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1699         dev_info(&pdev->dev,
1700              "PDC42819 can only drive SATA devices with this driver\n");
1701
1702     /* Some devices use non-standard BARs */
1703     if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1704         ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1705     else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1706         ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1707     else if (pdev->vendor == PCI_VENDOR_ID_CAVIUM) {
1708         if (pdev->device == 0xa01c)
1709             ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1710         if (pdev->device == 0xa084)
1711             ahci_pci_bar = AHCI_PCI_BAR_CAVIUM_GEN5;
1712     } else if (pdev->vendor == PCI_VENDOR_ID_LOONGSON) {
1713         if (pdev->device == 0x7a08)
1714             ahci_pci_bar = AHCI_PCI_BAR_LOONGSON;
1715     }
1716
1717     /* acquire resources */
1718     rc = pcim_enable_device(pdev);
1719     if (rc)
1720         return rc;
1721
1722     if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1723         (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1724         u8 map;
1725
1726         /* ICH6s share the same PCI ID for both piix and ahci
1727          * modes.  Enabling ahci mode while MAP indicates
1728          * combined mode is a bad idea.  Yield to ata_piix.
1729          */
1730         pci_read_config_byte(pdev, ICH_MAP, &map);
1731         if (map & 0x3) {
1732             dev_info(&pdev->dev,
1733                  "controller is in combined mode, can't enable AHCI mode\n");
1734             return -ENODEV;
1735         }
1736     }
1737
1738     /* AHCI controllers often implement SFF compatible interface.
1739      * Grab all PCI BARs just in case.
1740      */
1741     rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1742     if (rc == -EBUSY)
1743         pcim_pin_device(pdev);
1744     if (rc)
1745         return rc;
1746
1747     hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1748     if (!hpriv)
1749         return -ENOMEM;
1750     hpriv->flags |= (unsigned long)pi.private_data;
1751
1752     /* MCP65 revision A1 and A2 can't do MSI */
1753     if (board_id == board_ahci_mcp65 &&
1754         (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1755         hpriv->flags |= AHCI_HFLAG_NO_MSI;
1756
1757     /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1758     if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1759         hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1760
1761     /* only some SB600s can do 64bit DMA */
1762     if (ahci_sb600_enable_64bit(pdev))
1763         hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1764
1765     hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1766
1767     /* detect remapped nvme devices */
1768     ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1769
1770     sysfs_add_file_to_group(&pdev->dev.kobj,
1771                 &dev_attr_remapped_nvme.attr,
1772                 NULL);
1773
1774     /* must set flag prior to save config in order to take effect */
1775     if (ahci_broken_devslp(pdev))
1776         hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1777
1778 #ifdef CONFIG_ARM64
1779     if (pdev->vendor == PCI_VENDOR_ID_HUAWEI &&
1780         pdev->device == 0xa235 &&
1781         pdev->revision < 0x30)
1782         hpriv->flags |= AHCI_HFLAG_NO_SXS;
1783
1784     if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1785         hpriv->irq_handler = ahci_thunderx_irq_handler;
1786 #endif
1787
1788     /* save initial config */
1789     ahci_pci_save_initial_config(pdev, hpriv);
1790
1791     /*
1792      * If platform firmware failed to enable ports, try to enable
1793      * them here.
1794      */
1795     ahci_intel_pcs_quirk(pdev, hpriv);
1796
1797     /* prepare host */
1798     if (hpriv->cap & HOST_CAP_NCQ) {
1799         pi.flags |= ATA_FLAG_NCQ;
1800         /*
1801          * Auto-activate optimization is supposed to be
1802          * supported on all AHCI controllers indicating NCQ
1803          * capability, but it seems to be broken on some
1804          * chipsets including NVIDIAs.
1805          */
1806         if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1807             pi.flags |= ATA_FLAG_FPDMA_AA;
1808
1809         /*
1810          * All AHCI controllers should be forward-compatible
1811          * with the new auxiliary field. This code should be
1812          * conditionalized if any buggy AHCI controllers are
1813          * encountered.
1814          */
1815         pi.flags |= ATA_FLAG_FPDMA_AUX;
1816     }
1817
1818     if (hpriv->cap & HOST_CAP_PMP)
1819         pi.flags |= ATA_FLAG_PMP;
1820
1821     ahci_set_em_messages(hpriv, &pi);
1822
1823     if (ahci_broken_system_poweroff(pdev)) {
1824         pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1825         dev_info(&pdev->dev,
1826             "quirky BIOS, skipping spindown on poweroff\n");
1827     }
1828
1829     if (ahci_broken_lpm(pdev)) {
1830         pi.flags |= ATA_FLAG_NO_LPM;
1831         dev_warn(&pdev->dev,
1832              "BIOS update required for Link Power Management support\n");
1833     }
1834
1835     if (ahci_broken_suspend(pdev)) {
1836         hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1837         dev_warn(&pdev->dev,
1838              "BIOS update required for suspend/resume\n");
1839     }
1840
1841     if (ahci_broken_online(pdev)) {
1842         hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1843         dev_info(&pdev->dev,
1844              "online status unreliable, applying workaround\n");
1845     }
1846
1847
1848     /* Acer SA5-271 workaround modifies private_data */
1849     acer_sa5_271_workaround(hpriv, pdev);
1850
1851     /* CAP.NP sometimes indicate the index of the last enabled
1852      * port, at other times, that of the last possible port, so
1853      * determining the maximum port number requires looking at
1854      * both CAP.NP and port_map.
1855      */
1856     n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1857
1858     host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1859     if (!host)
1860         return -ENOMEM;
1861     host->private_data = hpriv;
1862
1863     if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1864         /* legacy intx interrupts */
1865         pci_intx(pdev, 1);
1866     }
1867     hpriv->irq = pci_irq_vector(pdev, 0);
1868
1869     if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1870         host->flags |= ATA_HOST_PARALLEL_SCAN;
1871     else
1872         dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1873
1874     if (pi.flags & ATA_FLAG_EM)
1875         ahci_reset_em(host);
1876
1877     for (i = 0; i < host->n_ports; i++) {
1878         struct ata_port *ap = host->ports[i];
1879
1880         ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1881         ata_port_pbar_desc(ap, ahci_pci_bar,
1882                    0x100 + ap->port_no * 0x80, "port");
1883
1884         /* set enclosure management message type */
1885         if (ap->flags & ATA_FLAG_EM)
1886             ap->em_message_type = hpriv->em_msg_type;
1887
1888         ahci_update_initial_lpm_policy(ap, hpriv);
1889
1890         /* disabled/not-implemented port */
1891         if (!(hpriv->port_map & (1 << i)))
1892             ap->ops = &ata_dummy_port_ops;
1893     }
1894
1895     /* apply workaround for ASUS P5W DH Deluxe mainboard */
1896     ahci_p5wdh_workaround(host);
1897
1898     /* apply gtf filter quirk */
1899     ahci_gtf_filter_workaround(host);
1900
1901     /* initialize adapter */
1902     rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1903     if (rc)
1904         return rc;
1905
1906     rc = ahci_reset_controller(host);
1907     if (rc)
1908         return rc;
1909
1910     ahci_pci_init_controller(host);
1911     ahci_pci_print_info(host);
1912
1913     pci_set_master(pdev);
1914
1915     rc = ahci_host_activate(host, &ahci_sht);
1916     if (rc)
1917         return rc;
1918
1919     pm_runtime_put_noidle(&pdev->dev);
1920     return 0;
1921 }
1922
1923 static void ahci_shutdown_one(struct pci_dev *pdev)
1924 {
1925     ata_pci_shutdown_one(pdev);
1926 }
1927
1928 static void ahci_remove_one(struct pci_dev *pdev)
1929 {
1930     sysfs_remove_file_from_group(&pdev->dev.kobj,
1931                      &dev_attr_remapped_nvme.attr,
1932                      NULL);
1933     pm_runtime_get_noresume(&pdev->dev);
1934     ata_pci_remove_one(pdev);
1935 }
1936
1937 module_pci_driver(ahci_pci_driver);
1938
1939 MODULE_AUTHOR("Jeff Garzik");
1940 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1941 MODULE_LICENSE("GPL");
1942 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1943 MODULE_VERSION(DRV_VERSION);