drivers/ata/acard-ahci.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002
0003 /*
0004  *  acard-ahci.c - ACard AHCI SATA support
0005  *
0006  *  Maintained by:  Tejun Heo <tj@kernel.org>
0007  *          Please ALWAYS copy linux-ide@vger.kernel.org
0008  *          on emails.
0009  *
0010  *  Copyright 2010 Red Hat, Inc.
0011  *
0012  * libata documentation is available via 'make {ps|pdf}docs',
0013  * as Documentation/driver-api/libata.rst
0014  *
0015  * AHCI hardware documentation:
0016  * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
0017  * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
0018  */
0019
0020 #include <linux/kernel.h>
0021 #include <linux/module.h>
0022 #include <linux/pci.h>
0023 #include <linux/blkdev.h>
0024 #include <linux/delay.h>
0025 #include <linux/interrupt.h>
0026 #include <linux/dma-mapping.h>
0027 #include <linux/device.h>
0028 #include <linux/dmi.h>
0029 #include <linux/gfp.h>
0030 #include <scsi/scsi_host.h>
0031 #include <scsi/scsi_cmnd.h>
0032 #include <linux/libata.h>
0033 #include "ahci.h"
0034
0035 #define DRV_NAME    "acard-ahci"
0036 #define DRV_VERSION "1.0"
0037
0038 /*
0039   Received FIS structure limited to 80h.
0040 */
0041
0042 #define ACARD_AHCI_RX_FIS_SZ 128
0043
0044 enum {
0045     AHCI_PCI_BAR        = 5,
0046 };
0047
0048 enum board_ids {
0049     board_acard_ahci,
0050 };
0051
0052 struct acard_sg {
0053     __le32          addr;
0054     __le32          addr_hi;
0055     __le32          reserved;
0056     __le32          size;    /* bit 31 (EOT) max==0x10000 (64k) */
0057 };
0058
0059 static enum ata_completion_errors acard_ahci_qc_prep(struct ata_queued_cmd *qc);
0060 static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
0061 static int acard_ahci_port_start(struct ata_port *ap);
0062 static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
0063
0064 #ifdef CONFIG_PM_SLEEP
0065 static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
0066 static int acard_ahci_pci_device_resume(struct pci_dev *pdev);
0067 #endif
0068
0069 static struct scsi_host_template acard_ahci_sht = {
0070     AHCI_SHT("acard-ahci"),
0071 };
0072
0073 static struct ata_port_operations acard_ops = {
0074     .inherits       = &ahci_ops,
0075     .qc_prep        = acard_ahci_qc_prep,
0076     .qc_fill_rtf        = acard_ahci_qc_fill_rtf,
0077     .port_start             = acard_ahci_port_start,
0078 };
0079
0080 #define AHCI_HFLAGS(flags)  .private_data   = (void *)(flags)
0081
0082 static const struct ata_port_info acard_ahci_port_info[] = {
0083     [board_acard_ahci] =
0084     {
0085         AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
0086         .flags      = AHCI_FLAG_COMMON,
0087         .pio_mask   = ATA_PIO4,
0088         .udma_mask  = ATA_UDMA6,
0089         .port_ops   = &acard_ops,
0090     },
0091 };
0092
0093 static const struct pci_device_id acard_ahci_pci_tbl[] = {
0094     /* ACard */
0095     { PCI_VDEVICE(ARTOP, 0x000d), board_acard_ahci }, /* ATP8620 */
0096
0097     { }    /* terminate list */
0098 };
0099
0100 static struct pci_driver acard_ahci_pci_driver = {
0101     .name           = DRV_NAME,
0102     .id_table       = acard_ahci_pci_tbl,
0103     .probe          = acard_ahci_init_one,
0104     .remove         = ata_pci_remove_one,
0105 #ifdef CONFIG_PM_SLEEP
0106     .suspend        = acard_ahci_pci_device_suspend,
0107     .resume         = acard_ahci_pci_device_resume,
0108 #endif
0109 };
0110
0111 #ifdef CONFIG_PM_SLEEP
0112 static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
0113 {
0114     struct ata_host *host = pci_get_drvdata(pdev);
0115     struct ahci_host_priv *hpriv = host->private_data;
0116     void __iomem *mmio = hpriv->mmio;
0117     u32 ctl;
0118
0119     if (mesg.event & PM_EVENT_SUSPEND &&
0120         hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
0121         dev_err(&pdev->dev,
0122             "BIOS update required for suspend/resume\n");
0123         return -EIO;
0124     }
0125
0126     if (mesg.event & PM_EVENT_SLEEP) {
0127         /* AHCI spec rev1.1 section 8.3.3:
0128          * Software must disable interrupts prior to requesting a
0129          * transition of the HBA to D3 state.
0130          */
0131         ctl = readl(mmio + HOST_CTL);
0132         ctl &= ~HOST_IRQ_EN;
0133         writel(ctl, mmio + HOST_CTL);
0134         readl(mmio + HOST_CTL); /* flush */
0135     }
0136
0137     return ata_pci_device_suspend(pdev, mesg);
0138 }
0139
0140 static int acard_ahci_pci_device_resume(struct pci_dev *pdev)
0141 {
0142     struct ata_host *host = pci_get_drvdata(pdev);
0143     int rc;
0144
0145     rc = ata_pci_device_do_resume(pdev);
0146     if (rc)
0147         return rc;
0148
0149     if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
0150         rc = ahci_reset_controller(host);
0151         if (rc)
0152             return rc;
0153
0154         ahci_init_controller(host);
0155     }
0156
0157     ata_host_resume(host);
0158
0159     return 0;
0160 }
0161 #endif
0162
0163 static void acard_ahci_pci_print_info(struct ata_host *host)
0164 {
0165     struct pci_dev *pdev = to_pci_dev(host->dev);
0166     u16 cc;
0167     const char *scc_s;
0168
0169     pci_read_config_word(pdev, 0x0a, &cc);
0170     if (cc == PCI_CLASS_STORAGE_IDE)
0171         scc_s = "IDE";
0172     else if (cc == PCI_CLASS_STORAGE_SATA)
0173         scc_s = "SATA";
0174     else if (cc == PCI_CLASS_STORAGE_RAID)
0175         scc_s = "RAID";
0176     else
0177         scc_s = "unknown";
0178
0179     ahci_print_info(host, scc_s);
0180 }
0181
0182 static unsigned int acard_ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
0183 {
0184     struct scatterlist *sg;
0185     struct acard_sg *acard_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
0186     unsigned int si, last_si = 0;
0187
0188     /*
0189      * Next, the S/G list.
0190      */
0191     for_each_sg(qc->sg, sg, qc->n_elem, si) {
0192         dma_addr_t addr = sg_dma_address(sg);
0193         u32 sg_len = sg_dma_len(sg);
0194
0195         /*
0196          * ACard note:
0197          * We must set an end-of-table (EOT) bit,
0198          * and the segment cannot exceed 64k (0x10000)
0199          */
0200         acard_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
0201         acard_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
0202         acard_sg[si].size = cpu_to_le32(sg_len);
0203         last_si = si;
0204     }
0205
0206     acard_sg[last_si].size |= cpu_to_le32(1 << 31); /* set EOT */
0207
0208     return si;
0209 }
0210
0211 static enum ata_completion_errors acard_ahci_qc_prep(struct ata_queued_cmd *qc)
0212 {
0213     struct ata_port *ap = qc->ap;
0214     struct ahci_port_priv *pp = ap->private_data;
0215     int is_atapi = ata_is_atapi(qc->tf.protocol);
0216     void *cmd_tbl;
0217     u32 opts;
0218     const u32 cmd_fis_len = 5; /* five dwords */
0219
0220     /*
0221      * Fill in command table information.  First, the header,
0222      * a SATA Register - Host to Device command FIS.
0223      */
0224     cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
0225
0226     ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
0227     if (is_atapi) {
0228         memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
0229         memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
0230     }
0231
0232     if (qc->flags & ATA_QCFLAG_DMAMAP)
0233         acard_ahci_fill_sg(qc, cmd_tbl);
0234
0235     /*
0236      * Fill in command slot information.
0237      *
0238      * ACard note: prd table length not filled in
0239      */
0240     opts = cmd_fis_len | (qc->dev->link->pmp << 12);
0241     if (qc->tf.flags & ATA_TFLAG_WRITE)
0242         opts |= AHCI_CMD_WRITE;
0243     if (is_atapi)
0244         opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
0245
0246     ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
0247
0248     return AC_ERR_OK;
0249 }
0250
0251 static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
0252 {
0253     struct ahci_port_priv *pp = qc->ap->private_data;
0254     u8 *rx_fis = pp->rx_fis;
0255
0256     if (pp->fbs_enabled)
0257         rx_fis += qc->dev->link->pmp * ACARD_AHCI_RX_FIS_SZ;
0258
0259     /*
0260      * After a successful execution of an ATA PIO data-in command,
0261      * the device doesn't send D2H Reg FIS to update the TF and
0262      * the host should take TF and E_Status from the preceding PIO
0263      * Setup FIS.
0264      */
0265     if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
0266         !(qc->flags & ATA_QCFLAG_FAILED)) {
0267         ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
0268         qc->result_tf.status = (rx_fis + RX_FIS_PIO_SETUP)[15];
0269     } else
0270         ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
0271
0272     return true;
0273 }
0274
0275 static int acard_ahci_port_start(struct ata_port *ap)
0276 {
0277     struct ahci_host_priv *hpriv = ap->host->private_data;
0278     struct device *dev = ap->host->dev;
0279     struct ahci_port_priv *pp;
0280     void *mem;
0281     dma_addr_t mem_dma;
0282     size_t dma_sz, rx_fis_sz;
0283
0284     pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
0285     if (!pp)
0286         return -ENOMEM;
0287
0288     /* check FBS capability */
0289     if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
0290         void __iomem *port_mmio = ahci_port_base(ap);
0291         u32 cmd = readl(port_mmio + PORT_CMD);
0292         if (cmd & PORT_CMD_FBSCP)
0293             pp->fbs_supported = true;
0294         else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
0295             dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
0296                  ap->port_no);
0297             pp->fbs_supported = true;
0298         } else
0299             dev_warn(dev, "port %d is not capable of FBS\n",
0300                  ap->port_no);
0301     }
0302
0303     if (pp->fbs_supported) {
0304         dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
0305         rx_fis_sz = ACARD_AHCI_RX_FIS_SZ * 16;
0306     } else {
0307         dma_sz = AHCI_PORT_PRIV_DMA_SZ;
0308         rx_fis_sz = ACARD_AHCI_RX_FIS_SZ;
0309     }
0310
0311     mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
0312     if (!mem)
0313         return -ENOMEM;
0314
0315     /*
0316      * First item in chunk of DMA memory: 32-slot command table,
0317      * 32 bytes each in size
0318      */
0319     pp->cmd_slot = mem;
0320     pp->cmd_slot_dma = mem_dma;
0321
0322     mem += AHCI_CMD_SLOT_SZ;
0323     mem_dma += AHCI_CMD_SLOT_SZ;
0324
0325     /*
0326      * Second item: Received-FIS area
0327      */
0328     pp->rx_fis = mem;
0329     pp->rx_fis_dma = mem_dma;
0330
0331     mem += rx_fis_sz;
0332     mem_dma += rx_fis_sz;
0333
0334     /*
0335      * Third item: data area for storing a single command
0336      * and its scatter-gather table
0337      */
0338     pp->cmd_tbl = mem;
0339     pp->cmd_tbl_dma = mem_dma;
0340
0341     /*
0342      * Save off initial list of interrupts to be enabled.
0343      * This could be changed later
0344      */
0345     pp->intr_mask = DEF_PORT_IRQ;
0346
0347     ap->private_data = pp;
0348
0349     /* engage engines, captain */
0350     return ahci_port_resume(ap);
0351 }
0352
0353 static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
0354 {
0355     unsigned int board_id = ent->driver_data;
0356     struct ata_port_info pi = acard_ahci_port_info[board_id];
0357     const struct ata_port_info *ppi[] = { &pi, NULL };
0358     struct device *dev = &pdev->dev;
0359     struct ahci_host_priv *hpriv;
0360     struct ata_host *host;
0361     int n_ports, i, rc;
0362
0363     WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
0364
0365     ata_print_version_once(&pdev->dev, DRV_VERSION);
0366
0367     /* acquire resources */
0368     rc = pcim_enable_device(pdev);
0369     if (rc)
0370         return rc;
0371
0372     /* AHCI controllers often implement SFF compatible interface.
0373      * Grab all PCI BARs just in case.
0374      */
0375     rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
0376     if (rc == -EBUSY)
0377         pcim_pin_device(pdev);
0378     if (rc)
0379         return rc;
0380
0381     hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
0382     if (!hpriv)
0383         return -ENOMEM;
0384
0385     hpriv->irq = pdev->irq;
0386     hpriv->flags |= (unsigned long)pi.private_data;
0387
0388     if (!(hpriv->flags & AHCI_HFLAG_NO_MSI))
0389         pci_enable_msi(pdev);
0390
0391     hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
0392
0393     /* save initial config */
0394     ahci_save_initial_config(&pdev->dev, hpriv);
0395
0396     /* prepare host */
0397     if (hpriv->cap & HOST_CAP_NCQ)
0398         pi.flags |= ATA_FLAG_NCQ;
0399
0400     if (hpriv->cap & HOST_CAP_PMP)
0401         pi.flags |= ATA_FLAG_PMP;
0402
0403     ahci_set_em_messages(hpriv, &pi);
0404
0405     /* CAP.NP sometimes indicate the index of the last enabled
0406      * port, at other times, that of the last possible port, so
0407      * determining the maximum port number requires looking at
0408      * both CAP.NP and port_map.
0409      */
0410     n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
0411
0412     host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
0413     if (!host)
0414         return -ENOMEM;
0415     host->private_data = hpriv;
0416
0417     if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
0418         host->flags |= ATA_HOST_PARALLEL_SCAN;
0419     else
0420         printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
0421
0422     for (i = 0; i < host->n_ports; i++) {
0423         struct ata_port *ap = host->ports[i];
0424
0425         ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
0426         ata_port_pbar_desc(ap, AHCI_PCI_BAR,
0427                    0x100 + ap->port_no * 0x80, "port");
0428
0429         /* set initial link pm policy */
0430         /*
0431         ap->pm_policy = NOT_AVAILABLE;
0432         */
0433         /* disabled/not-implemented port */
0434         if (!(hpriv->port_map & (1 << i)))
0435             ap->ops = &ata_dummy_port_ops;
0436     }
0437
0438     /* initialize adapter */
0439     rc = dma_set_mask_and_coherent(&pdev->dev,
0440             DMA_BIT_MASK((hpriv->cap & HOST_CAP_64) ? 64 : 32));
0441     if (rc) {
0442         dev_err(&pdev->dev, "DMA enable failed\n");
0443         return rc;
0444     }
0445
0446     rc = ahci_reset_controller(host);
0447     if (rc)
0448         return rc;
0449
0450     ahci_init_controller(host);
0451     acard_ahci_pci_print_info(host);
0452
0453     pci_set_master(pdev);
0454     return ahci_host_activate(host, &acard_ahci_sht);
0455 }
0456
0457 module_pci_driver(acard_ahci_pci_driver);
0458
0459 MODULE_AUTHOR("Jeff Garzik");
0460 MODULE_DESCRIPTION("ACard AHCI SATA low-level driver");
0461 MODULE_LICENSE("GPL");
0462 MODULE_DEVICE_TABLE(pci, acard_ahci_pci_tbl);
0463 MODULE_VERSION(DRV_VERSION);