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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  pci_root.c - ACPI PCI Root Bridge Driver ($Revision: 40 $)
0004  *
0005  *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
0006  *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
0007  */
0008 
0009 #define pr_fmt(fmt) "ACPI: " fmt
0010 
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/init.h>
0014 #include <linux/types.h>
0015 #include <linux/mutex.h>
0016 #include <linux/pm.h>
0017 #include <linux/pm_runtime.h>
0018 #include <linux/pci.h>
0019 #include <linux/pci-acpi.h>
0020 #include <linux/dmar.h>
0021 #include <linux/acpi.h>
0022 #include <linux/slab.h>
0023 #include <linux/dmi.h>
0024 #include <linux/platform_data/x86/apple.h>
0025 #include "internal.h"
0026 
0027 #define ACPI_PCI_ROOT_CLASS     "pci_bridge"
0028 #define ACPI_PCI_ROOT_DEVICE_NAME   "PCI Root Bridge"
0029 static int acpi_pci_root_add(struct acpi_device *device,
0030                  const struct acpi_device_id *not_used);
0031 static void acpi_pci_root_remove(struct acpi_device *device);
0032 
0033 static int acpi_pci_root_scan_dependent(struct acpi_device *adev)
0034 {
0035     acpiphp_check_host_bridge(adev);
0036     return 0;
0037 }
0038 
0039 #define ACPI_PCIE_REQ_SUPPORT (OSC_PCI_EXT_CONFIG_SUPPORT \
0040                 | OSC_PCI_ASPM_SUPPORT \
0041                 | OSC_PCI_CLOCK_PM_SUPPORT \
0042                 | OSC_PCI_MSI_SUPPORT)
0043 
0044 static const struct acpi_device_id root_device_ids[] = {
0045     {"PNP0A03", 0},
0046     {"", 0},
0047 };
0048 
0049 static struct acpi_scan_handler pci_root_handler = {
0050     .ids = root_device_ids,
0051     .attach = acpi_pci_root_add,
0052     .detach = acpi_pci_root_remove,
0053     .hotplug = {
0054         .enabled = true,
0055         .scan_dependent = acpi_pci_root_scan_dependent,
0056     },
0057 };
0058 
0059 /**
0060  * acpi_is_root_bridge - determine whether an ACPI CA node is a PCI root bridge
0061  * @handle:  the ACPI CA node in question.
0062  *
0063  * Note: we could make this API take a struct acpi_device * instead, but
0064  * for now, it's more convenient to operate on an acpi_handle.
0065  */
0066 int acpi_is_root_bridge(acpi_handle handle)
0067 {
0068     struct acpi_device *device = acpi_fetch_acpi_dev(handle);
0069     int ret;
0070 
0071     if (!device)
0072         return 0;
0073 
0074     ret = acpi_match_device_ids(device, root_device_ids);
0075     if (ret)
0076         return 0;
0077     else
0078         return 1;
0079 }
0080 EXPORT_SYMBOL_GPL(acpi_is_root_bridge);
0081 
0082 static acpi_status
0083 get_root_bridge_busnr_callback(struct acpi_resource *resource, void *data)
0084 {
0085     struct resource *res = data;
0086     struct acpi_resource_address64 address;
0087     acpi_status status;
0088 
0089     status = acpi_resource_to_address64(resource, &address);
0090     if (ACPI_FAILURE(status))
0091         return AE_OK;
0092 
0093     if ((address.address.address_length > 0) &&
0094         (address.resource_type == ACPI_BUS_NUMBER_RANGE)) {
0095         res->start = address.address.minimum;
0096         res->end = address.address.minimum + address.address.address_length - 1;
0097     }
0098 
0099     return AE_OK;
0100 }
0101 
0102 static acpi_status try_get_root_bridge_busnr(acpi_handle handle,
0103                          struct resource *res)
0104 {
0105     acpi_status status;
0106 
0107     res->start = -1;
0108     status =
0109         acpi_walk_resources(handle, METHOD_NAME__CRS,
0110                 get_root_bridge_busnr_callback, res);
0111     if (ACPI_FAILURE(status))
0112         return status;
0113     if (res->start == -1)
0114         return AE_ERROR;
0115     return AE_OK;
0116 }
0117 
0118 struct pci_osc_bit_struct {
0119     u32 bit;
0120     char *desc;
0121 };
0122 
0123 static struct pci_osc_bit_struct pci_osc_support_bit[] = {
0124     { OSC_PCI_EXT_CONFIG_SUPPORT, "ExtendedConfig" },
0125     { OSC_PCI_ASPM_SUPPORT, "ASPM" },
0126     { OSC_PCI_CLOCK_PM_SUPPORT, "ClockPM" },
0127     { OSC_PCI_SEGMENT_GROUPS_SUPPORT, "Segments" },
0128     { OSC_PCI_MSI_SUPPORT, "MSI" },
0129     { OSC_PCI_EDR_SUPPORT, "EDR" },
0130     { OSC_PCI_HPX_TYPE_3_SUPPORT, "HPX-Type3" },
0131 };
0132 
0133 static struct pci_osc_bit_struct pci_osc_control_bit[] = {
0134     { OSC_PCI_EXPRESS_NATIVE_HP_CONTROL, "PCIeHotplug" },
0135     { OSC_PCI_SHPC_NATIVE_HP_CONTROL, "SHPCHotplug" },
0136     { OSC_PCI_EXPRESS_PME_CONTROL, "PME" },
0137     { OSC_PCI_EXPRESS_AER_CONTROL, "AER" },
0138     { OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" },
0139     { OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" },
0140     { OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" },
0141 };
0142 
0143 static struct pci_osc_bit_struct cxl_osc_support_bit[] = {
0144     { OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT, "CXL11PortRegAccess" },
0145     { OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT, "CXL20PortDevRegAccess" },
0146     { OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT, "CXLProtocolErrorReporting" },
0147     { OSC_CXL_NATIVE_HP_SUPPORT, "CXLNativeHotPlug" },
0148 };
0149 
0150 static struct pci_osc_bit_struct cxl_osc_control_bit[] = {
0151     { OSC_CXL_ERROR_REPORTING_CONTROL, "CXLMemErrorReporting" },
0152 };
0153 
0154 static void decode_osc_bits(struct acpi_pci_root *root, char *msg, u32 word,
0155                 struct pci_osc_bit_struct *table, int size)
0156 {
0157     char buf[80];
0158     int i, len = 0;
0159     struct pci_osc_bit_struct *entry;
0160 
0161     buf[0] = '\0';
0162     for (i = 0, entry = table; i < size; i++, entry++)
0163         if (word & entry->bit)
0164             len += scnprintf(buf + len, sizeof(buf) - len, "%s%s",
0165                     len ? " " : "", entry->desc);
0166 
0167     dev_info(&root->device->dev, "_OSC: %s [%s]\n", msg, buf);
0168 }
0169 
0170 static void decode_osc_support(struct acpi_pci_root *root, char *msg, u32 word)
0171 {
0172     decode_osc_bits(root, msg, word, pci_osc_support_bit,
0173             ARRAY_SIZE(pci_osc_support_bit));
0174 }
0175 
0176 static void decode_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
0177 {
0178     decode_osc_bits(root, msg, word, pci_osc_control_bit,
0179             ARRAY_SIZE(pci_osc_control_bit));
0180 }
0181 
0182 static void decode_cxl_osc_support(struct acpi_pci_root *root, char *msg, u32 word)
0183 {
0184     decode_osc_bits(root, msg, word, cxl_osc_support_bit,
0185             ARRAY_SIZE(cxl_osc_support_bit));
0186 }
0187 
0188 static void decode_cxl_osc_control(struct acpi_pci_root *root, char *msg, u32 word)
0189 {
0190     decode_osc_bits(root, msg, word, cxl_osc_control_bit,
0191             ARRAY_SIZE(cxl_osc_control_bit));
0192 }
0193 
0194 static inline bool is_pcie(struct acpi_pci_root *root)
0195 {
0196     return root->bridge_type == ACPI_BRIDGE_TYPE_PCIE;
0197 }
0198 
0199 static inline bool is_cxl(struct acpi_pci_root *root)
0200 {
0201     return root->bridge_type == ACPI_BRIDGE_TYPE_CXL;
0202 }
0203 
0204 static u8 pci_osc_uuid_str[] = "33DB4D5B-1FF7-401C-9657-7441C03DD766";
0205 static u8 cxl_osc_uuid_str[] = "68F2D50B-C469-4d8A-BD3D-941A103FD3FC";
0206 
0207 static char *to_uuid(struct acpi_pci_root *root)
0208 {
0209     if (is_cxl(root))
0210         return cxl_osc_uuid_str;
0211     return pci_osc_uuid_str;
0212 }
0213 
0214 static int cap_length(struct acpi_pci_root *root)
0215 {
0216     if (is_cxl(root))
0217         return sizeof(u32) * OSC_CXL_CAPABILITY_DWORDS;
0218     return sizeof(u32) * OSC_PCI_CAPABILITY_DWORDS;
0219 }
0220 
0221 static acpi_status acpi_pci_run_osc(struct acpi_pci_root *root,
0222                     const u32 *capbuf, u32 *pci_control,
0223                     u32 *cxl_control)
0224 {
0225     struct acpi_osc_context context = {
0226         .uuid_str = to_uuid(root),
0227         .rev = 1,
0228         .cap.length = cap_length(root),
0229         .cap.pointer = (void *)capbuf,
0230     };
0231     acpi_status status;
0232 
0233     status = acpi_run_osc(root->device->handle, &context);
0234     if (ACPI_SUCCESS(status)) {
0235         *pci_control = acpi_osc_ctx_get_pci_control(&context);
0236         if (is_cxl(root))
0237             *cxl_control = acpi_osc_ctx_get_cxl_control(&context);
0238         kfree(context.ret.pointer);
0239     }
0240     return status;
0241 }
0242 
0243 static acpi_status acpi_pci_query_osc(struct acpi_pci_root *root, u32 support,
0244                       u32 *control, u32 cxl_support,
0245                       u32 *cxl_control)
0246 {
0247     acpi_status status;
0248     u32 pci_result, cxl_result, capbuf[OSC_CXL_CAPABILITY_DWORDS];
0249 
0250     support |= root->osc_support_set;
0251 
0252     capbuf[OSC_QUERY_DWORD] = OSC_QUERY_ENABLE;
0253     capbuf[OSC_SUPPORT_DWORD] = support;
0254     capbuf[OSC_CONTROL_DWORD] = *control | root->osc_control_set;
0255 
0256     if (is_cxl(root)) {
0257         cxl_support |= root->osc_ext_support_set;
0258         capbuf[OSC_EXT_SUPPORT_DWORD] = cxl_support;
0259         capbuf[OSC_EXT_CONTROL_DWORD] = *cxl_control | root->osc_ext_control_set;
0260     }
0261 
0262 retry:
0263     status = acpi_pci_run_osc(root, capbuf, &pci_result, &cxl_result);
0264     if (ACPI_SUCCESS(status)) {
0265         root->osc_support_set = support;
0266         *control = pci_result;
0267         if (is_cxl(root)) {
0268             root->osc_ext_support_set = cxl_support;
0269             *cxl_control = cxl_result;
0270         }
0271     } else if (is_cxl(root)) {
0272         /*
0273          * CXL _OSC is optional on CXL 1.1 hosts. Fall back to PCIe _OSC
0274          * upon any failure using CXL _OSC.
0275          */
0276         root->bridge_type = ACPI_BRIDGE_TYPE_PCIE;
0277         goto retry;
0278     }
0279     return status;
0280 }
0281 
0282 struct acpi_pci_root *acpi_pci_find_root(acpi_handle handle)
0283 {
0284     struct acpi_device *device = acpi_fetch_acpi_dev(handle);
0285     struct acpi_pci_root *root;
0286 
0287     if (!device || acpi_match_device_ids(device, root_device_ids))
0288         return NULL;
0289 
0290     root = acpi_driver_data(device);
0291 
0292     return root;
0293 }
0294 EXPORT_SYMBOL_GPL(acpi_pci_find_root);
0295 
0296 struct acpi_handle_node {
0297     struct list_head node;
0298     acpi_handle handle;
0299 };
0300 
0301 /**
0302  * acpi_get_pci_dev - convert ACPI CA handle to struct pci_dev
0303  * @handle: the handle in question
0304  *
0305  * Given an ACPI CA handle, the desired PCI device is located in the
0306  * list of PCI devices.
0307  *
0308  * If the device is found, its reference count is increased and this
0309  * function returns a pointer to its data structure.  The caller must
0310  * decrement the reference count by calling pci_dev_put().
0311  * If no device is found, %NULL is returned.
0312  */
0313 struct pci_dev *acpi_get_pci_dev(acpi_handle handle)
0314 {
0315     int dev, fn;
0316     unsigned long long adr;
0317     acpi_status status;
0318     acpi_handle phandle;
0319     struct pci_bus *pbus;
0320     struct pci_dev *pdev = NULL;
0321     struct acpi_handle_node *node, *tmp;
0322     struct acpi_pci_root *root;
0323     LIST_HEAD(device_list);
0324 
0325     /*
0326      * Walk up the ACPI CA namespace until we reach a PCI root bridge.
0327      */
0328     phandle = handle;
0329     while (!acpi_is_root_bridge(phandle)) {
0330         node = kzalloc(sizeof(struct acpi_handle_node), GFP_KERNEL);
0331         if (!node)
0332             goto out;
0333 
0334         INIT_LIST_HEAD(&node->node);
0335         node->handle = phandle;
0336         list_add(&node->node, &device_list);
0337 
0338         status = acpi_get_parent(phandle, &phandle);
0339         if (ACPI_FAILURE(status))
0340             goto out;
0341     }
0342 
0343     root = acpi_pci_find_root(phandle);
0344     if (!root)
0345         goto out;
0346 
0347     pbus = root->bus;
0348 
0349     /*
0350      * Now, walk back down the PCI device tree until we return to our
0351      * original handle. Assumes that everything between the PCI root
0352      * bridge and the device we're looking for must be a P2P bridge.
0353      */
0354     list_for_each_entry(node, &device_list, node) {
0355         acpi_handle hnd = node->handle;
0356         status = acpi_evaluate_integer(hnd, "_ADR", NULL, &adr);
0357         if (ACPI_FAILURE(status))
0358             goto out;
0359         dev = (adr >> 16) & 0xffff;
0360         fn  = adr & 0xffff;
0361 
0362         pdev = pci_get_slot(pbus, PCI_DEVFN(dev, fn));
0363         if (!pdev || hnd == handle)
0364             break;
0365 
0366         pbus = pdev->subordinate;
0367         pci_dev_put(pdev);
0368 
0369         /*
0370          * This function may be called for a non-PCI device that has a
0371          * PCI parent (eg. a disk under a PCI SATA controller).  In that
0372          * case pdev->subordinate will be NULL for the parent.
0373          */
0374         if (!pbus) {
0375             dev_dbg(&pdev->dev, "Not a PCI-to-PCI bridge\n");
0376             pdev = NULL;
0377             break;
0378         }
0379     }
0380 out:
0381     list_for_each_entry_safe(node, tmp, &device_list, node)
0382         kfree(node);
0383 
0384     return pdev;
0385 }
0386 EXPORT_SYMBOL_GPL(acpi_get_pci_dev);
0387 
0388 /**
0389  * acpi_pci_osc_control_set - Request control of PCI root _OSC features.
0390  * @handle: ACPI handle of a PCI root bridge (or PCIe Root Complex).
0391  * @mask: Mask of _OSC bits to request control of, place to store control mask.
0392  * @support: _OSC supported capability.
0393  * @cxl_mask: Mask of CXL _OSC control bits, place to store control mask.
0394  * @cxl_support: CXL _OSC supported capability.
0395  *
0396  * Run _OSC query for @mask and if that is successful, compare the returned
0397  * mask of control bits with @req.  If all of the @req bits are set in the
0398  * returned mask, run _OSC request for it.
0399  *
0400  * The variable at the @mask address may be modified regardless of whether or
0401  * not the function returns success.  On success it will contain the mask of
0402  * _OSC bits the BIOS has granted control of, but its contents are meaningless
0403  * on failure.
0404  **/
0405 static acpi_status acpi_pci_osc_control_set(acpi_handle handle, u32 *mask,
0406                         u32 support, u32 *cxl_mask,
0407                         u32 cxl_support)
0408 {
0409     u32 req = OSC_PCI_EXPRESS_CAPABILITY_CONTROL;
0410     struct acpi_pci_root *root;
0411     acpi_status status;
0412     u32 ctrl, cxl_ctrl = 0, capbuf[OSC_CXL_CAPABILITY_DWORDS];
0413 
0414     if (!mask)
0415         return AE_BAD_PARAMETER;
0416 
0417     root = acpi_pci_find_root(handle);
0418     if (!root)
0419         return AE_NOT_EXIST;
0420 
0421     ctrl   = *mask;
0422     *mask |= root->osc_control_set;
0423 
0424     if (is_cxl(root)) {
0425         cxl_ctrl = *cxl_mask;
0426         *cxl_mask |= root->osc_ext_control_set;
0427     }
0428 
0429     /* Need to check the available controls bits before requesting them. */
0430     do {
0431         u32 pci_missing = 0, cxl_missing = 0;
0432 
0433         status = acpi_pci_query_osc(root, support, mask, cxl_support,
0434                         cxl_mask);
0435         if (ACPI_FAILURE(status))
0436             return status;
0437         if (is_cxl(root)) {
0438             if (ctrl == *mask && cxl_ctrl == *cxl_mask)
0439                 break;
0440             pci_missing = ctrl & ~(*mask);
0441             cxl_missing = cxl_ctrl & ~(*cxl_mask);
0442         } else {
0443             if (ctrl == *mask)
0444                 break;
0445             pci_missing = ctrl & ~(*mask);
0446         }
0447         if (pci_missing)
0448             decode_osc_control(root, "platform does not support",
0449                        pci_missing);
0450         if (cxl_missing)
0451             decode_cxl_osc_control(root, "CXL platform does not support",
0452                        cxl_missing);
0453         ctrl = *mask;
0454         cxl_ctrl = *cxl_mask;
0455     } while (*mask || *cxl_mask);
0456 
0457     /* No need to request _OSC if the control was already granted. */
0458     if ((root->osc_control_set & ctrl) == ctrl &&
0459         (root->osc_ext_control_set & cxl_ctrl) == cxl_ctrl)
0460         return AE_OK;
0461 
0462     if ((ctrl & req) != req) {
0463         decode_osc_control(root, "not requesting control; platform does not support",
0464                    req & ~(ctrl));
0465         return AE_SUPPORT;
0466     }
0467 
0468     capbuf[OSC_QUERY_DWORD] = 0;
0469     capbuf[OSC_SUPPORT_DWORD] = root->osc_support_set;
0470     capbuf[OSC_CONTROL_DWORD] = ctrl;
0471     if (is_cxl(root)) {
0472         capbuf[OSC_EXT_SUPPORT_DWORD] = root->osc_ext_support_set;
0473         capbuf[OSC_EXT_CONTROL_DWORD] = cxl_ctrl;
0474     }
0475 
0476     status = acpi_pci_run_osc(root, capbuf, mask, cxl_mask);
0477     if (ACPI_FAILURE(status))
0478         return status;
0479 
0480     root->osc_control_set = *mask;
0481     root->osc_ext_control_set = *cxl_mask;
0482     return AE_OK;
0483 }
0484 
0485 static u32 calculate_support(void)
0486 {
0487     u32 support;
0488 
0489     /*
0490      * All supported architectures that use ACPI have support for
0491      * PCI domains, so we indicate this in _OSC support capabilities.
0492      */
0493     support = OSC_PCI_SEGMENT_GROUPS_SUPPORT;
0494     support |= OSC_PCI_HPX_TYPE_3_SUPPORT;
0495     if (pci_ext_cfg_avail())
0496         support |= OSC_PCI_EXT_CONFIG_SUPPORT;
0497     if (pcie_aspm_support_enabled())
0498         support |= OSC_PCI_ASPM_SUPPORT | OSC_PCI_CLOCK_PM_SUPPORT;
0499     if (pci_msi_enabled())
0500         support |= OSC_PCI_MSI_SUPPORT;
0501     if (IS_ENABLED(CONFIG_PCIE_EDR))
0502         support |= OSC_PCI_EDR_SUPPORT;
0503 
0504     return support;
0505 }
0506 
0507 /*
0508  * Background on hotplug support, and making it depend on only
0509  * CONFIG_HOTPLUG_PCI_PCIE vs. also considering CONFIG_MEMORY_HOTPLUG:
0510  *
0511  * CONFIG_ACPI_HOTPLUG_MEMORY does depend on CONFIG_MEMORY_HOTPLUG, but
0512  * there is no existing _OSC for memory hotplug support. The reason is that
0513  * ACPI memory hotplug requires the OS to acknowledge / coordinate with
0514  * memory plug events via a scan handler. On the CXL side the equivalent
0515  * would be if Linux supported the Mechanical Retention Lock [1], or
0516  * otherwise had some coordination for the driver of a PCI device
0517  * undergoing hotplug to be consulted on whether the hotplug should
0518  * proceed or not.
0519  *
0520  * The concern is that if Linux says no to supporting CXL hotplug then
0521  * the BIOS may say no to giving the OS hotplug control of any other PCIe
0522  * device. So the question here is not whether hotplug is enabled, it's
0523  * whether it is handled natively by the at all OS, and if
0524  * CONFIG_HOTPLUG_PCI_PCIE is enabled then the answer is "yes".
0525  *
0526  * Otherwise, the plan for CXL coordinated remove, since the kernel does
0527  * not support blocking hotplug, is to require the memory device to be
0528  * disabled before hotplug is attempted. When CONFIG_MEMORY_HOTPLUG is
0529  * disabled that step will fail and the remove attempt cancelled by the
0530  * user. If that is not honored and the card is removed anyway then it
0531  * does not matter if CONFIG_MEMORY_HOTPLUG is enabled or not, it will
0532  * cause a crash and other badness.
0533  *
0534  * Therefore, just say yes to CXL hotplug and require removal to
0535  * be coordinated by userspace unless and until the kernel grows better
0536  * mechanisms for doing "managed" removal of devices in consultation with
0537  * the driver.
0538  *
0539  * [1]: https://lore.kernel.org/all/20201122014203.4706-1-ashok.raj@intel.com/
0540  */
0541 static u32 calculate_cxl_support(void)
0542 {
0543     u32 support;
0544 
0545     support = OSC_CXL_2_0_PORT_DEV_REG_ACCESS_SUPPORT;
0546     if (pci_aer_available())
0547         support |= OSC_CXL_PROTOCOL_ERR_REPORTING_SUPPORT;
0548     if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
0549         support |= OSC_CXL_NATIVE_HP_SUPPORT;
0550 
0551     return support;
0552 }
0553 
0554 static u32 calculate_control(void)
0555 {
0556     u32 control;
0557 
0558     control = OSC_PCI_EXPRESS_CAPABILITY_CONTROL
0559         | OSC_PCI_EXPRESS_PME_CONTROL;
0560 
0561     if (IS_ENABLED(CONFIG_PCIEASPM))
0562         control |= OSC_PCI_EXPRESS_LTR_CONTROL;
0563 
0564     if (IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
0565         control |= OSC_PCI_EXPRESS_NATIVE_HP_CONTROL;
0566 
0567     if (IS_ENABLED(CONFIG_HOTPLUG_PCI_SHPC))
0568         control |= OSC_PCI_SHPC_NATIVE_HP_CONTROL;
0569 
0570     if (pci_aer_available())
0571         control |= OSC_PCI_EXPRESS_AER_CONTROL;
0572 
0573     /*
0574      * Per the Downstream Port Containment Related Enhancements ECN to
0575      * the PCI Firmware Spec, r3.2, sec 4.5.1, table 4-5,
0576      * OSC_PCI_EXPRESS_DPC_CONTROL indicates the OS supports both DPC
0577      * and EDR.
0578      */
0579     if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR))
0580         control |= OSC_PCI_EXPRESS_DPC_CONTROL;
0581 
0582     return control;
0583 }
0584 
0585 static u32 calculate_cxl_control(void)
0586 {
0587     u32 control = 0;
0588 
0589     if (IS_ENABLED(CONFIG_MEMORY_FAILURE))
0590         control |= OSC_CXL_ERROR_REPORTING_CONTROL;
0591 
0592     return control;
0593 }
0594 
0595 static bool os_control_query_checks(struct acpi_pci_root *root, u32 support)
0596 {
0597     struct acpi_device *device = root->device;
0598 
0599     if (pcie_ports_disabled) {
0600         dev_info(&device->dev, "PCIe port services disabled; not requesting _OSC control\n");
0601         return false;
0602     }
0603 
0604     if ((support & ACPI_PCIE_REQ_SUPPORT) != ACPI_PCIE_REQ_SUPPORT) {
0605         decode_osc_support(root, "not requesting OS control; OS requires",
0606                    ACPI_PCIE_REQ_SUPPORT);
0607         return false;
0608     }
0609 
0610     return true;
0611 }
0612 
0613 static void negotiate_os_control(struct acpi_pci_root *root, int *no_aspm)
0614 {
0615     u32 support, control = 0, requested = 0;
0616     u32 cxl_support = 0, cxl_control = 0, cxl_requested = 0;
0617     acpi_status status;
0618     struct acpi_device *device = root->device;
0619     acpi_handle handle = device->handle;
0620 
0621     /*
0622      * Apple always return failure on _OSC calls when _OSI("Darwin") has
0623      * been called successfully. We know the feature set supported by the
0624      * platform, so avoid calling _OSC at all
0625      */
0626     if (x86_apple_machine) {
0627         root->osc_control_set = ~OSC_PCI_EXPRESS_PME_CONTROL;
0628         decode_osc_control(root, "OS assumes control of",
0629                    root->osc_control_set);
0630         return;
0631     }
0632 
0633     support = calculate_support();
0634 
0635     decode_osc_support(root, "OS supports", support);
0636 
0637     if (os_control_query_checks(root, support))
0638         requested = control = calculate_control();
0639 
0640     if (is_cxl(root)) {
0641         cxl_support = calculate_cxl_support();
0642         decode_cxl_osc_support(root, "OS supports", cxl_support);
0643         cxl_requested = cxl_control = calculate_cxl_control();
0644     }
0645 
0646     status = acpi_pci_osc_control_set(handle, &control, support,
0647                       &cxl_control, cxl_support);
0648     if (ACPI_SUCCESS(status)) {
0649         if (control)
0650             decode_osc_control(root, "OS now controls", control);
0651         if (cxl_control)
0652             decode_cxl_osc_control(root, "OS now controls",
0653                        cxl_control);
0654 
0655         if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
0656             /*
0657              * We have ASPM control, but the FADT indicates that
0658              * it's unsupported. Leave existing configuration
0659              * intact and prevent the OS from touching it.
0660              */
0661             dev_info(&device->dev, "FADT indicates ASPM is unsupported, using BIOS configuration\n");
0662             *no_aspm = 1;
0663         }
0664     } else {
0665         /*
0666          * We want to disable ASPM here, but aspm_disabled
0667          * needs to remain in its state from boot so that we
0668          * properly handle PCIe 1.1 devices.  So we set this
0669          * flag here, to defer the action until after the ACPI
0670          * root scan.
0671          */
0672         *no_aspm = 1;
0673 
0674         /* _OSC is optional for PCI host bridges */
0675         if (status == AE_NOT_FOUND && !is_pcie(root))
0676             return;
0677 
0678         if (control) {
0679             decode_osc_control(root, "OS requested", requested);
0680             decode_osc_control(root, "platform willing to grant", control);
0681         }
0682         if (cxl_control) {
0683             decode_cxl_osc_control(root, "OS requested", cxl_requested);
0684             decode_cxl_osc_control(root, "platform willing to grant",
0685                        cxl_control);
0686         }
0687 
0688         dev_info(&device->dev, "_OSC: platform retains control of PCIe features (%s)\n",
0689              acpi_format_exception(status));
0690     }
0691 }
0692 
0693 static int acpi_pci_root_add(struct acpi_device *device,
0694                  const struct acpi_device_id *not_used)
0695 {
0696     unsigned long long segment, bus;
0697     acpi_status status;
0698     int result;
0699     struct acpi_pci_root *root;
0700     acpi_handle handle = device->handle;
0701     int no_aspm = 0;
0702     bool hotadd = system_state == SYSTEM_RUNNING;
0703     const char *acpi_hid;
0704 
0705     root = kzalloc(sizeof(struct acpi_pci_root), GFP_KERNEL);
0706     if (!root)
0707         return -ENOMEM;
0708 
0709     segment = 0;
0710     status = acpi_evaluate_integer(handle, METHOD_NAME__SEG, NULL,
0711                        &segment);
0712     if (ACPI_FAILURE(status) && status != AE_NOT_FOUND) {
0713         dev_err(&device->dev,  "can't evaluate _SEG\n");
0714         result = -ENODEV;
0715         goto end;
0716     }
0717 
0718     /* Check _CRS first, then _BBN.  If no _BBN, default to zero. */
0719     root->secondary.flags = IORESOURCE_BUS;
0720     status = try_get_root_bridge_busnr(handle, &root->secondary);
0721     if (ACPI_FAILURE(status)) {
0722         /*
0723          * We need both the start and end of the downstream bus range
0724          * to interpret _CBA (MMCONFIG base address), so it really is
0725          * supposed to be in _CRS.  If we don't find it there, all we
0726          * can do is assume [_BBN-0xFF] or [0-0xFF].
0727          */
0728         root->secondary.end = 0xFF;
0729         dev_warn(&device->dev,
0730              FW_BUG "no secondary bus range in _CRS\n");
0731         status = acpi_evaluate_integer(handle, METHOD_NAME__BBN,
0732                            NULL, &bus);
0733         if (ACPI_SUCCESS(status))
0734             root->secondary.start = bus;
0735         else if (status == AE_NOT_FOUND)
0736             root->secondary.start = 0;
0737         else {
0738             dev_err(&device->dev, "can't evaluate _BBN\n");
0739             result = -ENODEV;
0740             goto end;
0741         }
0742     }
0743 
0744     root->device = device;
0745     root->segment = segment & 0xFFFF;
0746     strcpy(acpi_device_name(device), ACPI_PCI_ROOT_DEVICE_NAME);
0747     strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS);
0748     device->driver_data = root;
0749 
0750     if (hotadd && dmar_device_add(handle)) {
0751         result = -ENXIO;
0752         goto end;
0753     }
0754 
0755     pr_info("%s [%s] (domain %04x %pR)\n",
0756            acpi_device_name(device), acpi_device_bid(device),
0757            root->segment, &root->secondary);
0758 
0759     root->mcfg_addr = acpi_pci_root_get_mcfg_addr(handle);
0760 
0761     acpi_hid = acpi_device_hid(root->device);
0762     if (strcmp(acpi_hid, "PNP0A08") == 0)
0763         root->bridge_type = ACPI_BRIDGE_TYPE_PCIE;
0764     else if (strcmp(acpi_hid, "ACPI0016") == 0)
0765         root->bridge_type = ACPI_BRIDGE_TYPE_CXL;
0766     else
0767         dev_dbg(&device->dev, "Assuming non-PCIe host bridge\n");
0768 
0769     negotiate_os_control(root, &no_aspm);
0770 
0771     /*
0772      * TBD: Need PCI interface for enumeration/configuration of roots.
0773      */
0774 
0775     /*
0776      * Scan the Root Bridge
0777      * --------------------
0778      * Must do this prior to any attempt to bind the root device, as the
0779      * PCI namespace does not get created until this call is made (and
0780      * thus the root bridge's pci_dev does not exist).
0781      */
0782     root->bus = pci_acpi_scan_root(root);
0783     if (!root->bus) {
0784         dev_err(&device->dev,
0785             "Bus %04x:%02x not present in PCI namespace\n",
0786             root->segment, (unsigned int)root->secondary.start);
0787         device->driver_data = NULL;
0788         result = -ENODEV;
0789         goto remove_dmar;
0790     }
0791 
0792     if (no_aspm)
0793         pcie_no_aspm();
0794 
0795     pci_acpi_add_bus_pm_notifier(device);
0796     device_set_wakeup_capable(root->bus->bridge, device->wakeup.flags.valid);
0797 
0798     if (hotadd) {
0799         pcibios_resource_survey_bus(root->bus);
0800         pci_assign_unassigned_root_bus_resources(root->bus);
0801         /*
0802          * This is only called for the hotadd case. For the boot-time
0803          * case, we need to wait until after PCI initialization in
0804          * order to deal with IOAPICs mapped in on a PCI BAR.
0805          *
0806          * This is currently x86-specific, because acpi_ioapic_add()
0807          * is an empty function without CONFIG_ACPI_HOTPLUG_IOAPIC.
0808          * And CONFIG_ACPI_HOTPLUG_IOAPIC depends on CONFIG_X86_IO_APIC
0809          * (see drivers/acpi/Kconfig).
0810          */
0811         acpi_ioapic_add(root->device->handle);
0812     }
0813 
0814     pci_lock_rescan_remove();
0815     pci_bus_add_devices(root->bus);
0816     pci_unlock_rescan_remove();
0817     return 1;
0818 
0819 remove_dmar:
0820     if (hotadd)
0821         dmar_device_remove(handle);
0822 end:
0823     kfree(root);
0824     return result;
0825 }
0826 
0827 static void acpi_pci_root_remove(struct acpi_device *device)
0828 {
0829     struct acpi_pci_root *root = acpi_driver_data(device);
0830 
0831     pci_lock_rescan_remove();
0832 
0833     pci_stop_root_bus(root->bus);
0834 
0835     pci_ioapic_remove(root);
0836     device_set_wakeup_capable(root->bus->bridge, false);
0837     pci_acpi_remove_bus_pm_notifier(device);
0838 
0839     pci_remove_root_bus(root->bus);
0840     WARN_ON(acpi_ioapic_remove(root));
0841 
0842     dmar_device_remove(device->handle);
0843 
0844     pci_unlock_rescan_remove();
0845 
0846     kfree(root);
0847 }
0848 
0849 /*
0850  * Following code to support acpi_pci_root_create() is copied from
0851  * arch/x86/pci/acpi.c and modified so it could be reused by x86, IA64
0852  * and ARM64.
0853  */
0854 static void acpi_pci_root_validate_resources(struct device *dev,
0855                          struct list_head *resources,
0856                          unsigned long type)
0857 {
0858     LIST_HEAD(list);
0859     struct resource *res1, *res2, *root = NULL;
0860     struct resource_entry *tmp, *entry, *entry2;
0861 
0862     BUG_ON((type & (IORESOURCE_MEM | IORESOURCE_IO)) == 0);
0863     root = (type & IORESOURCE_MEM) ? &iomem_resource : &ioport_resource;
0864 
0865     list_splice_init(resources, &list);
0866     resource_list_for_each_entry_safe(entry, tmp, &list) {
0867         bool free = false;
0868         resource_size_t end;
0869 
0870         res1 = entry->res;
0871         if (!(res1->flags & type))
0872             goto next;
0873 
0874         /* Exclude non-addressable range or non-addressable portion */
0875         end = min(res1->end, root->end);
0876         if (end <= res1->start) {
0877             dev_info(dev, "host bridge window %pR (ignored, not CPU addressable)\n",
0878                  res1);
0879             free = true;
0880             goto next;
0881         } else if (res1->end != end) {
0882             dev_info(dev, "host bridge window %pR ([%#llx-%#llx] ignored, not CPU addressable)\n",
0883                  res1, (unsigned long long)end + 1,
0884                  (unsigned long long)res1->end);
0885             res1->end = end;
0886         }
0887 
0888         resource_list_for_each_entry(entry2, resources) {
0889             res2 = entry2->res;
0890             if (!(res2->flags & type))
0891                 continue;
0892 
0893             /*
0894              * I don't like throwing away windows because then
0895              * our resources no longer match the ACPI _CRS, but
0896              * the kernel resource tree doesn't allow overlaps.
0897              */
0898             if (resource_union(res1, res2, res2)) {
0899                 dev_info(dev, "host bridge window expanded to %pR; %pR ignored\n",
0900                      res2, res1);
0901                 free = true;
0902                 goto next;
0903             }
0904         }
0905 
0906 next:
0907         resource_list_del(entry);
0908         if (free)
0909             resource_list_free_entry(entry);
0910         else
0911             resource_list_add_tail(entry, resources);
0912     }
0913 }
0914 
0915 static void acpi_pci_root_remap_iospace(struct fwnode_handle *fwnode,
0916             struct resource_entry *entry)
0917 {
0918 #ifdef PCI_IOBASE
0919     struct resource *res = entry->res;
0920     resource_size_t cpu_addr = res->start;
0921     resource_size_t pci_addr = cpu_addr - entry->offset;
0922     resource_size_t length = resource_size(res);
0923     unsigned long port;
0924 
0925     if (pci_register_io_range(fwnode, cpu_addr, length))
0926         goto err;
0927 
0928     port = pci_address_to_pio(cpu_addr);
0929     if (port == (unsigned long)-1)
0930         goto err;
0931 
0932     res->start = port;
0933     res->end = port + length - 1;
0934     entry->offset = port - pci_addr;
0935 
0936     if (pci_remap_iospace(res, cpu_addr) < 0)
0937         goto err;
0938 
0939     pr_info("Remapped I/O %pa to %pR\n", &cpu_addr, res);
0940     return;
0941 err:
0942     res->flags |= IORESOURCE_DISABLED;
0943 #endif
0944 }
0945 
0946 int acpi_pci_probe_root_resources(struct acpi_pci_root_info *info)
0947 {
0948     int ret;
0949     struct list_head *list = &info->resources;
0950     struct acpi_device *device = info->bridge;
0951     struct resource_entry *entry, *tmp;
0952     unsigned long flags;
0953 
0954     flags = IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT;
0955     ret = acpi_dev_get_resources(device, list,
0956                      acpi_dev_filter_resource_type_cb,
0957                      (void *)flags);
0958     if (ret < 0)
0959         dev_warn(&device->dev,
0960              "failed to parse _CRS method, error code %d\n", ret);
0961     else if (ret == 0)
0962         dev_dbg(&device->dev,
0963             "no IO and memory resources present in _CRS\n");
0964     else {
0965         resource_list_for_each_entry_safe(entry, tmp, list) {
0966             if (entry->res->flags & IORESOURCE_IO)
0967                 acpi_pci_root_remap_iospace(&device->fwnode,
0968                         entry);
0969 
0970             if (entry->res->flags & IORESOURCE_DISABLED)
0971                 resource_list_destroy_entry(entry);
0972             else
0973                 entry->res->name = info->name;
0974         }
0975         acpi_pci_root_validate_resources(&device->dev, list,
0976                          IORESOURCE_MEM);
0977         acpi_pci_root_validate_resources(&device->dev, list,
0978                          IORESOURCE_IO);
0979     }
0980 
0981     return ret;
0982 }
0983 
0984 static void pci_acpi_root_add_resources(struct acpi_pci_root_info *info)
0985 {
0986     struct resource_entry *entry, *tmp;
0987     struct resource *res, *conflict, *root = NULL;
0988 
0989     resource_list_for_each_entry_safe(entry, tmp, &info->resources) {
0990         res = entry->res;
0991         if (res->flags & IORESOURCE_MEM)
0992             root = &iomem_resource;
0993         else if (res->flags & IORESOURCE_IO)
0994             root = &ioport_resource;
0995         else
0996             continue;
0997 
0998         /*
0999          * Some legacy x86 host bridge drivers use iomem_resource and
1000          * ioport_resource as default resource pool, skip it.
1001          */
1002         if (res == root)
1003             continue;
1004 
1005         conflict = insert_resource_conflict(root, res);
1006         if (conflict) {
1007             dev_info(&info->bridge->dev,
1008                  "ignoring host bridge window %pR (conflicts with %s %pR)\n",
1009                  res, conflict->name, conflict);
1010             resource_list_destroy_entry(entry);
1011         }
1012     }
1013 }
1014 
1015 static void __acpi_pci_root_release_info(struct acpi_pci_root_info *info)
1016 {
1017     struct resource *res;
1018     struct resource_entry *entry, *tmp;
1019 
1020     if (!info)
1021         return;
1022 
1023     resource_list_for_each_entry_safe(entry, tmp, &info->resources) {
1024         res = entry->res;
1025         if (res->parent &&
1026             (res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
1027             release_resource(res);
1028         resource_list_destroy_entry(entry);
1029     }
1030 
1031     info->ops->release_info(info);
1032 }
1033 
1034 static void acpi_pci_root_release_info(struct pci_host_bridge *bridge)
1035 {
1036     struct resource *res;
1037     struct resource_entry *entry;
1038 
1039     resource_list_for_each_entry(entry, &bridge->windows) {
1040         res = entry->res;
1041         if (res->flags & IORESOURCE_IO)
1042             pci_unmap_iospace(res);
1043         if (res->parent &&
1044             (res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
1045             release_resource(res);
1046     }
1047     __acpi_pci_root_release_info(bridge->release_data);
1048 }
1049 
1050 struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
1051                      struct acpi_pci_root_ops *ops,
1052                      struct acpi_pci_root_info *info,
1053                      void *sysdata)
1054 {
1055     int ret, busnum = root->secondary.start;
1056     struct acpi_device *device = root->device;
1057     int node = acpi_get_node(device->handle);
1058     struct pci_bus *bus;
1059     struct pci_host_bridge *host_bridge;
1060     union acpi_object *obj;
1061 
1062     info->root = root;
1063     info->bridge = device;
1064     info->ops = ops;
1065     INIT_LIST_HEAD(&info->resources);
1066     snprintf(info->name, sizeof(info->name), "PCI Bus %04x:%02x",
1067          root->segment, busnum);
1068 
1069     if (ops->init_info && ops->init_info(info))
1070         goto out_release_info;
1071     if (ops->prepare_resources)
1072         ret = ops->prepare_resources(info);
1073     else
1074         ret = acpi_pci_probe_root_resources(info);
1075     if (ret < 0)
1076         goto out_release_info;
1077 
1078     pci_acpi_root_add_resources(info);
1079     pci_add_resource(&info->resources, &root->secondary);
1080     bus = pci_create_root_bus(NULL, busnum, ops->pci_ops,
1081                   sysdata, &info->resources);
1082     if (!bus)
1083         goto out_release_info;
1084 
1085     host_bridge = to_pci_host_bridge(bus->bridge);
1086     if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL))
1087         host_bridge->native_pcie_hotplug = 0;
1088     if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL))
1089         host_bridge->native_shpc_hotplug = 0;
1090     if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL))
1091         host_bridge->native_aer = 0;
1092     if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL))
1093         host_bridge->native_pme = 0;
1094     if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL))
1095         host_bridge->native_ltr = 0;
1096     if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL))
1097         host_bridge->native_dpc = 0;
1098 
1099     /*
1100      * Evaluate the "PCI Boot Configuration" _DSM Function.  If it
1101      * exists and returns 0, we must preserve any PCI resource
1102      * assignments made by firmware for this host bridge.
1103      */
1104     obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 1,
1105                 DSM_PCI_PRESERVE_BOOT_CONFIG, NULL);
1106     if (obj && obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 0)
1107         host_bridge->preserve_config = 1;
1108     ACPI_FREE(obj);
1109 
1110     acpi_dev_power_up_children_with_adr(device);
1111 
1112     pci_scan_child_bus(bus);
1113     pci_set_host_bridge_release(host_bridge, acpi_pci_root_release_info,
1114                     info);
1115     if (node != NUMA_NO_NODE)
1116         dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node);
1117     return bus;
1118 
1119 out_release_info:
1120     __acpi_pci_root_release_info(info);
1121     return NULL;
1122 }
1123 
1124 void __init acpi_pci_root_init(void)
1125 {
1126     if (acpi_pci_disabled)
1127         return;
1128 
1129     pci_acpi_crs_quirks();
1130     acpi_scan_add_handler_with_hotplug(&pci_root_handler, "pci_root");
1131 }
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