platform/uv/uv_time.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * SGI RTC clock/timer routines.
0004  *
0005  *  (C) Copyright 2020 Hewlett Packard Enterprise Development LP
0006  *  Copyright (c) 2009-2013 Silicon Graphics, Inc.  All Rights Reserved.
0007  *  Copyright (c) Dimitri Sivanich
0008  */
0009 #include <linux/clockchips.h>
0010 #include <linux/slab.h>
0011
0012 #include <asm/uv/uv_mmrs.h>
0013 #include <asm/uv/uv_hub.h>
0014 #include <asm/uv/bios.h>
0015 #include <asm/uv/uv.h>
0016 #include <asm/apic.h>
0017 #include <asm/cpu.h>
0018
0019 #define RTC_NAME        "sgi_rtc"
0020
0021 static u64 uv_read_rtc(struct clocksource *cs);
0022 static int uv_rtc_next_event(unsigned long, struct clock_event_device *);
0023 static int uv_rtc_shutdown(struct clock_event_device *evt);
0024
0025 static struct clocksource clocksource_uv = {
0026     .name       = RTC_NAME,
0027     .rating     = 299,
0028     .read       = uv_read_rtc,
0029     .mask       = (u64)UVH_RTC_REAL_TIME_CLOCK_MASK,
0030     .flags      = CLOCK_SOURCE_IS_CONTINUOUS,
0031 };
0032
0033 static struct clock_event_device clock_event_device_uv = {
0034     .name           = RTC_NAME,
0035     .features       = CLOCK_EVT_FEAT_ONESHOT,
0036     .shift          = 20,
0037     .rating         = 400,
0038     .irq            = -1,
0039     .set_next_event     = uv_rtc_next_event,
0040     .set_state_shutdown = uv_rtc_shutdown,
0041     .event_handler      = NULL,
0042 };
0043
0044 static DEFINE_PER_CPU(struct clock_event_device, cpu_ced);
0045
0046 /* There is one of these allocated per node */
0047 struct uv_rtc_timer_head {
0048     spinlock_t  lock;
0049     /* next cpu waiting for timer, local node relative: */
0050     int     next_cpu;
0051     /* number of cpus on this node: */
0052     int     ncpus;
0053     struct {
0054         int lcpu;       /* systemwide logical cpu number */
0055         u64 expires;    /* next timer expiration for this cpu */
0056     } cpu[];
0057 };
0058
0059 /*
0060  * Access to uv_rtc_timer_head via blade id.
0061  */
0062 static struct uv_rtc_timer_head     **blade_info __read_mostly;
0063
0064 static int              uv_rtc_evt_enable;
0065
0066 /*
0067  * Hardware interface routines
0068  */
0069
0070 /* Send IPIs to another node */
0071 static void uv_rtc_send_IPI(int cpu)
0072 {
0073     unsigned long apicid, val;
0074     int pnode;
0075
0076     apicid = cpu_physical_id(cpu);
0077     pnode = uv_apicid_to_pnode(apicid);
0078     val = (1UL << UVH_IPI_INT_SEND_SHFT) |
0079           (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
0080           (X86_PLATFORM_IPI_VECTOR << UVH_IPI_INT_VECTOR_SHFT);
0081
0082     uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
0083 }
0084
0085 /* Check for an RTC interrupt pending */
0086 static int uv_intr_pending(int pnode)
0087 {
0088     return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED2) &
0089         UVH_EVENT_OCCURRED2_RTC_1_MASK;
0090 }
0091
0092 /* Setup interrupt and return non-zero if early expiration occurred. */
0093 static int uv_setup_intr(int cpu, u64 expires)
0094 {
0095     u64 val;
0096     unsigned long apicid = cpu_physical_id(cpu);
0097     int pnode = uv_cpu_to_pnode(cpu);
0098
0099     uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
0100         UVH_RTC1_INT_CONFIG_M_MASK);
0101     uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L);
0102
0103     uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED2_ALIAS,
0104                   UVH_EVENT_OCCURRED2_RTC_1_MASK);
0105
0106     val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) |
0107         ((u64)apicid << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT);
0108
0109     /* Set configuration */
0110     uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val);
0111     /* Initialize comparator value */
0112     uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires);
0113
0114     if (uv_read_rtc(NULL) <= expires)
0115         return 0;
0116
0117     return !uv_intr_pending(pnode);
0118 }
0119
0120 /*
0121  * Per-cpu timer tracking routines
0122  */
0123
0124 static __init void uv_rtc_deallocate_timers(void)
0125 {
0126     int bid;
0127
0128     for_each_possible_blade(bid) {
0129         kfree(blade_info[bid]);
0130     }
0131     kfree(blade_info);
0132 }
0133
0134 /* Allocate per-node list of cpu timer expiration times. */
0135 static __init int uv_rtc_allocate_timers(void)
0136 {
0137     int cpu;
0138
0139     blade_info = kcalloc(uv_possible_blades, sizeof(void *), GFP_KERNEL);
0140     if (!blade_info)
0141         return -ENOMEM;
0142
0143     for_each_present_cpu(cpu) {
0144         int nid = cpu_to_node(cpu);
0145         int bid = uv_cpu_to_blade_id(cpu);
0146         int bcpu = uv_cpu_blade_processor_id(cpu);
0147         struct uv_rtc_timer_head *head = blade_info[bid];
0148
0149         if (!head) {
0150             head = kmalloc_node(struct_size(head, cpu,
0151                 uv_blade_nr_possible_cpus(bid)),
0152                 GFP_KERNEL, nid);
0153             if (!head) {
0154                 uv_rtc_deallocate_timers();
0155                 return -ENOMEM;
0156             }
0157             spin_lock_init(&head->lock);
0158             head->ncpus = uv_blade_nr_possible_cpus(bid);
0159             head->next_cpu = -1;
0160             blade_info[bid] = head;
0161         }
0162
0163         head->cpu[bcpu].lcpu = cpu;
0164         head->cpu[bcpu].expires = ULLONG_MAX;
0165     }
0166
0167     return 0;
0168 }
0169
0170 /* Find and set the next expiring timer.  */
0171 static void uv_rtc_find_next_timer(struct uv_rtc_timer_head *head, int pnode)
0172 {
0173     u64 lowest = ULLONG_MAX;
0174     int c, bcpu = -1;
0175
0176     head->next_cpu = -1;
0177     for (c = 0; c < head->ncpus; c++) {
0178         u64 exp = head->cpu[c].expires;
0179         if (exp < lowest) {
0180             bcpu = c;
0181             lowest = exp;
0182         }
0183     }
0184     if (bcpu >= 0) {
0185         head->next_cpu = bcpu;
0186         c = head->cpu[bcpu].lcpu;
0187         if (uv_setup_intr(c, lowest))
0188             /* If we didn't set it up in time, trigger */
0189             uv_rtc_send_IPI(c);
0190     } else {
0191         uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
0192             UVH_RTC1_INT_CONFIG_M_MASK);
0193     }
0194 }
0195
0196 /*
0197  * Set expiration time for current cpu.
0198  *
0199  * Returns 1 if we missed the expiration time.
0200  */
0201 static int uv_rtc_set_timer(int cpu, u64 expires)
0202 {
0203     int pnode = uv_cpu_to_pnode(cpu);
0204     int bid = uv_cpu_to_blade_id(cpu);
0205     struct uv_rtc_timer_head *head = blade_info[bid];
0206     int bcpu = uv_cpu_blade_processor_id(cpu);
0207     u64 *t = &head->cpu[bcpu].expires;
0208     unsigned long flags;
0209     int next_cpu;
0210
0211     spin_lock_irqsave(&head->lock, flags);
0212
0213     next_cpu = head->next_cpu;
0214     *t = expires;
0215
0216     /* Will this one be next to go off? */
0217     if (next_cpu < 0 || bcpu == next_cpu ||
0218             expires < head->cpu[next_cpu].expires) {
0219         head->next_cpu = bcpu;
0220         if (uv_setup_intr(cpu, expires)) {
0221             *t = ULLONG_MAX;
0222             uv_rtc_find_next_timer(head, pnode);
0223             spin_unlock_irqrestore(&head->lock, flags);
0224             return -ETIME;
0225         }
0226     }
0227
0228     spin_unlock_irqrestore(&head->lock, flags);
0229     return 0;
0230 }
0231
0232 /*
0233  * Unset expiration time for current cpu.
0234  *
0235  * Returns 1 if this timer was pending.
0236  */
0237 static int uv_rtc_unset_timer(int cpu, int force)
0238 {
0239     int pnode = uv_cpu_to_pnode(cpu);
0240     int bid = uv_cpu_to_blade_id(cpu);
0241     struct uv_rtc_timer_head *head = blade_info[bid];
0242     int bcpu = uv_cpu_blade_processor_id(cpu);
0243     u64 *t = &head->cpu[bcpu].expires;
0244     unsigned long flags;
0245     int rc = 0;
0246
0247     spin_lock_irqsave(&head->lock, flags);
0248
0249     if ((head->next_cpu == bcpu && uv_read_rtc(NULL) >= *t) || force)
0250         rc = 1;
0251
0252     if (rc) {
0253         *t = ULLONG_MAX;
0254         /* Was the hardware setup for this timer? */
0255         if (head->next_cpu == bcpu)
0256             uv_rtc_find_next_timer(head, pnode);
0257     }
0258
0259     spin_unlock_irqrestore(&head->lock, flags);
0260
0261     return rc;
0262 }
0263
0264
0265 /*
0266  * Kernel interface routines.
0267  */
0268
0269 /*
0270  * Read the RTC.
0271  *
0272  * Starting with HUB rev 2.0, the UV RTC register is replicated across all
0273  * cachelines of it's own page.  This allows faster simultaneous reads
0274  * from a given socket.
0275  */
0276 static u64 uv_read_rtc(struct clocksource *cs)
0277 {
0278     unsigned long offset;
0279
0280     if (uv_get_min_hub_revision_id() == 1)
0281         offset = 0;
0282     else
0283         offset = (uv_blade_processor_id() * L1_CACHE_BYTES) % PAGE_SIZE;
0284
0285     return (u64)uv_read_local_mmr(UVH_RTC | offset);
0286 }
0287
0288 /*
0289  * Program the next event, relative to now
0290  */
0291 static int uv_rtc_next_event(unsigned long delta,
0292                  struct clock_event_device *ced)
0293 {
0294     int ced_cpu = cpumask_first(ced->cpumask);
0295
0296     return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc(NULL));
0297 }
0298
0299 /*
0300  * Shutdown the RTC timer
0301  */
0302 static int uv_rtc_shutdown(struct clock_event_device *evt)
0303 {
0304     int ced_cpu = cpumask_first(evt->cpumask);
0305
0306     uv_rtc_unset_timer(ced_cpu, 1);
0307     return 0;
0308 }
0309
0310 static void uv_rtc_interrupt(void)
0311 {
0312     int cpu = smp_processor_id();
0313     struct clock_event_device *ced = &per_cpu(cpu_ced, cpu);
0314
0315     if (!ced || !ced->event_handler)
0316         return;
0317
0318     if (uv_rtc_unset_timer(cpu, 0) != 1)
0319         return;
0320
0321     ced->event_handler(ced);
0322 }
0323
0324 static int __init uv_enable_evt_rtc(char *str)
0325 {
0326     uv_rtc_evt_enable = 1;
0327
0328     return 1;
0329 }
0330 __setup("uvrtcevt", uv_enable_evt_rtc);
0331
0332 static __init void uv_rtc_register_clockevents(struct work_struct *dummy)
0333 {
0334     struct clock_event_device *ced = this_cpu_ptr(&cpu_ced);
0335
0336     *ced = clock_event_device_uv;
0337     ced->cpumask = cpumask_of(smp_processor_id());
0338     clockevents_register_device(ced);
0339 }
0340
0341 static __init int uv_rtc_setup_clock(void)
0342 {
0343     int rc;
0344
0345     if (!is_uv_system())
0346         return -ENODEV;
0347
0348     rc = clocksource_register_hz(&clocksource_uv, sn_rtc_cycles_per_second);
0349     if (rc)
0350         printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc);
0351     else
0352         printk(KERN_INFO "UV RTC clocksource registered freq %lu MHz\n",
0353             sn_rtc_cycles_per_second/(unsigned long)1E6);
0354
0355     if (rc || !uv_rtc_evt_enable || x86_platform_ipi_callback)
0356         return rc;
0357
0358     /* Setup and register clockevents */
0359     rc = uv_rtc_allocate_timers();
0360     if (rc)
0361         goto error;
0362
0363     x86_platform_ipi_callback = uv_rtc_interrupt;
0364
0365     clock_event_device_uv.mult = div_sc(sn_rtc_cycles_per_second,
0366                 NSEC_PER_SEC, clock_event_device_uv.shift);
0367
0368     clock_event_device_uv.min_delta_ns = NSEC_PER_SEC /
0369                         sn_rtc_cycles_per_second;
0370     clock_event_device_uv.min_delta_ticks = 1;
0371
0372     clock_event_device_uv.max_delta_ns = clocksource_uv.mask *
0373                 (NSEC_PER_SEC / sn_rtc_cycles_per_second);
0374     clock_event_device_uv.max_delta_ticks = clocksource_uv.mask;
0375
0376     rc = schedule_on_each_cpu(uv_rtc_register_clockevents);
0377     if (rc) {
0378         x86_platform_ipi_callback = NULL;
0379         uv_rtc_deallocate_timers();
0380         goto error;
0381     }
0382
0383     printk(KERN_INFO "UV RTC clockevents registered\n");
0384
0385     return 0;
0386
0387 error:
0388     clocksource_unregister(&clocksource_uv);
0389     printk(KERN_INFO "UV RTC clockevents failed rc %d\n", rc);
0390
0391     return rc;
0392 }
0393 arch_initcall(uv_rtc_setup_clock);