platform/uv/uv_irq.c

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * SGI UV IRQ functions
0007  *
0008  * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
0009  */
0010
0011 #include <linux/export.h>
0012 #include <linux/rbtree.h>
0013 #include <linux/slab.h>
0014 #include <linux/irq.h>
0015
0016 #include <asm/irqdomain.h>
0017 #include <asm/apic.h>
0018 #include <asm/uv/uv_irq.h>
0019 #include <asm/uv/uv_hub.h>
0020
0021 /* MMR offset and pnode of hub sourcing interrupts for a given irq */
0022 struct uv_irq_2_mmr_pnode {
0023     unsigned long       offset;
0024     int         pnode;
0025 };
0026
0027 static void uv_program_mmr(struct irq_cfg *cfg, struct uv_irq_2_mmr_pnode *info)
0028 {
0029     unsigned long mmr_value;
0030     struct uv_IO_APIC_route_entry *entry;
0031
0032     BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) !=
0033              sizeof(unsigned long));
0034
0035     mmr_value = 0;
0036     entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
0037     entry->vector       = cfg->vector;
0038     entry->delivery_mode    = apic->delivery_mode;
0039     entry->dest_mode    = apic->dest_mode_logical;
0040     entry->polarity     = 0;
0041     entry->trigger      = 0;
0042     entry->mask     = 0;
0043     entry->dest     = cfg->dest_apicid;
0044
0045     uv_write_global_mmr64(info->pnode, info->offset, mmr_value);
0046 }
0047
0048 static void uv_noop(struct irq_data *data) { }
0049
0050 static int
0051 uv_set_irq_affinity(struct irq_data *data, const struct cpumask *mask,
0052             bool force)
0053 {
0054     struct irq_data *parent = data->parent_data;
0055     struct irq_cfg *cfg = irqd_cfg(data);
0056     int ret;
0057
0058     ret = parent->chip->irq_set_affinity(parent, mask, force);
0059     if (ret >= 0) {
0060         uv_program_mmr(cfg, data->chip_data);
0061         send_cleanup_vector(cfg);
0062     }
0063
0064     return ret;
0065 }
0066
0067 static struct irq_chip uv_irq_chip = {
0068     .name           = "UV-CORE",
0069     .irq_mask       = uv_noop,
0070     .irq_unmask     = uv_noop,
0071     .irq_eoi        = apic_ack_irq,
0072     .irq_set_affinity   = uv_set_irq_affinity,
0073 };
0074
0075 static int uv_domain_alloc(struct irq_domain *domain, unsigned int virq,
0076                unsigned int nr_irqs, void *arg)
0077 {
0078     struct uv_irq_2_mmr_pnode *chip_data;
0079     struct irq_alloc_info *info = arg;
0080     struct irq_data *irq_data = irq_domain_get_irq_data(domain, virq);
0081     int ret;
0082
0083     if (nr_irqs > 1 || !info || info->type != X86_IRQ_ALLOC_TYPE_UV)
0084         return -EINVAL;
0085
0086     chip_data = kmalloc_node(sizeof(*chip_data), GFP_KERNEL,
0087                  irq_data_get_node(irq_data));
0088     if (!chip_data)
0089         return -ENOMEM;
0090
0091     ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
0092     if (ret >= 0) {
0093         if (info->uv.limit == UV_AFFINITY_CPU)
0094             irq_set_status_flags(virq, IRQ_NO_BALANCING);
0095         else
0096             irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
0097
0098         chip_data->pnode = uv_blade_to_pnode(info->uv.blade);
0099         chip_data->offset = info->uv.offset;
0100         irq_domain_set_info(domain, virq, virq, &uv_irq_chip, chip_data,
0101                     handle_percpu_irq, NULL, info->uv.name);
0102     } else {
0103         kfree(chip_data);
0104     }
0105
0106     return ret;
0107 }
0108
0109 static void uv_domain_free(struct irq_domain *domain, unsigned int virq,
0110                unsigned int nr_irqs)
0111 {
0112     struct irq_data *irq_data = irq_domain_get_irq_data(domain, virq);
0113
0114     BUG_ON(nr_irqs != 1);
0115     kfree(irq_data->chip_data);
0116     irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
0117     irq_clear_status_flags(virq, IRQ_NO_BALANCING);
0118     irq_domain_free_irqs_top(domain, virq, nr_irqs);
0119 }
0120
0121 /*
0122  * Re-target the irq to the specified CPU and enable the specified MMR located
0123  * on the specified blade to allow the sending of MSIs to the specified CPU.
0124  */
0125 static int uv_domain_activate(struct irq_domain *domain,
0126                   struct irq_data *irq_data, bool reserve)
0127 {
0128     uv_program_mmr(irqd_cfg(irq_data), irq_data->chip_data);
0129     return 0;
0130 }
0131
0132 /*
0133  * Disable the specified MMR located on the specified blade so that MSIs are
0134  * longer allowed to be sent.
0135  */
0136 static void uv_domain_deactivate(struct irq_domain *domain,
0137                  struct irq_data *irq_data)
0138 {
0139     unsigned long mmr_value;
0140     struct uv_IO_APIC_route_entry *entry;
0141
0142     mmr_value = 0;
0143     entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
0144     entry->mask = 1;
0145     uv_program_mmr(irqd_cfg(irq_data), irq_data->chip_data);
0146 }
0147
0148 static const struct irq_domain_ops uv_domain_ops = {
0149     .alloc      = uv_domain_alloc,
0150     .free       = uv_domain_free,
0151     .activate   = uv_domain_activate,
0152     .deactivate = uv_domain_deactivate,
0153 };
0154
0155 static struct irq_domain *uv_get_irq_domain(void)
0156 {
0157     static struct irq_domain *uv_domain;
0158     static DEFINE_MUTEX(uv_lock);
0159     struct fwnode_handle *fn;
0160
0161     mutex_lock(&uv_lock);
0162     if (uv_domain)
0163         goto out;
0164
0165     fn = irq_domain_alloc_named_fwnode("UV-CORE");
0166     if (!fn)
0167         goto out;
0168
0169     uv_domain = irq_domain_create_tree(fn, &uv_domain_ops, NULL);
0170     if (uv_domain)
0171         uv_domain->parent = x86_vector_domain;
0172     else
0173         irq_domain_free_fwnode(fn);
0174 out:
0175     mutex_unlock(&uv_lock);
0176
0177     return uv_domain;
0178 }
0179
0180 /*
0181  * Set up a mapping of an available irq and vector, and enable the specified
0182  * MMR that defines the MSI that is to be sent to the specified CPU when an
0183  * interrupt is raised.
0184  */
0185 int uv_setup_irq(char *irq_name, int cpu, int mmr_blade,
0186          unsigned long mmr_offset, int limit)
0187 {
0188     struct irq_alloc_info info;
0189     struct irq_domain *domain = uv_get_irq_domain();
0190
0191     if (!domain)
0192         return -ENOMEM;
0193
0194     init_irq_alloc_info(&info, cpumask_of(cpu));
0195     info.type = X86_IRQ_ALLOC_TYPE_UV;
0196     info.uv.limit = limit;
0197     info.uv.blade = mmr_blade;
0198     info.uv.offset = mmr_offset;
0199     info.uv.name = irq_name;
0200
0201     return irq_domain_alloc_irqs(domain, 1,
0202                      uv_blade_to_memory_nid(mmr_blade), &info);
0203 }
0204 EXPORT_SYMBOL_GPL(uv_setup_irq);
0205
0206 /*
0207  * Tear down a mapping of an irq and vector, and disable the specified MMR that
0208  * defined the MSI that was to be sent to the specified CPU when an interrupt
0209  * was raised.
0210  *
0211  * Set mmr_blade and mmr_offset to what was passed in on uv_setup_irq().
0212  */
0213 void uv_teardown_irq(unsigned int irq)
0214 {
0215     irq_domain_free_irqs(irq, 1);
0216 }
0217 EXPORT_SYMBOL_GPL(uv_teardown_irq);