platform/intel-mid/pwr.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Intel MID Power Management Unit (PWRMU) device driver
0004  *
0005  * Copyright (C) 2016, Intel Corporation
0006  *
0007  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
0008  *
0009  * Intel MID Power Management Unit device driver handles the South Complex PCI
0010  * devices such as GPDMA, SPI, I2C, PWM, and so on. By default PCI core
0011  * modifies bits in PMCSR register in the PCI configuration space. This is not
0012  * enough on some SoCs like Intel Tangier. In such case PCI core sets a new
0013  * power state of the device in question through a PM hook registered in struct
0014  * pci_platform_pm_ops (see drivers/pci/pci-mid.c).
0015  */
0016
0017 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0018
0019 #include <linux/delay.h>
0020 #include <linux/errno.h>
0021 #include <linux/interrupt.h>
0022 #include <linux/kernel.h>
0023 #include <linux/export.h>
0024 #include <linux/mutex.h>
0025 #include <linux/pci.h>
0026
0027 #include <asm/intel-mid.h>
0028
0029 /* Registers */
0030 #define PM_STS          0x00
0031 #define PM_CMD          0x04
0032 #define PM_ICS          0x08
0033 #define PM_WKC(x)       (0x10 + (x) * 4)
0034 #define PM_WKS(x)       (0x18 + (x) * 4)
0035 #define PM_SSC(x)       (0x20 + (x) * 4)
0036 #define PM_SSS(x)       (0x30 + (x) * 4)
0037
0038 /* Bits in PM_STS */
0039 #define PM_STS_BUSY     (1 << 8)
0040
0041 /* Bits in PM_CMD */
0042 #define PM_CMD_CMD(x)       ((x) << 0)
0043 #define PM_CMD_IOC      (1 << 8)
0044 #define PM_CMD_CM_NOP       (0 << 9)
0045 #define PM_CMD_CM_IMMEDIATE (1 << 9)
0046 #define PM_CMD_CM_DELAY     (2 << 9)
0047 #define PM_CMD_CM_TRIGGER   (3 << 9)
0048
0049 /* System states */
0050 #define PM_CMD_SYS_STATE_S5 (5 << 16)
0051
0052 /* Trigger variants */
0053 #define PM_CMD_CFG_TRIGGER_NC   (3 << 19)
0054
0055 /* Message to wait for TRIGGER_NC case */
0056 #define TRIGGER_NC_MSG_2    (2 << 22)
0057
0058 /* List of commands */
0059 #define CMD_SET_CFG     0x01
0060
0061 /* Bits in PM_ICS */
0062 #define PM_ICS_INT_STATUS(x)    ((x) & 0xff)
0063 #define PM_ICS_IE       (1 << 8)
0064 #define PM_ICS_IP       (1 << 9)
0065 #define PM_ICS_SW_INT_STS   (1 << 10)
0066
0067 /* List of interrupts */
0068 #define INT_INVALID     0
0069 #define INT_CMD_COMPLETE    1
0070 #define INT_CMD_ERR     2
0071 #define INT_WAKE_EVENT      3
0072 #define INT_LSS_POWER_ERR   4
0073 #define INT_S0iX_MSG_ERR    5
0074 #define INT_NO_C6       6
0075 #define INT_TRIGGER_ERR     7
0076 #define INT_INACTIVITY      8
0077
0078 /* South Complex devices */
0079 #define LSS_MAX_SHARED_DEVS 4
0080 #define LSS_MAX_DEVS        64
0081
0082 #define LSS_WS_BITS     1   /* wake state width */
0083 #define LSS_PWS_BITS        2   /* power state width */
0084
0085 /* Supported device IDs */
0086 #define PCI_DEVICE_ID_PENWELL   0x0828
0087 #define PCI_DEVICE_ID_TANGIER   0x11a1
0088
0089 struct mid_pwr_dev {
0090     struct pci_dev *pdev;
0091     pci_power_t state;
0092 };
0093
0094 struct mid_pwr {
0095     struct device *dev;
0096     void __iomem *regs;
0097     int irq;
0098     bool available;
0099
0100     struct mutex lock;
0101     struct mid_pwr_dev lss[LSS_MAX_DEVS][LSS_MAX_SHARED_DEVS];
0102 };
0103
0104 static struct mid_pwr *midpwr;
0105
0106 static u32 mid_pwr_get_state(struct mid_pwr *pwr, int reg)
0107 {
0108     return readl(pwr->regs + PM_SSS(reg));
0109 }
0110
0111 static void mid_pwr_set_state(struct mid_pwr *pwr, int reg, u32 value)
0112 {
0113     writel(value, pwr->regs + PM_SSC(reg));
0114 }
0115
0116 static void mid_pwr_set_wake(struct mid_pwr *pwr, int reg, u32 value)
0117 {
0118     writel(value, pwr->regs + PM_WKC(reg));
0119 }
0120
0121 static void mid_pwr_interrupt_disable(struct mid_pwr *pwr)
0122 {
0123     writel(~PM_ICS_IE, pwr->regs + PM_ICS);
0124 }
0125
0126 static bool mid_pwr_is_busy(struct mid_pwr *pwr)
0127 {
0128     return !!(readl(pwr->regs + PM_STS) & PM_STS_BUSY);
0129 }
0130
0131 /* Wait 500ms that the latest PWRMU command finished */
0132 static int mid_pwr_wait(struct mid_pwr *pwr)
0133 {
0134     unsigned int count = 500000;
0135     bool busy;
0136
0137     do {
0138         busy = mid_pwr_is_busy(pwr);
0139         if (!busy)
0140             return 0;
0141         udelay(1);
0142     } while (--count);
0143
0144     return -EBUSY;
0145 }
0146
0147 static int mid_pwr_wait_for_cmd(struct mid_pwr *pwr, u8 cmd)
0148 {
0149     writel(PM_CMD_CMD(cmd) | PM_CMD_CM_IMMEDIATE, pwr->regs + PM_CMD);
0150     return mid_pwr_wait(pwr);
0151 }
0152
0153 static int __update_power_state(struct mid_pwr *pwr, int reg, int bit, int new)
0154 {
0155     int curstate;
0156     u32 power;
0157     int ret;
0158
0159     /* Check if the device is already in desired state */
0160     power = mid_pwr_get_state(pwr, reg);
0161     curstate = (power >> bit) & 3;
0162     if (curstate == new)
0163         return 0;
0164
0165     /* Update the power state */
0166     mid_pwr_set_state(pwr, reg, (power & ~(3 << bit)) | (new << bit));
0167
0168     /* Send command to SCU */
0169     ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);
0170     if (ret)
0171         return ret;
0172
0173     /* Check if the device is already in desired state */
0174     power = mid_pwr_get_state(pwr, reg);
0175     curstate = (power >> bit) & 3;
0176     if (curstate != new)
0177         return -EAGAIN;
0178
0179     return 0;
0180 }
0181
0182 static pci_power_t __find_weakest_power_state(struct mid_pwr_dev *lss,
0183                           struct pci_dev *pdev,
0184                           pci_power_t state)
0185 {
0186     pci_power_t weakest = PCI_D3hot;
0187     unsigned int j;
0188
0189     /* Find device in cache or first free cell */
0190     for (j = 0; j < LSS_MAX_SHARED_DEVS; j++) {
0191         if (lss[j].pdev == pdev || !lss[j].pdev)
0192             break;
0193     }
0194
0195     /* Store the desired state in cache */
0196     if (j < LSS_MAX_SHARED_DEVS) {
0197         lss[j].pdev = pdev;
0198         lss[j].state = state;
0199     } else {
0200         dev_WARN(&pdev->dev, "No room for device in PWRMU LSS cache\n");
0201         weakest = state;
0202     }
0203
0204     /* Find the power state we may use */
0205     for (j = 0; j < LSS_MAX_SHARED_DEVS; j++) {
0206         if (lss[j].state < weakest)
0207             weakest = lss[j].state;
0208     }
0209
0210     return weakest;
0211 }
0212
0213 static int __set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev,
0214                  pci_power_t state, int id, int reg, int bit)
0215 {
0216     const char *name;
0217     int ret;
0218
0219     state = __find_weakest_power_state(pwr->lss[id], pdev, state);
0220     name = pci_power_name(state);
0221
0222     ret = __update_power_state(pwr, reg, bit, (__force int)state);
0223     if (ret) {
0224         dev_warn(&pdev->dev, "Can't set power state %s: %d\n", name, ret);
0225         return ret;
0226     }
0227
0228     dev_vdbg(&pdev->dev, "Set power state %s\n", name);
0229     return 0;
0230 }
0231
0232 static int mid_pwr_set_power_state(struct mid_pwr *pwr, struct pci_dev *pdev,
0233                    pci_power_t state)
0234 {
0235     int id, reg, bit;
0236     int ret;
0237
0238     id = intel_mid_pwr_get_lss_id(pdev);
0239     if (id < 0)
0240         return id;
0241
0242     reg = (id * LSS_PWS_BITS) / 32;
0243     bit = (id * LSS_PWS_BITS) % 32;
0244
0245     /* We support states between PCI_D0 and PCI_D3hot */
0246     if (state < PCI_D0)
0247         state = PCI_D0;
0248     if (state > PCI_D3hot)
0249         state = PCI_D3hot;
0250
0251     mutex_lock(&pwr->lock);
0252     ret = __set_power_state(pwr, pdev, state, id, reg, bit);
0253     mutex_unlock(&pwr->lock);
0254     return ret;
0255 }
0256
0257 int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
0258 {
0259     struct mid_pwr *pwr = midpwr;
0260     int ret = 0;
0261
0262     might_sleep();
0263
0264     if (pwr && pwr->available)
0265         ret = mid_pwr_set_power_state(pwr, pdev, state);
0266     dev_vdbg(&pdev->dev, "set_power_state() returns %d\n", ret);
0267
0268     return 0;
0269 }
0270
0271 pci_power_t intel_mid_pci_get_power_state(struct pci_dev *pdev)
0272 {
0273     struct mid_pwr *pwr = midpwr;
0274     int id, reg, bit;
0275     u32 power;
0276
0277     if (!pwr || !pwr->available)
0278         return PCI_UNKNOWN;
0279
0280     id = intel_mid_pwr_get_lss_id(pdev);
0281     if (id < 0)
0282         return PCI_UNKNOWN;
0283
0284     reg = (id * LSS_PWS_BITS) / 32;
0285     bit = (id * LSS_PWS_BITS) % 32;
0286     power = mid_pwr_get_state(pwr, reg);
0287     return (__force pci_power_t)((power >> bit) & 3);
0288 }
0289
0290 void intel_mid_pwr_power_off(void)
0291 {
0292     struct mid_pwr *pwr = midpwr;
0293     u32 cmd = PM_CMD_SYS_STATE_S5 |
0294           PM_CMD_CMD(CMD_SET_CFG) |
0295           PM_CMD_CM_TRIGGER |
0296           PM_CMD_CFG_TRIGGER_NC |
0297           TRIGGER_NC_MSG_2;
0298
0299     /* Send command to SCU */
0300     writel(cmd, pwr->regs + PM_CMD);
0301     mid_pwr_wait(pwr);
0302 }
0303
0304 int intel_mid_pwr_get_lss_id(struct pci_dev *pdev)
0305 {
0306     int vndr;
0307     u8 id;
0308
0309     /*
0310      * Mapping to PWRMU index is kept in the Logical SubSystem ID byte of
0311      * Vendor capability.
0312      */
0313     vndr = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
0314     if (!vndr)
0315         return -EINVAL;
0316
0317     /* Read the Logical SubSystem ID byte */
0318     pci_read_config_byte(pdev, vndr + INTEL_MID_PWR_LSS_OFFSET, &id);
0319     if (!(id & INTEL_MID_PWR_LSS_TYPE))
0320         return -ENODEV;
0321
0322     id &= ~INTEL_MID_PWR_LSS_TYPE;
0323     if (id >= LSS_MAX_DEVS)
0324         return -ERANGE;
0325
0326     return id;
0327 }
0328
0329 static irqreturn_t mid_pwr_irq_handler(int irq, void *dev_id)
0330 {
0331     struct mid_pwr *pwr = dev_id;
0332     u32 ics;
0333
0334     ics = readl(pwr->regs + PM_ICS);
0335     if (!(ics & PM_ICS_IP))
0336         return IRQ_NONE;
0337
0338     writel(ics | PM_ICS_IP, pwr->regs + PM_ICS);
0339
0340     dev_warn(pwr->dev, "Unexpected IRQ: %#x\n", PM_ICS_INT_STATUS(ics));
0341     return IRQ_HANDLED;
0342 }
0343
0344 struct mid_pwr_device_info {
0345     int (*set_initial_state)(struct mid_pwr *pwr);
0346 };
0347
0348 static int mid_pwr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
0349 {
0350     struct mid_pwr_device_info *info = (void *)id->driver_data;
0351     struct device *dev = &pdev->dev;
0352     struct mid_pwr *pwr;
0353     int ret;
0354
0355     ret = pcim_enable_device(pdev);
0356     if (ret < 0) {
0357         dev_err(&pdev->dev, "error: could not enable device\n");
0358         return ret;
0359     }
0360
0361     ret = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
0362     if (ret) {
0363         dev_err(&pdev->dev, "I/O memory remapping failed\n");
0364         return ret;
0365     }
0366
0367     pwr = devm_kzalloc(dev, sizeof(*pwr), GFP_KERNEL);
0368     if (!pwr)
0369         return -ENOMEM;
0370
0371     pwr->dev = dev;
0372     pwr->regs = pcim_iomap_table(pdev)[0];
0373     pwr->irq = pdev->irq;
0374
0375     mutex_init(&pwr->lock);
0376
0377     /* Disable interrupts */
0378     mid_pwr_interrupt_disable(pwr);
0379
0380     if (info && info->set_initial_state) {
0381         ret = info->set_initial_state(pwr);
0382         if (ret)
0383             dev_warn(dev, "Can't set initial state: %d\n", ret);
0384     }
0385
0386     ret = devm_request_irq(dev, pdev->irq, mid_pwr_irq_handler,
0387                    IRQF_NO_SUSPEND, pci_name(pdev), pwr);
0388     if (ret)
0389         return ret;
0390
0391     pwr->available = true;
0392     midpwr = pwr;
0393
0394     pci_set_drvdata(pdev, pwr);
0395     return 0;
0396 }
0397
0398 static int mid_set_initial_state(struct mid_pwr *pwr, const u32 *states)
0399 {
0400     unsigned int i, j;
0401     int ret;
0402
0403     /*
0404      * Enable wake events.
0405      *
0406      * PWRMU supports up to 32 sources for wake up the system. Ungate them
0407      * all here.
0408      */
0409     mid_pwr_set_wake(pwr, 0, 0xffffffff);
0410     mid_pwr_set_wake(pwr, 1, 0xffffffff);
0411
0412     /*
0413      * Power off South Complex devices.
0414      *
0415      * There is a map (see a note below) of 64 devices with 2 bits per each
0416      * on 32-bit HW registers. The following calls set all devices to one
0417      * known initial state, i.e. PCI_D3hot. This is done in conjunction
0418      * with PMCSR setting in arch/x86/pci/intel_mid_pci.c.
0419      *
0420      * NOTE: The actual device mapping is provided by a platform at run
0421      * time using vendor capability of PCI configuration space.
0422      */
0423     mid_pwr_set_state(pwr, 0, states[0]);
0424     mid_pwr_set_state(pwr, 1, states[1]);
0425     mid_pwr_set_state(pwr, 2, states[2]);
0426     mid_pwr_set_state(pwr, 3, states[3]);
0427
0428     /* Send command to SCU */
0429     ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);
0430     if (ret)
0431         return ret;
0432
0433     for (i = 0; i < LSS_MAX_DEVS; i++) {
0434         for (j = 0; j < LSS_MAX_SHARED_DEVS; j++)
0435             pwr->lss[i][j].state = PCI_D3hot;
0436     }
0437
0438     return 0;
0439 }
0440
0441 static int pnw_set_initial_state(struct mid_pwr *pwr)
0442 {
0443     /* On Penwell SRAM must stay powered on */
0444     static const u32 states[] = {
0445         0xf00fffff,     /* PM_SSC(0) */
0446         0xffffffff,     /* PM_SSC(1) */
0447         0xffffffff,     /* PM_SSC(2) */
0448         0xffffffff,     /* PM_SSC(3) */
0449     };
0450     return mid_set_initial_state(pwr, states);
0451 }
0452
0453 static int tng_set_initial_state(struct mid_pwr *pwr)
0454 {
0455     static const u32 states[] = {
0456         0xffffffff,     /* PM_SSC(0) */
0457         0xffffffff,     /* PM_SSC(1) */
0458         0xffffffff,     /* PM_SSC(2) */
0459         0xffffffff,     /* PM_SSC(3) */
0460     };
0461     return mid_set_initial_state(pwr, states);
0462 }
0463
0464 static const struct mid_pwr_device_info pnw_info = {
0465     .set_initial_state = pnw_set_initial_state,
0466 };
0467
0468 static const struct mid_pwr_device_info tng_info = {
0469     .set_initial_state = tng_set_initial_state,
0470 };
0471
0472 /* This table should be in sync with the one in drivers/pci/pci-mid.c */
0473 static const struct pci_device_id mid_pwr_pci_ids[] = {
0474     { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&pnw_info },
0475     { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&tng_info },
0476     {}
0477 };
0478
0479 static struct pci_driver mid_pwr_pci_driver = {
0480     .name       = "intel_mid_pwr",
0481     .probe      = mid_pwr_probe,
0482     .id_table   = mid_pwr_pci_ids,
0483 };
0484
0485 builtin_pci_driver(mid_pwr_pci_driver);