platform/intel-mid/intel-mid.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Intel MID platform setup code
0004  *
0005  * (C) Copyright 2008, 2012, 2021 Intel Corporation
0006  * Author: Jacob Pan (jacob.jun.pan@intel.com)
0007  * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
0008  */
0009
0010 #define pr_fmt(fmt) "intel_mid: " fmt
0011
0012 #include <linux/init.h>
0013 #include <linux/kernel.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/regulator/machine.h>
0016 #include <linux/scatterlist.h>
0017 #include <linux/irq.h>
0018 #include <linux/export.h>
0019 #include <linux/notifier.h>
0020
0021 #include <asm/setup.h>
0022 #include <asm/mpspec_def.h>
0023 #include <asm/hw_irq.h>
0024 #include <asm/apic.h>
0025 #include <asm/io_apic.h>
0026 #include <asm/intel-mid.h>
0027 #include <asm/io.h>
0028 #include <asm/i8259.h>
0029 #include <asm/intel_scu_ipc.h>
0030 #include <asm/reboot.h>
0031
0032 #define IPCMSG_COLD_OFF     0x80    /* Only for Tangier */
0033 #define IPCMSG_COLD_RESET   0xF1
0034
0035 static void intel_mid_power_off(void)
0036 {
0037     /* Shut down South Complex via PWRMU */
0038     intel_mid_pwr_power_off();
0039
0040     /* Only for Tangier, the rest will ignore this command */
0041     intel_scu_ipc_dev_simple_command(NULL, IPCMSG_COLD_OFF, 1);
0042 };
0043
0044 static void intel_mid_reboot(void)
0045 {
0046     intel_scu_ipc_dev_simple_command(NULL, IPCMSG_COLD_RESET, 0);
0047 }
0048
0049 static void __init intel_mid_time_init(void)
0050 {
0051     /* Lapic only, no apbt */
0052     x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
0053     x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
0054 }
0055
0056 static void intel_mid_arch_setup(void)
0057 {
0058     switch (boot_cpu_data.x86_model) {
0059     case 0x3C:
0060     case 0x4A:
0061         x86_platform.legacy.rtc = 1;
0062         break;
0063     default:
0064         break;
0065     }
0066
0067     /*
0068      * Intel MID platforms are using explicitly defined regulators.
0069      *
0070      * Let the regulator core know that we do not have any additional
0071      * regulators left. This lets it substitute unprovided regulators with
0072      * dummy ones:
0073      */
0074     regulator_has_full_constraints();
0075 }
0076
0077 /*
0078  * Moorestown does not have external NMI source nor port 0x61 to report
0079  * NMI status. The possible NMI sources are from pmu as a result of NMI
0080  * watchdog or lock debug. Reading io port 0x61 results in 0xff which
0081  * misled NMI handler.
0082  */
0083 static unsigned char intel_mid_get_nmi_reason(void)
0084 {
0085     return 0;
0086 }
0087
0088 /*
0089  * Moorestown specific x86_init function overrides and early setup
0090  * calls.
0091  */
0092 void __init x86_intel_mid_early_setup(void)
0093 {
0094     x86_init.resources.probe_roms = x86_init_noop;
0095     x86_init.resources.reserve_resources = x86_init_noop;
0096
0097     x86_init.timers.timer_init = intel_mid_time_init;
0098     x86_init.timers.setup_percpu_clockev = x86_init_noop;
0099
0100     x86_init.irqs.pre_vector_init = x86_init_noop;
0101
0102     x86_init.oem.arch_setup = intel_mid_arch_setup;
0103
0104     x86_platform.get_nmi_reason = intel_mid_get_nmi_reason;
0105
0106     x86_init.pci.arch_init = intel_mid_pci_init;
0107     x86_init.pci.fixup_irqs = x86_init_noop;
0108
0109     legacy_pic = &null_legacy_pic;
0110
0111     /*
0112      * Do nothing for now as everything needed done in
0113      * x86_intel_mid_early_setup() below.
0114      */
0115     x86_init.acpi.reduced_hw_early_init = x86_init_noop;
0116
0117     pm_power_off = intel_mid_power_off;
0118     machine_ops.emergency_restart  = intel_mid_reboot;
0119
0120     /* Avoid searching for BIOS MP tables */
0121     x86_init.mpparse.find_smp_config = x86_init_noop;
0122     x86_init.mpparse.get_smp_config = x86_init_uint_noop;
0123     set_bit(MP_BUS_ISA, mp_bus_not_pci);
0124 }