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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Xen PCI - handle PCI (INTx) and MSI infrastructure calls for PV, HVM and
0004  * initial domain support. We also handle the DSDT _PRT callbacks for GSI's
0005  * used in HVM and initial domain mode (PV does not parse ACPI, so it has no
0006  * concept of GSIs). Under PV we hook under the pnbbios API for IRQs and
0007  * 0xcf8 PCI configuration read/write.
0008  *
0009  *   Author: Ryan Wilson <hap9@epoch.ncsc.mil>
0010  *           Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
0011  *           Stefano Stabellini <stefano.stabellini@eu.citrix.com>
0012  */
0013 #include <linux/export.h>
0014 #include <linux/init.h>
0015 #include <linux/pci.h>
0016 #include <linux/acpi.h>
0017 
0018 #include <linux/io.h>
0019 #include <asm/io_apic.h>
0020 #include <asm/pci_x86.h>
0021 
0022 #include <asm/xen/hypervisor.h>
0023 
0024 #include <xen/features.h>
0025 #include <xen/events.h>
0026 #include <xen/pci.h>
0027 #include <asm/xen/pci.h>
0028 #include <asm/xen/cpuid.h>
0029 #include <asm/apic.h>
0030 #include <asm/acpi.h>
0031 #include <asm/i8259.h>
0032 
0033 static int xen_pcifront_enable_irq(struct pci_dev *dev)
0034 {
0035     int rc;
0036     int share = 1;
0037     int pirq;
0038     u8 gsi;
0039 
0040     rc = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi);
0041     if (rc < 0) {
0042         dev_warn(&dev->dev, "Xen PCI: failed to read interrupt line: %d\n",
0043              rc);
0044         return rc;
0045     }
0046     /* In PV DomU the Xen PCI backend puts the PIRQ in the interrupt line.*/
0047     pirq = gsi;
0048 
0049     if (gsi < nr_legacy_irqs())
0050         share = 0;
0051 
0052     rc = xen_bind_pirq_gsi_to_irq(gsi, pirq, share, "pcifront");
0053     if (rc < 0) {
0054         dev_warn(&dev->dev, "Xen PCI: failed to bind GSI%d (PIRQ%d) to IRQ: %d\n",
0055              gsi, pirq, rc);
0056         return rc;
0057     }
0058 
0059     dev->irq = rc;
0060     dev_info(&dev->dev, "Xen PCI mapped GSI%d to IRQ%d\n", gsi, dev->irq);
0061     return 0;
0062 }
0063 
0064 #ifdef CONFIG_ACPI
0065 static int xen_register_pirq(u32 gsi, int triggering, bool set_pirq)
0066 {
0067     int rc, pirq = -1, irq;
0068     struct physdev_map_pirq map_irq;
0069     int shareable = 0;
0070     char *name;
0071 
0072     irq = xen_irq_from_gsi(gsi);
0073     if (irq > 0)
0074         return irq;
0075 
0076     if (set_pirq)
0077         pirq = gsi;
0078 
0079     map_irq.domid = DOMID_SELF;
0080     map_irq.type = MAP_PIRQ_TYPE_GSI;
0081     map_irq.index = gsi;
0082     map_irq.pirq = pirq;
0083 
0084     rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
0085     if (rc) {
0086         printk(KERN_WARNING "xen map irq failed %d\n", rc);
0087         return -1;
0088     }
0089 
0090     if (triggering == ACPI_EDGE_SENSITIVE) {
0091         shareable = 0;
0092         name = "ioapic-edge";
0093     } else {
0094         shareable = 1;
0095         name = "ioapic-level";
0096     }
0097 
0098     irq = xen_bind_pirq_gsi_to_irq(gsi, map_irq.pirq, shareable, name);
0099     if (irq < 0)
0100         goto out;
0101 
0102     printk(KERN_DEBUG "xen: --> pirq=%d -> irq=%d (gsi=%d)\n", map_irq.pirq, irq, gsi);
0103 out:
0104     return irq;
0105 }
0106 
0107 static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi,
0108                      int trigger, int polarity)
0109 {
0110     if (!xen_hvm_domain())
0111         return -1;
0112 
0113     return xen_register_pirq(gsi, trigger,
0114                  false /* no mapping of GSI to PIRQ */);
0115 }
0116 
0117 #ifdef CONFIG_XEN_PV_DOM0
0118 static int xen_register_gsi(u32 gsi, int triggering, int polarity)
0119 {
0120     int rc, irq;
0121     struct physdev_setup_gsi setup_gsi;
0122 
0123     if (!xen_pv_domain())
0124         return -1;
0125 
0126     printk(KERN_DEBUG "xen: registering gsi %u triggering %d polarity %d\n",
0127             gsi, triggering, polarity);
0128 
0129     irq = xen_register_pirq(gsi, triggering, true);
0130 
0131     setup_gsi.gsi = gsi;
0132     setup_gsi.triggering = (triggering == ACPI_EDGE_SENSITIVE ? 0 : 1);
0133     setup_gsi.polarity = (polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
0134 
0135     rc = HYPERVISOR_physdev_op(PHYSDEVOP_setup_gsi, &setup_gsi);
0136     if (rc == -EEXIST)
0137         printk(KERN_INFO "Already setup the GSI :%d\n", gsi);
0138     else if (rc) {
0139         printk(KERN_ERR "Failed to setup GSI :%d, err_code:%d\n",
0140                 gsi, rc);
0141     }
0142 
0143     return irq;
0144 }
0145 
0146 static int acpi_register_gsi_xen(struct device *dev, u32 gsi,
0147                  int trigger, int polarity)
0148 {
0149     return xen_register_gsi(gsi, trigger, polarity);
0150 }
0151 #endif
0152 #endif
0153 
0154 #if defined(CONFIG_PCI_MSI)
0155 #include <linux/msi.h>
0156 
0157 struct xen_pci_frontend_ops *xen_pci_frontend;
0158 EXPORT_SYMBOL_GPL(xen_pci_frontend);
0159 
0160 struct xen_msi_ops {
0161     int (*setup_msi_irqs)(struct pci_dev *dev, int nvec, int type);
0162     void (*teardown_msi_irqs)(struct pci_dev *dev);
0163 };
0164 
0165 static struct xen_msi_ops xen_msi_ops __ro_after_init;
0166 
0167 static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
0168 {
0169     int irq, ret, i;
0170     struct msi_desc *msidesc;
0171     int *v;
0172 
0173     if (type == PCI_CAP_ID_MSI && nvec > 1)
0174         return 1;
0175 
0176     v = kcalloc(max(1, nvec), sizeof(int), GFP_KERNEL);
0177     if (!v)
0178         return -ENOMEM;
0179 
0180     if (type == PCI_CAP_ID_MSIX)
0181         ret = xen_pci_frontend_enable_msix(dev, v, nvec);
0182     else
0183         ret = xen_pci_frontend_enable_msi(dev, v);
0184     if (ret)
0185         goto error;
0186     i = 0;
0187     msi_for_each_desc(msidesc, &dev->dev, MSI_DESC_NOTASSOCIATED) {
0188         irq = xen_bind_pirq_msi_to_irq(dev, msidesc, v[i],
0189                            (type == PCI_CAP_ID_MSI) ? nvec : 1,
0190                            (type == PCI_CAP_ID_MSIX) ?
0191                            "pcifront-msi-x" :
0192                            "pcifront-msi",
0193                         DOMID_SELF);
0194         if (irq < 0) {
0195             ret = irq;
0196             goto free;
0197         }
0198         i++;
0199     }
0200     kfree(v);
0201     return 0;
0202 
0203 error:
0204     if (ret == -ENOSYS)
0205         dev_err(&dev->dev, "Xen PCI frontend has not registered MSI/MSI-X support!\n");
0206     else if (ret)
0207         dev_err(&dev->dev, "Xen PCI frontend error: %d!\n", ret);
0208 free:
0209     kfree(v);
0210     return ret;
0211 }
0212 
0213 static void xen_msi_compose_msg(struct pci_dev *pdev, unsigned int pirq,
0214         struct msi_msg *msg)
0215 {
0216     /*
0217      * We set vector == 0 to tell the hypervisor we don't care about
0218      * it, but we want a pirq setup instead.  We use the dest_id fields
0219      * to pass the pirq that we want.
0220      */
0221     memset(msg, 0, sizeof(*msg));
0222     msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
0223     msg->arch_addr_hi.destid_8_31 = pirq >> 8;
0224     msg->arch_addr_lo.destid_0_7 = pirq & 0xFF;
0225     msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW;
0226     msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
0227 }
0228 
0229 static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
0230 {
0231     int irq, pirq;
0232     struct msi_desc *msidesc;
0233     struct msi_msg msg;
0234 
0235     if (type == PCI_CAP_ID_MSI && nvec > 1)
0236         return 1;
0237 
0238     msi_for_each_desc(msidesc, &dev->dev, MSI_DESC_NOTASSOCIATED) {
0239         pirq = xen_allocate_pirq_msi(dev, msidesc);
0240         if (pirq < 0) {
0241             irq = -ENODEV;
0242             goto error;
0243         }
0244         xen_msi_compose_msg(dev, pirq, &msg);
0245         __pci_write_msi_msg(msidesc, &msg);
0246         dev_dbg(&dev->dev, "xen: msi bound to pirq=%d\n", pirq);
0247         irq = xen_bind_pirq_msi_to_irq(dev, msidesc, pirq,
0248                            (type == PCI_CAP_ID_MSI) ? nvec : 1,
0249                            (type == PCI_CAP_ID_MSIX) ?
0250                            "msi-x" : "msi",
0251                            DOMID_SELF);
0252         if (irq < 0)
0253             goto error;
0254         dev_dbg(&dev->dev,
0255             "xen: msi --> pirq=%d --> irq=%d\n", pirq, irq);
0256     }
0257     return 0;
0258 
0259 error:
0260     dev_err(&dev->dev, "Failed to create MSI%s! ret=%d!\n",
0261         type == PCI_CAP_ID_MSI ? "" : "-X", irq);
0262     return irq;
0263 }
0264 
0265 #ifdef CONFIG_XEN_PV_DOM0
0266 static bool __read_mostly pci_seg_supported = true;
0267 
0268 static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
0269 {
0270     int ret = 0;
0271     struct msi_desc *msidesc;
0272 
0273     msi_for_each_desc(msidesc, &dev->dev, MSI_DESC_NOTASSOCIATED) {
0274         struct physdev_map_pirq map_irq;
0275         domid_t domid;
0276 
0277         domid = ret = xen_find_device_domain_owner(dev);
0278         /* N.B. Casting int's -ENODEV to uint16_t results in 0xFFED,
0279          * hence check ret value for < 0. */
0280         if (ret < 0)
0281             domid = DOMID_SELF;
0282 
0283         memset(&map_irq, 0, sizeof(map_irq));
0284         map_irq.domid = domid;
0285         map_irq.type = MAP_PIRQ_TYPE_MSI_SEG;
0286         map_irq.index = -1;
0287         map_irq.pirq = -1;
0288         map_irq.bus = dev->bus->number |
0289                   (pci_domain_nr(dev->bus) << 16);
0290         map_irq.devfn = dev->devfn;
0291 
0292         if (type == PCI_CAP_ID_MSI && nvec > 1) {
0293             map_irq.type = MAP_PIRQ_TYPE_MULTI_MSI;
0294             map_irq.entry_nr = nvec;
0295         } else if (type == PCI_CAP_ID_MSIX) {
0296             int pos;
0297             unsigned long flags;
0298             u32 table_offset, bir;
0299 
0300             pos = dev->msix_cap;
0301             pci_read_config_dword(dev, pos + PCI_MSIX_TABLE,
0302                           &table_offset);
0303             bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
0304             flags = pci_resource_flags(dev, bir);
0305             if (!flags || (flags & IORESOURCE_UNSET))
0306                 return -EINVAL;
0307 
0308             map_irq.table_base = pci_resource_start(dev, bir);
0309             map_irq.entry_nr = msidesc->msi_index;
0310         }
0311 
0312         ret = -EINVAL;
0313         if (pci_seg_supported)
0314             ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
0315                             &map_irq);
0316         if (type == PCI_CAP_ID_MSI && nvec > 1 && ret) {
0317             /*
0318              * If MAP_PIRQ_TYPE_MULTI_MSI is not available
0319              * there's nothing else we can do in this case.
0320              * Just set ret > 0 so driver can retry with
0321              * single MSI.
0322              */
0323             ret = 1;
0324             goto out;
0325         }
0326         if (ret == -EINVAL && !pci_domain_nr(dev->bus)) {
0327             map_irq.type = MAP_PIRQ_TYPE_MSI;
0328             map_irq.index = -1;
0329             map_irq.pirq = -1;
0330             map_irq.bus = dev->bus->number;
0331             ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
0332                             &map_irq);
0333             if (ret != -EINVAL)
0334                 pci_seg_supported = false;
0335         }
0336         if (ret) {
0337             dev_warn(&dev->dev, "xen map irq failed %d for %d domain\n",
0338                  ret, domid);
0339             goto out;
0340         }
0341 
0342         ret = xen_bind_pirq_msi_to_irq(dev, msidesc, map_irq.pirq,
0343                                        (type == PCI_CAP_ID_MSI) ? nvec : 1,
0344                                        (type == PCI_CAP_ID_MSIX) ? "msi-x" : "msi",
0345                                        domid);
0346         if (ret < 0)
0347             goto out;
0348     }
0349     ret = 0;
0350 out:
0351     return ret;
0352 }
0353 
0354 bool xen_initdom_restore_msi(struct pci_dev *dev)
0355 {
0356     int ret = 0;
0357 
0358     if (!xen_initial_domain())
0359         return true;
0360 
0361     if (pci_seg_supported) {
0362         struct physdev_pci_device restore_ext;
0363 
0364         restore_ext.seg = pci_domain_nr(dev->bus);
0365         restore_ext.bus = dev->bus->number;
0366         restore_ext.devfn = dev->devfn;
0367         ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi_ext,
0368                     &restore_ext);
0369         if (ret == -ENOSYS)
0370             pci_seg_supported = false;
0371         WARN(ret && ret != -ENOSYS, "restore_msi_ext -> %d\n", ret);
0372     }
0373     if (!pci_seg_supported) {
0374         struct physdev_restore_msi restore;
0375 
0376         restore.bus = dev->bus->number;
0377         restore.devfn = dev->devfn;
0378         ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi, &restore);
0379         WARN(ret && ret != -ENOSYS, "restore_msi -> %d\n", ret);
0380     }
0381     return false;
0382 }
0383 #else /* CONFIG_XEN_PV_DOM0 */
0384 #define xen_initdom_setup_msi_irqs  NULL
0385 #endif /* !CONFIG_XEN_PV_DOM0 */
0386 
0387 static void xen_teardown_msi_irqs(struct pci_dev *dev)
0388 {
0389     struct msi_desc *msidesc;
0390     int i;
0391 
0392     msi_for_each_desc(msidesc, &dev->dev, MSI_DESC_ASSOCIATED) {
0393         for (i = 0; i < msidesc->nvec_used; i++)
0394             xen_destroy_irq(msidesc->irq + i);
0395     }
0396 }
0397 
0398 static void xen_pv_teardown_msi_irqs(struct pci_dev *dev)
0399 {
0400     if (dev->msix_enabled)
0401         xen_pci_frontend_disable_msix(dev);
0402     else
0403         xen_pci_frontend_disable_msi(dev);
0404 
0405     xen_teardown_msi_irqs(dev);
0406 }
0407 
0408 static int xen_msi_domain_alloc_irqs(struct irq_domain *domain,
0409                      struct device *dev,  int nvec)
0410 {
0411     int type;
0412 
0413     if (WARN_ON_ONCE(!dev_is_pci(dev)))
0414         return -EINVAL;
0415 
0416     type = to_pci_dev(dev)->msix_enabled ? PCI_CAP_ID_MSIX : PCI_CAP_ID_MSI;
0417 
0418     return xen_msi_ops.setup_msi_irqs(to_pci_dev(dev), nvec, type);
0419 }
0420 
0421 static void xen_msi_domain_free_irqs(struct irq_domain *domain,
0422                      struct device *dev)
0423 {
0424     if (WARN_ON_ONCE(!dev_is_pci(dev)))
0425         return;
0426 
0427     xen_msi_ops.teardown_msi_irqs(to_pci_dev(dev));
0428 }
0429 
0430 static struct msi_domain_ops xen_pci_msi_domain_ops = {
0431     .domain_alloc_irqs  = xen_msi_domain_alloc_irqs,
0432     .domain_free_irqs   = xen_msi_domain_free_irqs,
0433 };
0434 
0435 static struct msi_domain_info xen_pci_msi_domain_info = {
0436     .ops            = &xen_pci_msi_domain_ops,
0437 };
0438 
0439 /*
0440  * This irq domain is a blatant violation of the irq domain design, but
0441  * distangling XEN into real irq domains is not a job for mere mortals with
0442  * limited XENology. But it's the least dangerous way for a mere mortal to
0443  * get rid of the arch_*_msi_irqs() hackery in order to store the irq
0444  * domain pointer in struct device. This irq domain wrappery allows to do
0445  * that without breaking XEN terminally.
0446  */
0447 static __init struct irq_domain *xen_create_pci_msi_domain(void)
0448 {
0449     struct irq_domain *d = NULL;
0450     struct fwnode_handle *fn;
0451 
0452     fn = irq_domain_alloc_named_fwnode("XEN-MSI");
0453     if (fn)
0454         d = msi_create_irq_domain(fn, &xen_pci_msi_domain_info, NULL);
0455 
0456     /* FIXME: No idea how to survive if this fails */
0457     BUG_ON(!d);
0458 
0459     return d;
0460 }
0461 
0462 static __init void xen_setup_pci_msi(void)
0463 {
0464     if (xen_pv_domain()) {
0465         if (xen_initial_domain())
0466             xen_msi_ops.setup_msi_irqs = xen_initdom_setup_msi_irqs;
0467         else
0468             xen_msi_ops.setup_msi_irqs = xen_setup_msi_irqs;
0469         xen_msi_ops.teardown_msi_irqs = xen_pv_teardown_msi_irqs;
0470     } else if (xen_hvm_domain()) {
0471         xen_msi_ops.setup_msi_irqs = xen_hvm_setup_msi_irqs;
0472         xen_msi_ops.teardown_msi_irqs = xen_teardown_msi_irqs;
0473     } else {
0474         WARN_ON_ONCE(1);
0475         return;
0476     }
0477 
0478     /*
0479      * Override the PCI/MSI irq domain init function. No point
0480      * in allocating the native domain and never use it.
0481      */
0482     x86_init.irqs.create_pci_msi_domain = xen_create_pci_msi_domain;
0483     /*
0484      * With XEN PIRQ/Eventchannels in use PCI/MSI[-X] masking is solely
0485      * controlled by the hypervisor.
0486      */
0487     pci_msi_ignore_mask = 1;
0488 }
0489 
0490 #else /* CONFIG_PCI_MSI */
0491 static inline void xen_setup_pci_msi(void) { }
0492 #endif /* CONFIG_PCI_MSI */
0493 
0494 int __init pci_xen_init(void)
0495 {
0496     if (!xen_pv_domain() || xen_initial_domain())
0497         return -ENODEV;
0498 
0499     printk(KERN_INFO "PCI: setting up Xen PCI frontend stub\n");
0500 
0501     pcibios_set_cache_line_size();
0502 
0503     pcibios_enable_irq = xen_pcifront_enable_irq;
0504     pcibios_disable_irq = NULL;
0505 
0506     /* Keep ACPI out of the picture */
0507     acpi_noirq_set();
0508 
0509     xen_setup_pci_msi();
0510     return 0;
0511 }
0512 
0513 #ifdef CONFIG_PCI_MSI
0514 static void __init xen_hvm_msi_init(void)
0515 {
0516     if (!disable_apic) {
0517         /*
0518          * If hardware supports (x2)APIC virtualization (as indicated
0519          * by hypervisor's leaf 4) then we don't need to use pirqs/
0520          * event channels for MSI handling and instead use regular
0521          * APIC processing
0522          */
0523         uint32_t eax = cpuid_eax(xen_cpuid_base() + 4);
0524 
0525         if (((eax & XEN_HVM_CPUID_X2APIC_VIRT) && x2apic_mode) ||
0526             ((eax & XEN_HVM_CPUID_APIC_ACCESS_VIRT) && boot_cpu_has(X86_FEATURE_APIC)))
0527             return;
0528     }
0529     xen_setup_pci_msi();
0530 }
0531 #endif
0532 
0533 int __init pci_xen_hvm_init(void)
0534 {
0535     if (!xen_have_vector_callback || !xen_feature(XENFEAT_hvm_pirqs))
0536         return 0;
0537 
0538 #ifdef CONFIG_ACPI
0539     /*
0540      * We don't want to change the actual ACPI delivery model,
0541      * just how GSIs get registered.
0542      */
0543     __acpi_register_gsi = acpi_register_gsi_xen_hvm;
0544     __acpi_unregister_gsi = NULL;
0545 #endif
0546 
0547 #ifdef CONFIG_PCI_MSI
0548     /*
0549      * We need to wait until after x2apic is initialized
0550      * before we can set MSI IRQ ops.
0551      */
0552     x86_platform.apic_post_init = xen_hvm_msi_init;
0553 #endif
0554     return 0;
0555 }
0556 
0557 #ifdef CONFIG_XEN_PV_DOM0
0558 int __init pci_xen_initial_domain(void)
0559 {
0560     int irq;
0561 
0562     xen_setup_pci_msi();
0563     __acpi_register_gsi = acpi_register_gsi_xen;
0564     __acpi_unregister_gsi = NULL;
0565     /*
0566      * Pre-allocate the legacy IRQs.  Use NR_LEGACY_IRQS here
0567      * because we don't have a PIC and thus nr_legacy_irqs() is zero.
0568      */
0569     for (irq = 0; irq < NR_IRQS_LEGACY; irq++) {
0570         int trigger, polarity;
0571 
0572         if (acpi_get_override_irq(irq, &trigger, &polarity) == -1)
0573             continue;
0574 
0575         xen_register_pirq(irq,
0576             trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE,
0577             true /* Map GSI to PIRQ */);
0578     }
0579     if (0 == nr_ioapics) {
0580         for (irq = 0; irq < nr_legacy_irqs(); irq++)
0581             xen_bind_pirq_gsi_to_irq(irq, irq, 0, "xt-pic");
0582     }
0583     return 0;
0584 }
0585 #endif
0586
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