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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  Low-Level PCI Support for PC -- Routing of Interrupts
0004  *
0005  *  (c) 1999--2000 Martin Mares <mj@ucw.cz>
0006  */
0007 
0008 #include <linux/types.h>
0009 #include <linux/kernel.h>
0010 #include <linux/pci.h>
0011 #include <linux/init.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/dmi.h>
0014 #include <linux/io.h>
0015 #include <linux/smp.h>
0016 #include <linux/spinlock.h>
0017 #include <asm/io_apic.h>
0018 #include <linux/irq.h>
0019 #include <linux/acpi.h>
0020 
0021 #include <asm/i8259.h>
0022 #include <asm/pc-conf-reg.h>
0023 #include <asm/pci_x86.h>
0024 
0025 #define PIRQ_SIGNATURE  (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
0026 #define PIRQ_VERSION 0x0100
0027 
0028 #define IRT_SIGNATURE   (('$' << 0) + ('I' << 8) + ('R' << 16) + ('T' << 24))
0029 
0030 static int broken_hp_bios_irq9;
0031 static int acer_tm360_irqrouting;
0032 
0033 static struct irq_routing_table *pirq_table;
0034 
0035 static int pirq_enable_irq(struct pci_dev *dev);
0036 static void pirq_disable_irq(struct pci_dev *dev);
0037 
0038 /*
0039  * Never use: 0, 1, 2 (timer, keyboard, and cascade)
0040  * Avoid using: 13, 14 and 15 (FP error and IDE).
0041  * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
0042  */
0043 unsigned int pcibios_irq_mask = 0xfff8;
0044 
0045 static int pirq_penalty[16] = {
0046     1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
0047     0, 0, 0, 0, 1000, 100000, 100000, 100000
0048 };
0049 
0050 struct irq_router {
0051     char *name;
0052     u16 vendor, device;
0053     int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
0054     int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq,
0055         int new);
0056     int (*lvl)(struct pci_dev *router, struct pci_dev *dev, int pirq,
0057         int irq);
0058 };
0059 
0060 struct irq_router_handler {
0061     u16 vendor;
0062     int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
0063 };
0064 
0065 int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq;
0066 void (*pcibios_disable_irq)(struct pci_dev *dev) = pirq_disable_irq;
0067 
0068 /*
0069  *  Check passed address for the PCI IRQ Routing Table signature
0070  *  and perform checksum verification.
0071  */
0072 
0073 static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr,
0074                                  u8 *limit)
0075 {
0076     struct irq_routing_table *rt;
0077     int i;
0078     u8 sum;
0079 
0080     rt = (struct irq_routing_table *)addr;
0081     if (rt->signature != PIRQ_SIGNATURE ||
0082         rt->version != PIRQ_VERSION ||
0083         rt->size % 16 ||
0084         rt->size < sizeof(struct irq_routing_table) ||
0085         (limit && rt->size > limit - addr))
0086         return NULL;
0087     sum = 0;
0088     for (i = 0; i < rt->size; i++)
0089         sum += addr[i];
0090     if (!sum) {
0091         DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%lx\n",
0092             __pa(rt));
0093         return rt;
0094     }
0095     return NULL;
0096 }
0097 
0098 /*
0099  * Handle the $IRT PCI IRQ Routing Table format used by AMI for its BCP
0100  * (BIOS Configuration Program) external tool meant for tweaking BIOS
0101  * structures without the need to rebuild it from sources.  The $IRT
0102  * format has been invented by AMI before Microsoft has come up with its
0103  * $PIR format and a $IRT table is therefore there in some systems that
0104  * lack a $PIR table.
0105  *
0106  * It uses the same PCI BIOS 2.1 format for interrupt routing entries
0107  * themselves but has a different simpler header prepended instead,
0108  * occupying 8 bytes, where a `$IRT' signature is followed by one byte
0109  * specifying the total number of interrupt routing entries allocated in
0110  * the table, then one byte specifying the actual number of entries used
0111  * (which the BCP tool can take advantage of when modifying the table),
0112  * and finally a 16-bit word giving the IRQs devoted exclusively to PCI.
0113  * Unlike with the $PIR table there is no alignment guarantee.
0114  *
0115  * Given the similarity of the two formats the $IRT one is trivial to
0116  * convert to the $PIR one, which we do here, except that obviously we
0117  * have no information as to the router device to use, but we can handle
0118  * it by matching PCI device IDs actually seen on the bus against ones
0119  * that our individual routers recognise.
0120  *
0121  * Reportedly there is another $IRT table format where a 16-bit word
0122  * follows the header instead that points to interrupt routing entries
0123  * in a $PIR table provided elsewhere.  In that case this code will not
0124  * be reached though as the $PIR table will have been chosen instead.
0125  */
0126 static inline struct irq_routing_table *pirq_convert_irt_table(u8 *addr,
0127                                    u8 *limit)
0128 {
0129     struct irt_routing_table *ir;
0130     struct irq_routing_table *rt;
0131     u16 size;
0132     u8 sum;
0133     int i;
0134 
0135     ir = (struct irt_routing_table *)addr;
0136     if (ir->signature != IRT_SIGNATURE || !ir->used || ir->size < ir->used)
0137         return NULL;
0138 
0139     size = sizeof(*ir) + ir->used * sizeof(ir->slots[0]);
0140     if (size > limit - addr)
0141         return NULL;
0142 
0143     DBG(KERN_DEBUG "PCI: $IRT Interrupt Routing Table found at 0x%lx\n",
0144         __pa(ir));
0145 
0146     size = sizeof(*rt) + ir->used * sizeof(rt->slots[0]);
0147     rt = kzalloc(size, GFP_KERNEL);
0148     if (!rt)
0149         return NULL;
0150 
0151     rt->signature = PIRQ_SIGNATURE;
0152     rt->version = PIRQ_VERSION;
0153     rt->size = size;
0154     rt->exclusive_irqs = ir->exclusive_irqs;
0155     for (i = 0; i < ir->used; i++)
0156         rt->slots[i] = ir->slots[i];
0157 
0158     addr = (u8 *)rt;
0159     sum = 0;
0160     for (i = 0; i < size; i++)
0161         sum += addr[i];
0162     rt->checksum = -sum;
0163 
0164     return rt;
0165 }
0166 
0167 /*
0168  *  Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
0169  */
0170 
0171 static struct irq_routing_table * __init pirq_find_routing_table(void)
0172 {
0173     u8 * const bios_start = (u8 *)__va(0xf0000);
0174     u8 * const bios_end = (u8 *)__va(0x100000);
0175     u8 *addr;
0176     struct irq_routing_table *rt;
0177 
0178     if (pirq_table_addr) {
0179         rt = pirq_check_routing_table((u8 *)__va(pirq_table_addr),
0180                           NULL);
0181         if (rt)
0182             return rt;
0183         printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n");
0184     }
0185     for (addr = bios_start;
0186          addr < bios_end - sizeof(struct irq_routing_table);
0187          addr += 16) {
0188         rt = pirq_check_routing_table(addr, bios_end);
0189         if (rt)
0190             return rt;
0191     }
0192     for (addr = bios_start;
0193          addr < bios_end - sizeof(struct irt_routing_table);
0194          addr++) {
0195         rt = pirq_convert_irt_table(addr, bios_end);
0196         if (rt)
0197             return rt;
0198     }
0199     return NULL;
0200 }
0201 
0202 /*
0203  *  If we have a IRQ routing table, use it to search for peer host
0204  *  bridges.  It's a gross hack, but since there are no other known
0205  *  ways how to get a list of buses, we have to go this way.
0206  */
0207 
0208 static void __init pirq_peer_trick(void)
0209 {
0210     struct irq_routing_table *rt = pirq_table;
0211     u8 busmap[256];
0212     int i;
0213     struct irq_info *e;
0214 
0215     memset(busmap, 0, sizeof(busmap));
0216     for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
0217         e = &rt->slots[i];
0218 #ifdef DEBUG
0219         {
0220             int j;
0221             DBG(KERN_DEBUG "%02x:%02x.%x slot=%02x",
0222                 e->bus, e->devfn / 8, e->devfn % 8, e->slot);
0223             for (j = 0; j < 4; j++)
0224                 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
0225             DBG("\n");
0226         }
0227 #endif
0228         busmap[e->bus] = 1;
0229     }
0230     for (i = 1; i < 256; i++) {
0231         if (!busmap[i] || pci_find_bus(0, i))
0232             continue;
0233         pcibios_scan_root(i);
0234     }
0235     pcibios_last_bus = -1;
0236 }
0237 
0238 /*
0239  *  Code for querying and setting of IRQ routes on various interrupt routers.
0240  *  PIC Edge/Level Control Registers (ELCR) 0x4d0 & 0x4d1.
0241  */
0242 
0243 void elcr_set_level_irq(unsigned int irq)
0244 {
0245     unsigned char mask = 1 << (irq & 7);
0246     unsigned int port = PIC_ELCR1 + (irq >> 3);
0247     unsigned char val;
0248     static u16 elcr_irq_mask;
0249 
0250     if (irq >= 16 || (1 << irq) & elcr_irq_mask)
0251         return;
0252 
0253     elcr_irq_mask |= (1 << irq);
0254     printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq);
0255     val = inb(port);
0256     if (!(val & mask)) {
0257         DBG(KERN_DEBUG " -> edge");
0258         outb(val | mask, port);
0259     }
0260 }
0261 
0262 /*
0263  *  PIRQ routing for the M1487 ISA Bus Controller (IBC) ASIC used
0264  *  with the ALi FinALi 486 chipset.  The IBC is not decoded in the
0265  *  PCI configuration space, so we identify it by the accompanying
0266  *  M1489 Cache-Memory PCI Controller (CMP) ASIC.
0267  *
0268  *  There are four 4-bit mappings provided, spread across two PCI
0269  *  INTx Routing Table Mapping Registers, available in the port I/O
0270  *  space accessible indirectly via the index/data register pair at
0271  *  0x22/0x23, located at indices 0x42 and 0x43 for the INT1/INT2
0272  *  and INT3/INT4 lines respectively.  The INT1/INT3 and INT2/INT4
0273  *  lines are mapped in the low and the high 4-bit nibble of the
0274  *  corresponding register as follows:
0275  *
0276  *  0000 : Disabled
0277  *  0001 : IRQ9
0278  *  0010 : IRQ3
0279  *  0011 : IRQ10
0280  *  0100 : IRQ4
0281  *  0101 : IRQ5
0282  *  0110 : IRQ7
0283  *  0111 : IRQ6
0284  *  1000 : Reserved
0285  *  1001 : IRQ11
0286  *  1010 : Reserved
0287  *  1011 : IRQ12
0288  *  1100 : Reserved
0289  *  1101 : IRQ14
0290  *  1110 : Reserved
0291  *  1111 : IRQ15
0292  *
0293  *  In addition to the usual ELCR register pair there is a separate
0294  *  PCI INTx Sensitivity Register at index 0x44 in the same port I/O
0295  *  space, whose bits 3:0 select the trigger mode for INT[4:1] lines
0296  *  respectively.  Any bit set to 1 causes interrupts coming on the
0297  *  corresponding line to be passed to ISA as edge-triggered and
0298  *  otherwise they are passed as level-triggered.  Manufacturer's
0299  *  documentation says this register has to be set consistently with
0300  *  the relevant ELCR register.
0301  *
0302  *  Accesses to the port I/O space concerned here need to be unlocked
0303  *  by writing the value of 0xc5 to the Lock Register at index 0x03
0304  *  beforehand.  Any other value written to said register prevents
0305  *  further accesses from reaching the register file, except for the
0306  *  Lock Register being written with 0xc5 again.
0307  *
0308  *  References:
0309  *
0310  *  "M1489/M1487: 486 PCI Chip Set", Version 1.2, Acer Laboratories
0311  *  Inc., July 1997
0312  */
0313 
0314 #define PC_CONF_FINALI_LOCK     0x03u
0315 #define PC_CONF_FINALI_PCI_INTX_RT1 0x42u
0316 #define PC_CONF_FINALI_PCI_INTX_RT2 0x43u
0317 #define PC_CONF_FINALI_PCI_INTX_SENS    0x44u
0318 
0319 #define PC_CONF_FINALI_LOCK_KEY     0xc5u
0320 
0321 static u8 read_pc_conf_nybble(u8 base, u8 index)
0322 {
0323     u8 reg = base + (index >> 1);
0324     u8 x;
0325 
0326     x = pc_conf_get(reg);
0327     return index & 1 ? x >> 4 : x & 0xf;
0328 }
0329 
0330 static void write_pc_conf_nybble(u8 base, u8 index, u8 val)
0331 {
0332     u8 reg = base + (index >> 1);
0333     u8 x;
0334 
0335     x = pc_conf_get(reg);
0336     x = index & 1 ? (x & 0x0f) | (val << 4) : (x & 0xf0) | val;
0337     pc_conf_set(reg, x);
0338 }
0339 
0340 /*
0341  * FinALi pirq rules are as follows:
0342  *
0343  * - bit 0 selects between INTx Routing Table Mapping Registers,
0344  *
0345  * - bit 3 selects the nibble within the INTx Routing Table Mapping Register,
0346  *
0347  * - bits 7:4 map to bits 3:0 of the PCI INTx Sensitivity Register.
0348  */
0349 static int pirq_finali_get(struct pci_dev *router, struct pci_dev *dev,
0350                int pirq)
0351 {
0352     static const u8 irqmap[16] = {
0353         0, 9, 3, 10, 4, 5, 7, 6, 0, 11, 0, 12, 0, 14, 0, 15
0354     };
0355     unsigned long flags;
0356     u8 index;
0357     u8 x;
0358 
0359     index = (pirq & 1) << 1 | (pirq & 8) >> 3;
0360     raw_spin_lock_irqsave(&pc_conf_lock, flags);
0361     pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY);
0362     x = irqmap[read_pc_conf_nybble(PC_CONF_FINALI_PCI_INTX_RT1, index)];
0363     pc_conf_set(PC_CONF_FINALI_LOCK, 0);
0364     raw_spin_unlock_irqrestore(&pc_conf_lock, flags);
0365     return x;
0366 }
0367 
0368 static int pirq_finali_set(struct pci_dev *router, struct pci_dev *dev,
0369                int pirq, int irq)
0370 {
0371     static const u8 irqmap[16] = {
0372         0, 0, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15
0373     };
0374     u8 val = irqmap[irq];
0375     unsigned long flags;
0376     u8 index;
0377 
0378     if (!val)
0379         return 0;
0380 
0381     index = (pirq & 1) << 1 | (pirq & 8) >> 3;
0382     raw_spin_lock_irqsave(&pc_conf_lock, flags);
0383     pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY);
0384     write_pc_conf_nybble(PC_CONF_FINALI_PCI_INTX_RT1, index, val);
0385     pc_conf_set(PC_CONF_FINALI_LOCK, 0);
0386     raw_spin_unlock_irqrestore(&pc_conf_lock, flags);
0387     return 1;
0388 }
0389 
0390 static int pirq_finali_lvl(struct pci_dev *router, struct pci_dev *dev,
0391                int pirq, int irq)
0392 {
0393     u8 mask = ~((pirq & 0xf0u) >> 4);
0394     unsigned long flags;
0395     u8 trig;
0396 
0397     elcr_set_level_irq(irq);
0398     raw_spin_lock_irqsave(&pc_conf_lock, flags);
0399     pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY);
0400     trig = pc_conf_get(PC_CONF_FINALI_PCI_INTX_SENS);
0401     trig &= mask;
0402     pc_conf_set(PC_CONF_FINALI_PCI_INTX_SENS, trig);
0403     pc_conf_set(PC_CONF_FINALI_LOCK, 0);
0404     raw_spin_unlock_irqrestore(&pc_conf_lock, flags);
0405     return 1;
0406 }
0407 
0408 /*
0409  * Common IRQ routing practice: nibbles in config space,
0410  * offset by some magic constant.
0411  */
0412 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
0413 {
0414     u8 x;
0415     unsigned reg = offset + (nr >> 1);
0416 
0417     pci_read_config_byte(router, reg, &x);
0418     return (nr & 1) ? (x >> 4) : (x & 0xf);
0419 }
0420 
0421 static void write_config_nybble(struct pci_dev *router, unsigned offset,
0422     unsigned nr, unsigned int val)
0423 {
0424     u8 x;
0425     unsigned reg = offset + (nr >> 1);
0426 
0427     pci_read_config_byte(router, reg, &x);
0428     x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
0429     pci_write_config_byte(router, reg, x);
0430 }
0431 
0432 /*
0433  * ALI pirq entries are damn ugly, and completely undocumented.
0434  * This has been figured out from pirq tables, and it's not a pretty
0435  * picture.
0436  */
0437 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
0438 {
0439     static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
0440 
0441     WARN_ON_ONCE(pirq > 16);
0442     return irqmap[read_config_nybble(router, 0x48, pirq-1)];
0443 }
0444 
0445 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
0446 {
0447     static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
0448     unsigned int val = irqmap[irq];
0449 
0450     WARN_ON_ONCE(pirq > 16);
0451     if (val) {
0452         write_config_nybble(router, 0x48, pirq-1, val);
0453         return 1;
0454     }
0455     return 0;
0456 }
0457 
0458 /*
0459  *  PIRQ routing for the 82374EB/82374SB EISA System Component (ESC)
0460  *  ASIC used with the Intel 82420 and 82430 PCIsets.  The ESC is not
0461  *  decoded in the PCI configuration space, so we identify it by the
0462  *  accompanying 82375EB/82375SB PCI-EISA Bridge (PCEB) ASIC.
0463  *
0464  *  There are four PIRQ Route Control registers, available in the
0465  *  port I/O space accessible indirectly via the index/data register
0466  *  pair at 0x22/0x23, located at indices 0x60/0x61/0x62/0x63 for the
0467  *  PIRQ0/1/2/3# lines respectively.  The semantics is the same as
0468  *  with the PIIX router.
0469  *
0470  *  Accesses to the port I/O space concerned here need to be unlocked
0471  *  by writing the value of 0x0f to the ESC ID Register at index 0x02
0472  *  beforehand.  Any other value written to said register prevents
0473  *  further accesses from reaching the register file, except for the
0474  *  ESC ID Register being written with 0x0f again.
0475  *
0476  *  References:
0477  *
0478  *  "82374EB/82374SB EISA System Component (ESC)", Intel Corporation,
0479  *  Order Number: 290476-004, March 1996
0480  *
0481  *  "82375EB/82375SB PCI-EISA Bridge (PCEB)", Intel Corporation, Order
0482  *  Number: 290477-004, March 1996
0483  */
0484 
0485 #define PC_CONF_I82374_ESC_ID           0x02u
0486 #define PC_CONF_I82374_PIRQ_ROUTE_CONTROL   0x60u
0487 
0488 #define PC_CONF_I82374_ESC_ID_KEY       0x0fu
0489 
0490 static int pirq_esc_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
0491 {
0492     unsigned long flags;
0493     int reg;
0494     u8 x;
0495 
0496     reg = pirq;
0497     if (reg >= 1 && reg <= 4)
0498         reg += PC_CONF_I82374_PIRQ_ROUTE_CONTROL - 1;
0499 
0500     raw_spin_lock_irqsave(&pc_conf_lock, flags);
0501     pc_conf_set(PC_CONF_I82374_ESC_ID, PC_CONF_I82374_ESC_ID_KEY);
0502     x = pc_conf_get(reg);
0503     pc_conf_set(PC_CONF_I82374_ESC_ID, 0);
0504     raw_spin_unlock_irqrestore(&pc_conf_lock, flags);
0505     return (x < 16) ? x : 0;
0506 }
0507 
0508 static int pirq_esc_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
0509                int irq)
0510 {
0511     unsigned long flags;
0512     int reg;
0513 
0514     reg = pirq;
0515     if (reg >= 1 && reg <= 4)
0516         reg += PC_CONF_I82374_PIRQ_ROUTE_CONTROL - 1;
0517 
0518     raw_spin_lock_irqsave(&pc_conf_lock, flags);
0519     pc_conf_set(PC_CONF_I82374_ESC_ID, PC_CONF_I82374_ESC_ID_KEY);
0520     pc_conf_set(reg, irq);
0521     pc_conf_set(PC_CONF_I82374_ESC_ID, 0);
0522     raw_spin_unlock_irqrestore(&pc_conf_lock, flags);
0523     return 1;
0524 }
0525 
0526 /*
0527  * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
0528  * just a pointer to the config space.
0529  */
0530 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
0531 {
0532     u8 x;
0533 
0534     pci_read_config_byte(router, pirq, &x);
0535     return (x < 16) ? x : 0;
0536 }
0537 
0538 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
0539 {
0540     pci_write_config_byte(router, pirq, irq);
0541     return 1;
0542 }
0543 
0544 /*
0545  *  PIRQ routing for the 82426EX ISA Bridge (IB) ASIC used with the
0546  *  Intel 82420EX PCIset.
0547  *
0548  *  There are only two PIRQ Route Control registers, available in the
0549  *  combined 82425EX/82426EX PCI configuration space, at 0x66 and 0x67
0550  *  for the PIRQ0# and PIRQ1# lines respectively.  The semantics is
0551  *  the same as with the PIIX router.
0552  *
0553  *  References:
0554  *
0555  *  "82420EX PCIset Data Sheet, 82425EX PCI System Controller (PSC)
0556  *  and 82426EX ISA Bridge (IB)", Intel Corporation, Order Number:
0557  *  290488-004, December 1995
0558  */
0559 
0560 #define PCI_I82426EX_PIRQ_ROUTE_CONTROL 0x66u
0561 
0562 static int pirq_ib_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
0563 {
0564     int reg;
0565     u8 x;
0566 
0567     reg = pirq;
0568     if (reg >= 1 && reg <= 2)
0569         reg += PCI_I82426EX_PIRQ_ROUTE_CONTROL - 1;
0570 
0571     pci_read_config_byte(router, reg, &x);
0572     return (x < 16) ? x : 0;
0573 }
0574 
0575 static int pirq_ib_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
0576                int irq)
0577 {
0578     int reg;
0579 
0580     reg = pirq;
0581     if (reg >= 1 && reg <= 2)
0582         reg += PCI_I82426EX_PIRQ_ROUTE_CONTROL - 1;
0583 
0584     pci_write_config_byte(router, reg, irq);
0585     return 1;
0586 }
0587 
0588 /*
0589  * The VIA pirq rules are nibble-based, like ALI,
0590  * but without the ugly irq number munging.
0591  * However, PIRQD is in the upper instead of lower 4 bits.
0592  */
0593 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
0594 {
0595     return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
0596 }
0597 
0598 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
0599 {
0600     write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
0601     return 1;
0602 }
0603 
0604 /*
0605  * The VIA pirq rules are nibble-based, like ALI,
0606  * but without the ugly irq number munging.
0607  * However, for 82C586, nibble map is different .
0608  */
0609 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
0610 {
0611     static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
0612 
0613     WARN_ON_ONCE(pirq > 5);
0614     return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
0615 }
0616 
0617 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
0618 {
0619     static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
0620 
0621     WARN_ON_ONCE(pirq > 5);
0622     write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
0623     return 1;
0624 }
0625 
0626 /*
0627  * ITE 8330G pirq rules are nibble-based
0628  * FIXME: pirqmap may be { 1, 0, 3, 2 },
0629  *    2+3 are both mapped to irq 9 on my system
0630  */
0631 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
0632 {
0633     static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
0634 
0635     WARN_ON_ONCE(pirq > 4);
0636     return read_config_nybble(router, 0x43, pirqmap[pirq-1]);
0637 }
0638 
0639 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
0640 {
0641     static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
0642 
0643     WARN_ON_ONCE(pirq > 4);
0644     write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
0645     return 1;
0646 }
0647 
0648 /*
0649  * OPTI: high four bits are nibble pointer..
0650  * I wonder what the low bits do?
0651  */
0652 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
0653 {
0654     return read_config_nybble(router, 0xb8, pirq >> 4);
0655 }
0656 
0657 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
0658 {
0659     write_config_nybble(router, 0xb8, pirq >> 4, irq);
0660     return 1;
0661 }
0662 
0663 /*
0664  * Cyrix: nibble offset 0x5C
0665  * 0x5C bits 7:4 is INTB bits 3:0 is INTA
0666  * 0x5D bits 7:4 is INTD bits 3:0 is INTC
0667  */
0668 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
0669 {
0670     return read_config_nybble(router, 0x5C, (pirq-1)^1);
0671 }
0672 
0673 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
0674 {
0675     write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
0676     return 1;
0677 }
0678 
0679 
0680 /*
0681  *  PIRQ routing for the SiS85C497 AT Bus Controller & Megacell (ATM)
0682  *  ISA bridge used with the SiS 85C496/497 486 Green PC VESA/ISA/PCI
0683  *  Chipset.
0684  *
0685  *  There are four PCI INTx#-to-IRQ Link registers provided in the
0686  *  SiS85C497 part of the peculiar combined 85C496/497 configuration
0687  *  space decoded by the SiS85C496 PCI & CPU Memory Controller (PCM)
0688  *  host bridge, at 0xc0/0xc1/0xc2/0xc3 respectively for the PCI INT
0689  *  A/B/C/D lines.  Bit 7 enables the respective link if set and bits
0690  *  3:0 select the 8259A IRQ line as follows:
0691  *
0692  *  0000 : Reserved
0693  *  0001 : Reserved
0694  *  0010 : Reserved
0695  *  0011 : IRQ3
0696  *  0100 : IRQ4
0697  *  0101 : IRQ5
0698  *  0110 : IRQ6
0699  *  0111 : IRQ7
0700  *  1000 : Reserved
0701  *  1001 : IRQ9
0702  *  1010 : IRQ10
0703  *  1011 : IRQ11
0704  *  1100 : IRQ12
0705  *  1101 : Reserved
0706  *  1110 : IRQ14
0707  *  1111 : IRQ15
0708  *
0709  *  We avoid using a reserved value for disabled links, hence the
0710  *  choice of IRQ15 for that case.
0711  *
0712  *  References:
0713  *
0714  *  "486 Green PC VESA/ISA/PCI Chipset, SiS 85C496/497", Rev 3.0,
0715  *  Silicon Integrated Systems Corp., July 1995
0716  */
0717 
0718 #define PCI_SIS497_INTA_TO_IRQ_LINK 0xc0u
0719 
0720 #define PIRQ_SIS497_IRQ_MASK        0x0fu
0721 #define PIRQ_SIS497_IRQ_ENABLE      0x80u
0722 
0723 static int pirq_sis497_get(struct pci_dev *router, struct pci_dev *dev,
0724                int pirq)
0725 {
0726     int reg;
0727     u8 x;
0728 
0729     reg = pirq;
0730     if (reg >= 1 && reg <= 4)
0731         reg += PCI_SIS497_INTA_TO_IRQ_LINK - 1;
0732 
0733     pci_read_config_byte(router, reg, &x);
0734     return (x & PIRQ_SIS497_IRQ_ENABLE) ? (x & PIRQ_SIS497_IRQ_MASK) : 0;
0735 }
0736 
0737 static int pirq_sis497_set(struct pci_dev *router, struct pci_dev *dev,
0738                int pirq, int irq)
0739 {
0740     int reg;
0741     u8 x;
0742 
0743     reg = pirq;
0744     if (reg >= 1 && reg <= 4)
0745         reg += PCI_SIS497_INTA_TO_IRQ_LINK - 1;
0746 
0747     pci_read_config_byte(router, reg, &x);
0748     x &= ~(PIRQ_SIS497_IRQ_MASK | PIRQ_SIS497_IRQ_ENABLE);
0749     x |= irq ? (PIRQ_SIS497_IRQ_ENABLE | irq) : PIRQ_SIS497_IRQ_MASK;
0750     pci_write_config_byte(router, reg, x);
0751     return 1;
0752 }
0753 
0754 /*
0755  *  PIRQ routing for SiS 85C503 router used in several SiS chipsets.
0756  *  We have to deal with the following issues here:
0757  *  - vendors have different ideas about the meaning of link values
0758  *  - some onboard devices (integrated in the chipset) have special
0759  *    links and are thus routed differently (i.e. not via PCI INTA-INTD)
0760  *  - different revision of the router have a different layout for
0761  *    the routing registers, particularly for the onchip devices
0762  *
0763  *  For all routing registers the common thing is we have one byte
0764  *  per routeable link which is defined as:
0765  *       bit 7      IRQ mapping enabled (0) or disabled (1)
0766  *       bits [6:4] reserved (sometimes used for onchip devices)
0767  *       bits [3:0] IRQ to map to
0768  *           allowed: 3-7, 9-12, 14-15
0769  *           reserved: 0, 1, 2, 8, 13
0770  *
0771  *  The config-space registers located at 0x41/0x42/0x43/0x44 are
0772  *  always used to route the normal PCI INT A/B/C/D respectively.
0773  *  Apparently there are systems implementing PCI routing table using
0774  *  link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
0775  *  We try our best to handle both link mappings.
0776  *
0777  *  Currently (2003-05-21) it appears most SiS chipsets follow the
0778  *  definition of routing registers from the SiS-5595 southbridge.
0779  *  According to the SiS 5595 datasheets the revision id's of the
0780  *  router (ISA-bridge) should be 0x01 or 0xb0.
0781  *
0782  *  Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
0783  *  Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
0784  *  They seem to work with the current routing code. However there is
0785  *  some concern because of the two USB-OHCI HCs (original SiS 5595
0786  *  had only one). YMMV.
0787  *
0788  *  Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
0789  *
0790  *  0x61:   IDEIRQ:
0791  *      bits [6:5] must be written 01
0792  *      bit 4 channel-select primary (0), secondary (1)
0793  *
0794  *  0x62:   USBIRQ:
0795  *      bit 6 OHCI function disabled (0), enabled (1)
0796  *
0797  *  0x6a:   ACPI/SCI IRQ: bits 4-6 reserved
0798  *
0799  *  0x7e:   Data Acq. Module IRQ - bits 4-6 reserved
0800  *
0801  *  We support USBIRQ (in addition to INTA-INTD) and keep the
0802  *  IDE, ACPI and DAQ routing untouched as set by the BIOS.
0803  *
0804  *  Currently the only reported exception is the new SiS 65x chipset
0805  *  which includes the SiS 69x southbridge. Here we have the 85C503
0806  *  router revision 0x04 and there are changes in the register layout
0807  *  mostly related to the different USB HCs with USB 2.0 support.
0808  *
0809  *  Onchip routing for router rev-id 0x04 (try-and-error observation)
0810  *
0811  *  0x60/0x61/0x62/0x63:    1xEHCI and 3xOHCI (companion) USB-HCs
0812  *              bit 6-4 are probably unused, not like 5595
0813  */
0814 
0815 #define PIRQ_SIS503_IRQ_MASK    0x0f
0816 #define PIRQ_SIS503_IRQ_DISABLE 0x80
0817 #define PIRQ_SIS503_USB_ENABLE  0x40
0818 
0819 static int pirq_sis503_get(struct pci_dev *router, struct pci_dev *dev,
0820                int pirq)
0821 {
0822     u8 x;
0823     int reg;
0824 
0825     reg = pirq;
0826     if (reg >= 0x01 && reg <= 0x04)
0827         reg += 0x40;
0828     pci_read_config_byte(router, reg, &x);
0829     return (x & PIRQ_SIS503_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS503_IRQ_MASK);
0830 }
0831 
0832 static int pirq_sis503_set(struct pci_dev *router, struct pci_dev *dev,
0833                int pirq, int irq)
0834 {
0835     u8 x;
0836     int reg;
0837 
0838     reg = pirq;
0839     if (reg >= 0x01 && reg <= 0x04)
0840         reg += 0x40;
0841     pci_read_config_byte(router, reg, &x);
0842     x &= ~(PIRQ_SIS503_IRQ_MASK | PIRQ_SIS503_IRQ_DISABLE);
0843     x |= irq ? irq : PIRQ_SIS503_IRQ_DISABLE;
0844     pci_write_config_byte(router, reg, x);
0845     return 1;
0846 }
0847 
0848 
0849 /*
0850  * VLSI: nibble offset 0x74 - educated guess due to routing table and
0851  *       config space of VLSI 82C534 PCI-bridge/router (1004:0102)
0852  *       Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
0853  *       devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
0854  *       for the busbridge to the docking station.
0855  */
0856 
0857 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
0858 {
0859     WARN_ON_ONCE(pirq >= 9);
0860     if (pirq > 8) {
0861         dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
0862         return 0;
0863     }
0864     return read_config_nybble(router, 0x74, pirq-1);
0865 }
0866 
0867 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
0868 {
0869     WARN_ON_ONCE(pirq >= 9);
0870     if (pirq > 8) {
0871         dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
0872         return 0;
0873     }
0874     write_config_nybble(router, 0x74, pirq-1, irq);
0875     return 1;
0876 }
0877 
0878 /*
0879  * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
0880  * and Redirect I/O registers (0x0c00 and 0x0c01).  The Index register
0881  * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a.  The Redirect
0882  * register is a straight binary coding of desired PIC IRQ (low nibble).
0883  *
0884  * The 'link' value in the PIRQ table is already in the correct format
0885  * for the Index register.  There are some special index values:
0886  * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
0887  * and 0x03 for SMBus.
0888  */
0889 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
0890 {
0891     outb(pirq, 0xc00);
0892     return inb(0xc01) & 0xf;
0893 }
0894 
0895 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev,
0896     int pirq, int irq)
0897 {
0898     outb(pirq, 0xc00);
0899     outb(irq, 0xc01);
0900     return 1;
0901 }
0902 
0903 /* Support for AMD756 PCI IRQ Routing
0904  * Jhon H. Caicedo <jhcaiced@osso.org.co>
0905  * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
0906  * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
0907  * The AMD756 pirq rules are nibble-based
0908  * offset 0x56 0-3 PIRQA  4-7  PIRQB
0909  * offset 0x57 0-3 PIRQC  4-7  PIRQD
0910  */
0911 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
0912 {
0913     u8 irq;
0914     irq = 0;
0915     if (pirq <= 4)
0916         irq = read_config_nybble(router, 0x56, pirq - 1);
0917     dev_info(&dev->dev,
0918          "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n",
0919          dev->vendor, dev->device, pirq, irq);
0920     return irq;
0921 }
0922 
0923 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
0924 {
0925     dev_info(&dev->dev,
0926          "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n",
0927          dev->vendor, dev->device, pirq, irq);
0928     if (pirq <= 4)
0929         write_config_nybble(router, 0x56, pirq - 1, irq);
0930     return 1;
0931 }
0932 
0933 /*
0934  * PicoPower PT86C523
0935  */
0936 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
0937 {
0938     outb(0x10 + ((pirq - 1) >> 1), 0x24);
0939     return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf);
0940 }
0941 
0942 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
0943             int irq)
0944 {
0945     unsigned int x;
0946     outb(0x10 + ((pirq - 1) >> 1), 0x24);
0947     x = inb(0x26);
0948     x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq));
0949     outb(x, 0x26);
0950     return 1;
0951 }
0952 
0953 #ifdef CONFIG_PCI_BIOS
0954 
0955 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
0956 {
0957     struct pci_dev *bridge;
0958     int pin = pci_get_interrupt_pin(dev, &bridge);
0959     return pcibios_set_irq_routing(bridge, pin - 1, irq);
0960 }
0961 
0962 #endif
0963 
0964 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
0965 {
0966     static struct pci_device_id __initdata pirq_440gx[] = {
0967         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
0968         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
0969         { },
0970     };
0971 
0972     /* 440GX has a proprietary PIRQ router -- don't use it */
0973     if (pci_dev_present(pirq_440gx))
0974         return 0;
0975 
0976     switch (device) {
0977     case PCI_DEVICE_ID_INTEL_82375:
0978         r->name = "PCEB/ESC";
0979         r->get = pirq_esc_get;
0980         r->set = pirq_esc_set;
0981         return 1;
0982     case PCI_DEVICE_ID_INTEL_82371FB_0:
0983     case PCI_DEVICE_ID_INTEL_82371SB_0:
0984     case PCI_DEVICE_ID_INTEL_82371AB_0:
0985     case PCI_DEVICE_ID_INTEL_82371MX:
0986     case PCI_DEVICE_ID_INTEL_82443MX_0:
0987     case PCI_DEVICE_ID_INTEL_82801AA_0:
0988     case PCI_DEVICE_ID_INTEL_82801AB_0:
0989     case PCI_DEVICE_ID_INTEL_82801BA_0:
0990     case PCI_DEVICE_ID_INTEL_82801BA_10:
0991     case PCI_DEVICE_ID_INTEL_82801CA_0:
0992     case PCI_DEVICE_ID_INTEL_82801CA_12:
0993     case PCI_DEVICE_ID_INTEL_82801DB_0:
0994     case PCI_DEVICE_ID_INTEL_82801E_0:
0995     case PCI_DEVICE_ID_INTEL_82801EB_0:
0996     case PCI_DEVICE_ID_INTEL_ESB_1:
0997     case PCI_DEVICE_ID_INTEL_ICH6_0:
0998     case PCI_DEVICE_ID_INTEL_ICH6_1:
0999     case PCI_DEVICE_ID_INTEL_ICH7_0:
1000     case PCI_DEVICE_ID_INTEL_ICH7_1:
1001     case PCI_DEVICE_ID_INTEL_ICH7_30:
1002     case PCI_DEVICE_ID_INTEL_ICH7_31:
1003     case PCI_DEVICE_ID_INTEL_TGP_LPC:
1004     case PCI_DEVICE_ID_INTEL_ESB2_0:
1005     case PCI_DEVICE_ID_INTEL_ICH8_0:
1006     case PCI_DEVICE_ID_INTEL_ICH8_1:
1007     case PCI_DEVICE_ID_INTEL_ICH8_2:
1008     case PCI_DEVICE_ID_INTEL_ICH8_3:
1009     case PCI_DEVICE_ID_INTEL_ICH8_4:
1010     case PCI_DEVICE_ID_INTEL_ICH9_0:
1011     case PCI_DEVICE_ID_INTEL_ICH9_1:
1012     case PCI_DEVICE_ID_INTEL_ICH9_2:
1013     case PCI_DEVICE_ID_INTEL_ICH9_3:
1014     case PCI_DEVICE_ID_INTEL_ICH9_4:
1015     case PCI_DEVICE_ID_INTEL_ICH9_5:
1016     case PCI_DEVICE_ID_INTEL_EP80579_0:
1017     case PCI_DEVICE_ID_INTEL_ICH10_0:
1018     case PCI_DEVICE_ID_INTEL_ICH10_1:
1019     case PCI_DEVICE_ID_INTEL_ICH10_2:
1020     case PCI_DEVICE_ID_INTEL_ICH10_3:
1021     case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0:
1022     case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1:
1023         r->name = "PIIX/ICH";
1024         r->get = pirq_piix_get;
1025         r->set = pirq_piix_set;
1026         return 1;
1027     case PCI_DEVICE_ID_INTEL_82425:
1028         r->name = "PSC/IB";
1029         r->get = pirq_ib_get;
1030         r->set = pirq_ib_set;
1031         return 1;
1032     }
1033 
1034     if ((device >= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN && 
1035          device <= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX) 
1036     ||  (device >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && 
1037          device <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX)
1038     ||  (device >= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN &&
1039          device <= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX)
1040     ||  (device >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
1041          device <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) {
1042         r->name = "PIIX/ICH";
1043         r->get = pirq_piix_get;
1044         r->set = pirq_piix_set;
1045         return 1;
1046     }
1047 
1048     return 0;
1049 }
1050 
1051 static __init int via_router_probe(struct irq_router *r,
1052                 struct pci_dev *router, u16 device)
1053 {
1054     /* FIXME: We should move some of the quirk fixup stuff here */
1055 
1056     /*
1057      * workarounds for some buggy BIOSes
1058      */
1059     if (device == PCI_DEVICE_ID_VIA_82C586_0) {
1060         switch (router->device) {
1061         case PCI_DEVICE_ID_VIA_82C686:
1062             /*
1063              * Asus k7m bios wrongly reports 82C686A
1064              * as 586-compatible
1065              */
1066             device = PCI_DEVICE_ID_VIA_82C686;
1067             break;
1068         case PCI_DEVICE_ID_VIA_8235:
1069             /**
1070              * Asus a7v-x bios wrongly reports 8235
1071              * as 586-compatible
1072              */
1073             device = PCI_DEVICE_ID_VIA_8235;
1074             break;
1075         case PCI_DEVICE_ID_VIA_8237:
1076             /**
1077              * Asus a7v600 bios wrongly reports 8237
1078              * as 586-compatible
1079              */
1080             device = PCI_DEVICE_ID_VIA_8237;
1081             break;
1082         }
1083     }
1084 
1085     switch (device) {
1086     case PCI_DEVICE_ID_VIA_82C586_0:
1087         r->name = "VIA";
1088         r->get = pirq_via586_get;
1089         r->set = pirq_via586_set;
1090         return 1;
1091     case PCI_DEVICE_ID_VIA_82C596:
1092     case PCI_DEVICE_ID_VIA_82C686:
1093     case PCI_DEVICE_ID_VIA_8231:
1094     case PCI_DEVICE_ID_VIA_8233A:
1095     case PCI_DEVICE_ID_VIA_8235:
1096     case PCI_DEVICE_ID_VIA_8237:
1097         /* FIXME: add new ones for 8233/5 */
1098         r->name = "VIA";
1099         r->get = pirq_via_get;
1100         r->set = pirq_via_set;
1101         return 1;
1102     }
1103     return 0;
1104 }
1105 
1106 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1107 {
1108     switch (device) {
1109     case PCI_DEVICE_ID_VLSI_82C534:
1110         r->name = "VLSI 82C534";
1111         r->get = pirq_vlsi_get;
1112         r->set = pirq_vlsi_set;
1113         return 1;
1114     }
1115     return 0;
1116 }
1117 
1118 
1119 static __init int serverworks_router_probe(struct irq_router *r,
1120         struct pci_dev *router, u16 device)
1121 {
1122     switch (device) {
1123     case PCI_DEVICE_ID_SERVERWORKS_OSB4:
1124     case PCI_DEVICE_ID_SERVERWORKS_CSB5:
1125         r->name = "ServerWorks";
1126         r->get = pirq_serverworks_get;
1127         r->set = pirq_serverworks_set;
1128         return 1;
1129     }
1130     return 0;
1131 }
1132 
1133 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1134 {
1135     switch (device) {
1136     case PCI_DEVICE_ID_SI_496:
1137         r->name = "SiS85C497";
1138         r->get = pirq_sis497_get;
1139         r->set = pirq_sis497_set;
1140         return 1;
1141     case PCI_DEVICE_ID_SI_503:
1142         r->name = "SiS85C503";
1143         r->get = pirq_sis503_get;
1144         r->set = pirq_sis503_set;
1145         return 1;
1146     }
1147     return 0;
1148 }
1149 
1150 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1151 {
1152     switch (device) {
1153     case PCI_DEVICE_ID_CYRIX_5520:
1154         r->name = "NatSemi";
1155         r->get = pirq_cyrix_get;
1156         r->set = pirq_cyrix_set;
1157         return 1;
1158     }
1159     return 0;
1160 }
1161 
1162 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1163 {
1164     switch (device) {
1165     case PCI_DEVICE_ID_OPTI_82C700:
1166         r->name = "OPTI";
1167         r->get = pirq_opti_get;
1168         r->set = pirq_opti_set;
1169         return 1;
1170     }
1171     return 0;
1172 }
1173 
1174 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1175 {
1176     switch (device) {
1177     case PCI_DEVICE_ID_ITE_IT8330G_0:
1178         r->name = "ITE";
1179         r->get = pirq_ite_get;
1180         r->set = pirq_ite_set;
1181         return 1;
1182     }
1183     return 0;
1184 }
1185 
1186 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1187 {
1188     switch (device) {
1189     case PCI_DEVICE_ID_AL_M1489:
1190         r->name = "FinALi";
1191         r->get = pirq_finali_get;
1192         r->set = pirq_finali_set;
1193         r->lvl = pirq_finali_lvl;
1194         return 1;
1195     case PCI_DEVICE_ID_AL_M1533:
1196     case PCI_DEVICE_ID_AL_M1563:
1197         r->name = "ALI";
1198         r->get = pirq_ali_get;
1199         r->set = pirq_ali_set;
1200         return 1;
1201     }
1202     return 0;
1203 }
1204 
1205 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1206 {
1207     switch (device) {
1208     case PCI_DEVICE_ID_AMD_VIPER_740B:
1209         r->name = "AMD756";
1210         break;
1211     case PCI_DEVICE_ID_AMD_VIPER_7413:
1212         r->name = "AMD766";
1213         break;
1214     case PCI_DEVICE_ID_AMD_VIPER_7443:
1215         r->name = "AMD768";
1216         break;
1217     default:
1218         return 0;
1219     }
1220     r->get = pirq_amd756_get;
1221     r->set = pirq_amd756_set;
1222     return 1;
1223 }
1224 
1225 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
1226 {
1227     switch (device) {
1228     case PCI_DEVICE_ID_PICOPOWER_PT86C523:
1229         r->name = "PicoPower PT86C523";
1230         r->get = pirq_pico_get;
1231         r->set = pirq_pico_set;
1232         return 1;
1233 
1234     case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP:
1235         r->name = "PicoPower PT86C523 rev. BB+";
1236         r->get = pirq_pico_get;
1237         r->set = pirq_pico_set;
1238         return 1;
1239     }
1240     return 0;
1241 }
1242 
1243 static __initdata struct irq_router_handler pirq_routers[] = {
1244     { PCI_VENDOR_ID_INTEL, intel_router_probe },
1245     { PCI_VENDOR_ID_AL, ali_router_probe },
1246     { PCI_VENDOR_ID_ITE, ite_router_probe },
1247     { PCI_VENDOR_ID_VIA, via_router_probe },
1248     { PCI_VENDOR_ID_OPTI, opti_router_probe },
1249     { PCI_VENDOR_ID_SI, sis_router_probe },
1250     { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
1251     { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
1252     { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
1253     { PCI_VENDOR_ID_AMD, amd_router_probe },
1254     { PCI_VENDOR_ID_PICOPOWER, pico_router_probe },
1255     /* Someone with docs needs to add the ATI Radeon IGP */
1256     { 0, NULL }
1257 };
1258 static struct irq_router pirq_router;
1259 static struct pci_dev *pirq_router_dev;
1260 
1261 
1262 /*
1263  *  FIXME: should we have an option to say "generic for
1264  *  chipset" ?
1265  */
1266 
1267 static bool __init pirq_try_router(struct irq_router *r,
1268                    struct irq_routing_table *rt,
1269                    struct pci_dev *dev)
1270 {
1271     struct irq_router_handler *h;
1272 
1273     DBG(KERN_DEBUG "PCI: Trying IRQ router for [%04x:%04x]\n",
1274         dev->vendor, dev->device);
1275 
1276     for (h = pirq_routers; h->vendor; h++) {
1277         /* First look for a router match */
1278         if (rt->rtr_vendor == h->vendor &&
1279             h->probe(r, dev, rt->rtr_device))
1280             return true;
1281         /* Fall back to a device match */
1282         if (dev->vendor == h->vendor &&
1283             h->probe(r, dev, dev->device))
1284             return true;
1285     }
1286     return false;
1287 }
1288 
1289 static void __init pirq_find_router(struct irq_router *r)
1290 {
1291     struct irq_routing_table *rt = pirq_table;
1292     struct pci_dev *dev;
1293 
1294 #ifdef CONFIG_PCI_BIOS
1295     if (!rt->signature) {
1296         printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
1297         r->set = pirq_bios_set;
1298         r->name = "BIOS";
1299         return;
1300     }
1301 #endif
1302 
1303     /* Default unless a driver reloads it */
1304     r->name = "default";
1305     r->get = NULL;
1306     r->set = NULL;
1307 
1308     DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n",
1309         rt->rtr_vendor, rt->rtr_device);
1310 
1311     /* Use any vendor:device provided by the routing table or try all.  */
1312     if (rt->rtr_vendor) {
1313         dev = pci_get_domain_bus_and_slot(0, rt->rtr_bus,
1314                           rt->rtr_devfn);
1315         if (dev && pirq_try_router(r, rt, dev))
1316             pirq_router_dev = dev;
1317     } else {
1318         dev = NULL;
1319         for_each_pci_dev(dev) {
1320             if (pirq_try_router(r, rt, dev)) {
1321                 pirq_router_dev = dev;
1322                 break;
1323             }
1324         }
1325     }
1326 
1327     if (pirq_router_dev)
1328         dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n",
1329              pirq_router.name,
1330              pirq_router_dev->vendor, pirq_router_dev->device);
1331     else
1332         DBG(KERN_DEBUG "PCI: Interrupt router not found at "
1333             "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
1334 
1335     /* The device remains referenced for the kernel lifetime */
1336 }
1337 
1338 /*
1339  * We're supposed to match on the PCI device only and not the function,
1340  * but some BIOSes build their tables with the PCI function included
1341  * for motherboard devices, so if a complete match is found, then give
1342  * it precedence over a slot match.
1343  */
1344 static struct irq_info *pirq_get_dev_info(struct pci_dev *dev)
1345 {
1346     struct irq_routing_table *rt = pirq_table;
1347     int entries = (rt->size - sizeof(struct irq_routing_table)) /
1348         sizeof(struct irq_info);
1349     struct irq_info *slotinfo = NULL;
1350     struct irq_info *info;
1351 
1352     for (info = rt->slots; entries--; info++)
1353         if (info->bus == dev->bus->number) {
1354             if (info->devfn == dev->devfn)
1355                 return info;
1356             if (!slotinfo &&
1357                 PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
1358                 slotinfo = info;
1359         }
1360     return slotinfo;
1361 }
1362 
1363 /*
1364  * Buses behind bridges are typically not listed in the PIRQ routing table.
1365  * Do the usual dance then and walk the tree of bridges up adjusting the
1366  * pin number accordingly on the way until the originating root bus device
1367  * has been reached and then use its routing information.
1368  */
1369 static struct irq_info *pirq_get_info(struct pci_dev *dev, u8 *pin)
1370 {
1371     struct pci_dev *temp_dev = dev;
1372     struct irq_info *info;
1373     u8 temp_pin = *pin;
1374     u8 dpin = temp_pin;
1375 
1376     info = pirq_get_dev_info(dev);
1377     while (!info && temp_dev->bus->parent) {
1378         struct pci_dev *bridge = temp_dev->bus->self;
1379 
1380         temp_pin = pci_swizzle_interrupt_pin(temp_dev, temp_pin);
1381         info = pirq_get_dev_info(bridge);
1382         if (info)
1383             dev_warn(&dev->dev,
1384                  "using bridge %s INT %c to get INT %c\n",
1385                  pci_name(bridge),
1386                  'A' + temp_pin - 1, 'A' + dpin - 1);
1387 
1388         temp_dev = bridge;
1389     }
1390     *pin = temp_pin;
1391     return info;
1392 }
1393 
1394 static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
1395 {
1396     struct irq_info *info;
1397     int i, pirq, newirq;
1398     u8 dpin, pin;
1399     int irq = 0;
1400     u32 mask;
1401     struct irq_router *r = &pirq_router;
1402     struct pci_dev *dev2 = NULL;
1403     char *msg = NULL;
1404 
1405     /* Find IRQ pin */
1406     pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &dpin);
1407     if (!dpin) {
1408         dev_dbg(&dev->dev, "no interrupt pin\n");
1409         return 0;
1410     }
1411 
1412     if (io_apic_assign_pci_irqs)
1413         return 0;
1414 
1415     /* Find IRQ routing entry */
1416 
1417     if (!pirq_table)
1418         return 0;
1419 
1420     pin = dpin;
1421     info = pirq_get_info(dev, &pin);
1422     if (!info) {
1423         dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n",
1424             'A' + dpin - 1);
1425         return 0;
1426     }
1427     pirq = info->irq[pin - 1].link;
1428     mask = info->irq[pin - 1].bitmap;
1429     if (!pirq) {
1430         dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + dpin - 1);
1431         return 0;
1432     }
1433     dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x",
1434         'A' + dpin - 1, pirq, mask, pirq_table->exclusive_irqs);
1435     mask &= pcibios_irq_mask;
1436 
1437     /* Work around broken HP Pavilion Notebooks which assign USB to
1438        IRQ 9 even though it is actually wired to IRQ 11 */
1439 
1440     if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
1441         dev->irq = 11;
1442         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
1443         r->set(pirq_router_dev, dev, pirq, 11);
1444     }
1445 
1446     /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
1447     if (acer_tm360_irqrouting && dev->irq == 11 &&
1448         dev->vendor == PCI_VENDOR_ID_O2) {
1449         pirq = 0x68;
1450         mask = 0x400;
1451         dev->irq = r->get(pirq_router_dev, dev, pirq);
1452         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
1453     }
1454 
1455     /*
1456      * Find the best IRQ to assign: use the one
1457      * reported by the device if possible.
1458      */
1459     newirq = dev->irq;
1460     if (newirq && !((1 << newirq) & mask)) {
1461         if (pci_probe & PCI_USE_PIRQ_MASK)
1462             newirq = 0;
1463         else
1464             dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask "
1465                  "%#x; try pci=usepirqmask\n", newirq, mask);
1466     }
1467     if (!newirq && assign) {
1468         for (i = 0; i < 16; i++) {
1469             if (!(mask & (1 << i)))
1470                 continue;
1471             if (pirq_penalty[i] < pirq_penalty[newirq] &&
1472                 can_request_irq(i, IRQF_SHARED))
1473                 newirq = i;
1474         }
1475     }
1476     dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + dpin - 1, newirq);
1477 
1478     /* Check if it is hardcoded */
1479     if ((pirq & 0xf0) == 0xf0) {
1480         irq = pirq & 0xf;
1481         msg = "hardcoded";
1482     } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
1483     ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) {
1484         msg = "found";
1485         if (r->lvl)
1486             r->lvl(pirq_router_dev, dev, pirq, irq);
1487         else
1488             elcr_set_level_irq(irq);
1489     } else if (newirq && r->set &&
1490         (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
1491         if (r->set(pirq_router_dev, dev, pirq, newirq)) {
1492             if (r->lvl)
1493                 r->lvl(pirq_router_dev, dev, pirq, newirq);
1494             else
1495                 elcr_set_level_irq(newirq);
1496             msg = "assigned";
1497             irq = newirq;
1498         }
1499     }
1500 
1501     if (!irq) {
1502         if (newirq && mask == (1 << newirq)) {
1503             msg = "guessed";
1504             irq = newirq;
1505         } else {
1506             dev_dbg(&dev->dev, "can't route interrupt\n");
1507             return 0;
1508         }
1509     }
1510     dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n",
1511          msg, 'A' + dpin - 1, irq);
1512 
1513     /* Update IRQ for all devices with the same pirq value */
1514     for_each_pci_dev(dev2) {
1515         pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &dpin);
1516         if (!dpin)
1517             continue;
1518 
1519         pin = dpin;
1520         info = pirq_get_info(dev2, &pin);
1521         if (!info)
1522             continue;
1523         if (info->irq[pin - 1].link == pirq) {
1524             /*
1525              * We refuse to override the dev->irq
1526              * information. Give a warning!
1527              */
1528             if (dev2->irq && dev2->irq != irq && \
1529             (!(pci_probe & PCI_USE_PIRQ_MASK) || \
1530             ((1 << dev2->irq) & mask))) {
1531 #ifndef CONFIG_PCI_MSI
1532                 dev_info(&dev2->dev, "IRQ routing conflict: "
1533                      "have IRQ %d, want IRQ %d\n",
1534                      dev2->irq, irq);
1535 #endif
1536                 continue;
1537             }
1538             dev2->irq = irq;
1539             pirq_penalty[irq]++;
1540             if (dev != dev2)
1541                 dev_info(&dev->dev, "sharing IRQ %d with %s\n",
1542                      irq, pci_name(dev2));
1543         }
1544     }
1545     return 1;
1546 }
1547 
1548 void __init pcibios_fixup_irqs(void)
1549 {
1550     struct pci_dev *dev = NULL;
1551     u8 pin;
1552 
1553     DBG(KERN_DEBUG "PCI: IRQ fixup\n");
1554     for_each_pci_dev(dev) {
1555         /*
1556          * If the BIOS has set an out of range IRQ number, just
1557          * ignore it.  Also keep track of which IRQ's are
1558          * already in use.
1559          */
1560         if (dev->irq >= 16) {
1561             dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq);
1562             dev->irq = 0;
1563         }
1564         /*
1565          * If the IRQ is already assigned to a PCI device,
1566          * ignore its ISA use penalty
1567          */
1568         if (pirq_penalty[dev->irq] >= 100 &&
1569                 pirq_penalty[dev->irq] < 100000)
1570             pirq_penalty[dev->irq] = 0;
1571         pirq_penalty[dev->irq]++;
1572     }
1573 
1574     if (io_apic_assign_pci_irqs)
1575         return;
1576 
1577     dev = NULL;
1578     for_each_pci_dev(dev) {
1579         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1580         if (!pin)
1581             continue;
1582 
1583         /*
1584          * Still no IRQ? Try to lookup one...
1585          */
1586         if (!dev->irq)
1587             pcibios_lookup_irq(dev, 0);
1588     }
1589 }
1590 
1591 /*
1592  * Work around broken HP Pavilion Notebooks which assign USB to
1593  * IRQ 9 even though it is actually wired to IRQ 11
1594  */
1595 static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d)
1596 {
1597     if (!broken_hp_bios_irq9) {
1598         broken_hp_bios_irq9 = 1;
1599         printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1600             d->ident);
1601     }
1602     return 0;
1603 }
1604 
1605 /*
1606  * Work around broken Acer TravelMate 360 Notebooks which assign
1607  * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
1608  */
1609 static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d)
1610 {
1611     if (!acer_tm360_irqrouting) {
1612         acer_tm360_irqrouting = 1;
1613         printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
1614             d->ident);
1615     }
1616     return 0;
1617 }
1618 
1619 static const struct dmi_system_id pciirq_dmi_table[] __initconst = {
1620     {
1621         .callback = fix_broken_hp_bios_irq9,
1622         .ident = "HP Pavilion N5400 Series Laptop",
1623         .matches = {
1624             DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1625             DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
1626             DMI_MATCH(DMI_PRODUCT_VERSION,
1627                 "HP Pavilion Notebook Model GE"),
1628             DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
1629         },
1630     },
1631     {
1632         .callback = fix_acer_tm360_irqrouting,
1633         .ident = "Acer TravelMate 36x Laptop",
1634         .matches = {
1635             DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1636             DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
1637         },
1638     },
1639     { }
1640 };
1641 
1642 void __init pcibios_irq_init(void)
1643 {
1644     struct irq_routing_table *rtable = NULL;
1645 
1646     DBG(KERN_DEBUG "PCI: IRQ init\n");
1647 
1648     if (raw_pci_ops == NULL)
1649         return;
1650 
1651     dmi_check_system(pciirq_dmi_table);
1652 
1653     pirq_table = pirq_find_routing_table();
1654 
1655 #ifdef CONFIG_PCI_BIOS
1656     if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) {
1657         pirq_table = pcibios_get_irq_routing_table();
1658         rtable = pirq_table;
1659     }
1660 #endif
1661     if (pirq_table) {
1662         pirq_peer_trick();
1663         pirq_find_router(&pirq_router);
1664         if (pirq_table->exclusive_irqs) {
1665             int i;
1666             for (i = 0; i < 16; i++)
1667                 if (!(pirq_table->exclusive_irqs & (1 << i)))
1668                     pirq_penalty[i] += 100;
1669         }
1670         /*
1671          * If we're using the I/O APIC, avoid using the PCI IRQ
1672          * routing table
1673          */
1674         if (io_apic_assign_pci_irqs) {
1675             kfree(rtable);
1676             pirq_table = NULL;
1677         }
1678     }
1679 
1680     x86_init.pci.fixup_irqs();
1681 
1682     if (io_apic_assign_pci_irqs && pci_routeirq) {
1683         struct pci_dev *dev = NULL;
1684         /*
1685          * PCI IRQ routing is set up by pci_enable_device(), but we
1686          * also do it here in case there are still broken drivers that
1687          * don't use pci_enable_device().
1688          */
1689         printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n");
1690         for_each_pci_dev(dev)
1691             pirq_enable_irq(dev);
1692     }
1693 }
1694 
1695 static void pirq_penalize_isa_irq(int irq, int active)
1696 {
1697     /*
1698      *  If any ISAPnP device reports an IRQ in its list of possible
1699      *  IRQ's, we try to avoid assigning it to PCI devices.
1700      */
1701     if (irq < 16) {
1702         if (active)
1703             pirq_penalty[irq] += 1000;
1704         else
1705             pirq_penalty[irq] += 100;
1706     }
1707 }
1708 
1709 void pcibios_penalize_isa_irq(int irq, int active)
1710 {
1711 #ifdef CONFIG_ACPI
1712     if (!acpi_noirq)
1713         acpi_penalize_isa_irq(irq, active);
1714     else
1715 #endif
1716         pirq_penalize_isa_irq(irq, active);
1717 }
1718 
1719 static int pirq_enable_irq(struct pci_dev *dev)
1720 {
1721     u8 pin = 0;
1722 
1723     pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1724     if (pin && !pcibios_lookup_irq(dev, 1)) {
1725         char *msg = "";
1726 
1727         if (!io_apic_assign_pci_irqs && dev->irq)
1728             return 0;
1729 
1730         if (io_apic_assign_pci_irqs) {
1731 #ifdef CONFIG_X86_IO_APIC
1732             struct pci_dev *temp_dev;
1733             int irq;
1734 
1735             if (dev->irq_managed && dev->irq > 0)
1736                 return 0;
1737 
1738             irq = IO_APIC_get_PCI_irq_vector(dev->bus->number,
1739                         PCI_SLOT(dev->devfn), pin - 1);
1740             /*
1741              * Busses behind bridges are typically not listed in the MP-table.
1742              * In this case we have to look up the IRQ based on the parent bus,
1743              * parent slot, and pin number. The SMP code detects such bridged
1744              * busses itself so we should get into this branch reliably.
1745              */
1746             temp_dev = dev;
1747             while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1748                 struct pci_dev *bridge = dev->bus->self;
1749 
1750                 pin = pci_swizzle_interrupt_pin(dev, pin);
1751                 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1752                         PCI_SLOT(bridge->devfn),
1753                         pin - 1);
1754                 if (irq >= 0)
1755                     dev_warn(&dev->dev, "using bridge %s "
1756                          "INT %c to get IRQ %d\n",
1757                          pci_name(bridge), 'A' + pin - 1,
1758                          irq);
1759                 dev = bridge;
1760             }
1761             dev = temp_dev;
1762             if (irq >= 0) {
1763                 dev->irq_managed = 1;
1764                 dev->irq = irq;
1765                 dev_info(&dev->dev, "PCI->APIC IRQ transform: "
1766                      "INT %c -> IRQ %d\n", 'A' + pin - 1, irq);
1767                 return 0;
1768             } else
1769                 msg = "; probably buggy MP table";
1770 #endif
1771         } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1772             msg = "";
1773         else
1774             msg = "; please try using pci=biosirq";
1775 
1776         /*
1777          * With IDE legacy devices the IRQ lookup failure is not
1778          * a problem..
1779          */
1780         if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE &&
1781                 !(dev->class & 0x5))
1782             return 0;
1783 
1784         dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n",
1785              'A' + pin - 1, msg);
1786     }
1787     return 0;
1788 }
1789 
1790 bool mp_should_keep_irq(struct device *dev)
1791 {
1792     if (dev->power.is_prepared)
1793         return true;
1794 #ifdef CONFIG_PM
1795     if (dev->power.runtime_status == RPM_SUSPENDING)
1796         return true;
1797 #endif
1798 
1799     return false;
1800 }
1801 
1802 static void pirq_disable_irq(struct pci_dev *dev)
1803 {
1804     if (io_apic_assign_pci_irqs && !mp_should_keep_irq(&dev->dev) &&
1805         dev->irq_managed && dev->irq) {
1806         mp_unmap_irq(dev->irq);
1807         dev->irq = 0;
1808         dev->irq_managed = 0;
1809     }
1810 }
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