x86/pci/intel_mid_pci.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Intel MID PCI support
0004  *   Copyright (c) 2008 Intel Corporation
0005  *     Jesse Barnes <jesse.barnes@intel.com>
0006  *
0007  * Moorestown has an interesting PCI implementation:
0008  *   - configuration space is memory mapped (as defined by MCFG)
0009  *   - Lincroft devices also have a real, type 1 configuration space
0010  *   - Early Lincroft silicon has a type 1 access bug that will cause
0011  *     a hang if non-existent devices are accessed
0012  *   - some devices have the "fixed BAR" capability, which means
0013  *     they can't be relocated or modified; check for that during
0014  *     BAR sizing
0015  *
0016  * So, we use the MCFG space for all reads and writes, but also send
0017  * Lincroft writes to type 1 space.  But only read/write if the device
0018  * actually exists, otherwise return all 1s for reads and bit bucket
0019  * the writes.
0020  */
0021
0022 #include <linux/sched.h>
0023 #include <linux/pci.h>
0024 #include <linux/ioport.h>
0025 #include <linux/init.h>
0026 #include <linux/dmi.h>
0027 #include <linux/acpi.h>
0028 #include <linux/io.h>
0029 #include <linux/smp.h>
0030
0031 #include <asm/cpu_device_id.h>
0032 #include <asm/segment.h>
0033 #include <asm/pci_x86.h>
0034 #include <asm/hw_irq.h>
0035 #include <asm/io_apic.h>
0036 #include <asm/intel-family.h>
0037 #include <asm/intel-mid.h>
0038 #include <asm/acpi.h>
0039
0040 #define PCIE_CAP_OFFSET 0x100
0041
0042 /* Quirks for the listed devices */
0043 #define PCI_DEVICE_ID_INTEL_MRFLD_MMC   0x1190
0044 #define PCI_DEVICE_ID_INTEL_MRFLD_HSU   0x1191
0045
0046 /* Fixed BAR fields */
0047 #define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00 /* Fixed BAR (TBD) */
0048 #define PCI_FIXED_BAR_0_SIZE    0x04
0049 #define PCI_FIXED_BAR_1_SIZE    0x08
0050 #define PCI_FIXED_BAR_2_SIZE    0x0c
0051 #define PCI_FIXED_BAR_3_SIZE    0x10
0052 #define PCI_FIXED_BAR_4_SIZE    0x14
0053 #define PCI_FIXED_BAR_5_SIZE    0x1c
0054
0055 static int pci_soc_mode;
0056
0057 /**
0058  * fixed_bar_cap - return the offset of the fixed BAR cap if found
0059  * @bus: PCI bus
0060  * @devfn: device in question
0061  *
0062  * Look for the fixed BAR cap on @bus and @devfn, returning its offset
0063  * if found or 0 otherwise.
0064  */
0065 static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn)
0066 {
0067     int pos;
0068     u32 pcie_cap = 0, cap_data;
0069
0070     pos = PCIE_CAP_OFFSET;
0071
0072     if (!raw_pci_ext_ops)
0073         return 0;
0074
0075     while (pos) {
0076         if (raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
0077                       devfn, pos, 4, &pcie_cap))
0078             return 0;
0079
0080         if (PCI_EXT_CAP_ID(pcie_cap) == 0x0000 ||
0081             PCI_EXT_CAP_ID(pcie_cap) == 0xffff)
0082             break;
0083
0084         if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) {
0085             raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
0086                           devfn, pos + 4, 4, &cap_data);
0087             if ((cap_data & 0xffff) == PCIE_VNDR_CAP_ID_FIXED_BAR)
0088                 return pos;
0089         }
0090
0091         pos = PCI_EXT_CAP_NEXT(pcie_cap);
0092     }
0093
0094     return 0;
0095 }
0096
0097 static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
0098                    int reg, int len, u32 val, int offset)
0099 {
0100     u32 size;
0101     unsigned int domain, busnum;
0102     int bar = (reg - PCI_BASE_ADDRESS_0) >> 2;
0103
0104     domain = pci_domain_nr(bus);
0105     busnum = bus->number;
0106
0107     if (val == ~0 && len == 4) {
0108         unsigned long decode;
0109
0110         raw_pci_ext_ops->read(domain, busnum, devfn,
0111                    offset + 8 + (bar * 4), 4, &size);
0112
0113         /* Turn the size into a decode pattern for the sizing code */
0114         if (size) {
0115             decode = size - 1;
0116             decode |= decode >> 1;
0117             decode |= decode >> 2;
0118             decode |= decode >> 4;
0119             decode |= decode >> 8;
0120             decode |= decode >> 16;
0121             decode++;
0122             decode = ~(decode - 1);
0123         } else {
0124             decode = 0;
0125         }
0126
0127         /*
0128          * If val is all ones, the core code is trying to size the reg,
0129          * so update the mmconfig space with the real size.
0130          *
0131          * Note: this assumes the fixed size we got is a power of two.
0132          */
0133         return raw_pci_ext_ops->write(domain, busnum, devfn, reg, 4,
0134                        decode);
0135     }
0136
0137     /* This is some other kind of BAR write, so just do it. */
0138     return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val);
0139 }
0140
0141 /**
0142  * type1_access_ok - check whether to use type 1
0143  * @bus: bus number
0144  * @devfn: device & function in question
0145  * @reg: configuration register offset
0146  *
0147  * If the bus is on a Lincroft chip and it exists, or is not on a Lincroft at
0148  * all, the we can go ahead with any reads & writes.  If it's on a Lincroft,
0149  * but doesn't exist, avoid the access altogether to keep the chip from
0150  * hanging.
0151  */
0152 static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
0153 {
0154     /*
0155      * This is a workaround for A0 LNC bug where PCI status register does
0156      * not have new CAP bit set. can not be written by SW either.
0157      *
0158      * PCI header type in real LNC indicates a single function device, this
0159      * will prevent probing other devices under the same function in PCI
0160      * shim. Therefore, use the header type in shim instead.
0161      */
0162     if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE)
0163         return false;
0164     if (bus == 0 && (devfn == PCI_DEVFN(2, 0)
0165                 || devfn == PCI_DEVFN(0, 0)
0166                 || devfn == PCI_DEVFN(3, 0)))
0167         return true;
0168     return false; /* Langwell on others */
0169 }
0170
0171 static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
0172             int size, u32 *value)
0173 {
0174     if (type1_access_ok(bus->number, devfn, where))
0175         return pci_direct_conf1.read(pci_domain_nr(bus), bus->number,
0176                     devfn, where, size, value);
0177     return raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
0178                   devfn, where, size, value);
0179 }
0180
0181 static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
0182              int size, u32 value)
0183 {
0184     int offset;
0185
0186     /*
0187      * On MRST, there is no PCI ROM BAR, this will cause a subsequent read
0188      * to ROM BAR return 0 then being ignored.
0189      */
0190     if (where == PCI_ROM_ADDRESS)
0191         return 0;
0192
0193     /*
0194      * Devices with fixed BARs need special handling:
0195      *   - BAR sizing code will save, write ~0, read size, restore
0196      *   - so writes to fixed BARs need special handling
0197      *   - other writes to fixed BAR devices should go through mmconfig
0198      */
0199     offset = fixed_bar_cap(bus, devfn);
0200     if (offset &&
0201         (where >= PCI_BASE_ADDRESS_0 && where <= PCI_BASE_ADDRESS_5)) {
0202         return pci_device_update_fixed(bus, devfn, where, size, value,
0203                            offset);
0204     }
0205
0206     /*
0207      * On Moorestown update both real & mmconfig space
0208      * Note: early Lincroft silicon can't handle type 1 accesses to
0209      *       non-existent devices, so just eat the write in that case.
0210      */
0211     if (type1_access_ok(bus->number, devfn, where))
0212         return pci_direct_conf1.write(pci_domain_nr(bus), bus->number,
0213                           devfn, where, size, value);
0214     return raw_pci_ext_ops->write(pci_domain_nr(bus), bus->number, devfn,
0215                    where, size, value);
0216 }
0217
0218 static const struct x86_cpu_id intel_mid_cpu_ids[] = {
0219     X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, NULL),
0220     {}
0221 };
0222
0223 static int intel_mid_pci_irq_enable(struct pci_dev *dev)
0224 {
0225     const struct x86_cpu_id *id;
0226     struct irq_alloc_info info;
0227     bool polarity_low;
0228     u16 model = 0;
0229     int ret;
0230     u8 gsi;
0231
0232     if (dev->irq_managed && dev->irq > 0)
0233         return 0;
0234
0235     ret = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi);
0236     if (ret < 0) {
0237         dev_warn(&dev->dev, "Failed to read interrupt line: %d\n", ret);
0238         return ret;
0239     }
0240
0241     id = x86_match_cpu(intel_mid_cpu_ids);
0242     if (id)
0243         model = id->model;
0244
0245     switch (model) {
0246     case INTEL_FAM6_ATOM_SILVERMONT_MID:
0247         polarity_low = false;
0248
0249         /* Special treatment for IRQ0 */
0250         if (gsi == 0) {
0251             /*
0252              * Skip HS UART common registers device since it has
0253              * IRQ0 assigned and not used by the kernel.
0254              */
0255             if (dev->device == PCI_DEVICE_ID_INTEL_MRFLD_HSU)
0256                 return -EBUSY;
0257             /*
0258              * TNG has IRQ0 assigned to eMMC controller. But there
0259              * are also other devices with bogus PCI configuration
0260              * that have IRQ0 assigned. This check ensures that
0261              * eMMC gets it. The rest of devices still could be
0262              * enabled without interrupt line being allocated.
0263              */
0264             if (dev->device != PCI_DEVICE_ID_INTEL_MRFLD_MMC)
0265                 return 0;
0266         }
0267         break;
0268     default:
0269         polarity_low = true;
0270         break;
0271     }
0272
0273     ioapic_set_alloc_attr(&info, dev_to_node(&dev->dev), 1, polarity_low);
0274
0275     /*
0276      * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
0277      * IOAPIC RTE entries, so we just enable RTE for the device.
0278      */
0279     ret = mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC, &info);
0280     if (ret < 0)
0281         return ret;
0282
0283     dev->irq = ret;
0284     dev->irq_managed = 1;
0285
0286     return 0;
0287 }
0288
0289 static void intel_mid_pci_irq_disable(struct pci_dev *dev)
0290 {
0291     if (!mp_should_keep_irq(&dev->dev) && dev->irq_managed &&
0292         dev->irq > 0) {
0293         mp_unmap_irq(dev->irq);
0294         dev->irq_managed = 0;
0295     }
0296 }
0297
0298 static const struct pci_ops intel_mid_pci_ops __initconst = {
0299     .read = pci_read,
0300     .write = pci_write,
0301 };
0302
0303 /**
0304  * intel_mid_pci_init - installs intel_mid_pci_ops
0305  *
0306  * Moorestown has an interesting PCI implementation (see above).
0307  * Called when the early platform detection installs it.
0308  */
0309 int __init intel_mid_pci_init(void)
0310 {
0311     pr_info("Intel MID platform detected, using MID PCI ops\n");
0312     pci_mmcfg_late_init();
0313     pcibios_enable_irq = intel_mid_pci_irq_enable;
0314     pcibios_disable_irq = intel_mid_pci_irq_disable;
0315     pci_root_ops = intel_mid_pci_ops;
0316     pci_soc_mode = 1;
0317     /* Continue with standard init */
0318     acpi_noirq_set();
0319     return 1;
0320 }
0321
0322 /*
0323  * Langwell devices are not true PCI devices; they are not subject to 10 ms
0324  * d3 to d0 delay required by PCI spec.
0325  */
0326 static void pci_d3delay_fixup(struct pci_dev *dev)
0327 {
0328     /*
0329      * PCI fixups are effectively decided compile time. If we have a dual
0330      * SoC/non-SoC kernel we don't want to mangle d3 on non-SoC devices.
0331      */
0332     if (!pci_soc_mode)
0333         return;
0334     /*
0335      * True PCI devices in Lincroft should allow type 1 access, the rest
0336      * are Langwell fake PCI devices.
0337      */
0338     if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))
0339         return;
0340     dev->d3hot_delay = 0;
0341 }
0342 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);
0343
0344 static void mid_power_off_one_device(struct pci_dev *dev)
0345 {
0346     u16 pmcsr;
0347
0348     /*
0349      * Update current state first, otherwise PCI core enforces PCI_D0 in
0350      * pci_set_power_state() for devices which status was PCI_UNKNOWN.
0351      */
0352     pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
0353     dev->current_state = (pci_power_t __force)(pmcsr & PCI_PM_CTRL_STATE_MASK);
0354
0355     pci_set_power_state(dev, PCI_D3hot);
0356 }
0357
0358 static void mid_power_off_devices(struct pci_dev *dev)
0359 {
0360     int id;
0361
0362     if (!pci_soc_mode)
0363         return;
0364
0365     id = intel_mid_pwr_get_lss_id(dev);
0366     if (id < 0)
0367         return;
0368
0369     /*
0370      * This sets only PMCSR bits. The actual power off will happen in
0371      * arch/x86/platform/intel-mid/pwr.c.
0372      */
0373     mid_power_off_one_device(dev);
0374 }
0375
0376 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, mid_power_off_devices);
0377
0378 /*
0379  * Langwell devices reside at fixed offsets, don't try to move them.
0380  */
0381 static void pci_fixed_bar_fixup(struct pci_dev *dev)
0382 {
0383     unsigned long offset;
0384     u32 size;
0385     int i;
0386
0387     if (!pci_soc_mode)
0388         return;
0389
0390     /* Must have extended configuration space */
0391     if (dev->cfg_size < PCIE_CAP_OFFSET + 4)
0392         return;
0393
0394     /* Fixup the BAR sizes for fixed BAR devices and make them unmoveable */
0395     offset = fixed_bar_cap(dev->bus, dev->devfn);
0396     if (!offset || PCI_DEVFN(2, 0) == dev->devfn ||
0397         PCI_DEVFN(2, 2) == dev->devfn)
0398         return;
0399
0400     for (i = 0; i < PCI_STD_NUM_BARS; i++) {
0401         pci_read_config_dword(dev, offset + 8 + (i * 4), &size);
0402         dev->resource[i].end = dev->resource[i].start + size - 1;
0403         dev->resource[i].flags |= IORESOURCE_PCI_FIXED;
0404     }
0405 }
0406 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixed_bar_fixup);