x86/pci/i386.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  *  Low-Level PCI Access for i386 machines
0004  *
0005  * Copyright 1993, 1994 Drew Eckhardt
0006  *      Visionary Computing
0007  *      (Unix and Linux consulting and custom programming)
0008  *      Drew@Colorado.EDU
0009  *      +1 (303) 786-7975
0010  *
0011  * Drew's work was sponsored by:
0012  *  iX Multiuser Multitasking Magazine
0013  *  Hannover, Germany
0014  *  hm@ix.de
0015  *
0016  * Copyright 1997--2000 Martin Mares <mj@ucw.cz>
0017  *
0018  * For more information, please consult the following manuals (look at
0019  * http://www.pcisig.com/ for how to get them):
0020  *
0021  * PCI BIOS Specification
0022  * PCI Local Bus Specification
0023  * PCI to PCI Bridge Specification
0024  * PCI System Design Guide
0025  *
0026  */
0027
0028 #include <linux/types.h>
0029 #include <linux/kernel.h>
0030 #include <linux/export.h>
0031 #include <linux/pci.h>
0032 #include <linux/init.h>
0033 #include <linux/ioport.h>
0034 #include <linux/errno.h>
0035 #include <linux/memblock.h>
0036
0037 #include <asm/memtype.h>
0038 #include <asm/e820/api.h>
0039 #include <asm/pci_x86.h>
0040 #include <asm/io_apic.h>
0041
0042
0043 /*
0044  * This list of dynamic mappings is for temporarily maintaining
0045  * original BIOS BAR addresses for possible reinstatement.
0046  */
0047 struct pcibios_fwaddrmap {
0048     struct list_head list;
0049     struct pci_dev *dev;
0050     resource_size_t fw_addr[DEVICE_COUNT_RESOURCE];
0051 };
0052
0053 static LIST_HEAD(pcibios_fwaddrmappings);
0054 static DEFINE_SPINLOCK(pcibios_fwaddrmap_lock);
0055 static bool pcibios_fw_addr_done;
0056
0057 /* Must be called with 'pcibios_fwaddrmap_lock' lock held. */
0058 static struct pcibios_fwaddrmap *pcibios_fwaddrmap_lookup(struct pci_dev *dev)
0059 {
0060     struct pcibios_fwaddrmap *map;
0061
0062     lockdep_assert_held(&pcibios_fwaddrmap_lock);
0063
0064     list_for_each_entry(map, &pcibios_fwaddrmappings, list)
0065         if (map->dev == dev)
0066             return map;
0067
0068     return NULL;
0069 }
0070
0071 static void
0072 pcibios_save_fw_addr(struct pci_dev *dev, int idx, resource_size_t fw_addr)
0073 {
0074     unsigned long flags;
0075     struct pcibios_fwaddrmap *map;
0076
0077     if (pcibios_fw_addr_done)
0078         return;
0079
0080     spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
0081     map = pcibios_fwaddrmap_lookup(dev);
0082     if (!map) {
0083         spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
0084         map = kzalloc(sizeof(*map), GFP_KERNEL);
0085         if (!map)
0086             return;
0087
0088         map->dev = pci_dev_get(dev);
0089         map->fw_addr[idx] = fw_addr;
0090         INIT_LIST_HEAD(&map->list);
0091
0092         spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
0093         list_add_tail(&map->list, &pcibios_fwaddrmappings);
0094     } else
0095         map->fw_addr[idx] = fw_addr;
0096     spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
0097 }
0098
0099 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
0100 {
0101     unsigned long flags;
0102     struct pcibios_fwaddrmap *map;
0103     resource_size_t fw_addr = 0;
0104
0105     if (pcibios_fw_addr_done)
0106         return 0;
0107
0108     spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
0109     map = pcibios_fwaddrmap_lookup(dev);
0110     if (map)
0111         fw_addr = map->fw_addr[idx];
0112     spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
0113
0114     return fw_addr;
0115 }
0116
0117 static void __init pcibios_fw_addr_list_del(void)
0118 {
0119     unsigned long flags;
0120     struct pcibios_fwaddrmap *entry, *next;
0121
0122     spin_lock_irqsave(&pcibios_fwaddrmap_lock, flags);
0123     list_for_each_entry_safe(entry, next, &pcibios_fwaddrmappings, list) {
0124         list_del(&entry->list);
0125         pci_dev_put(entry->dev);
0126         kfree(entry);
0127     }
0128     spin_unlock_irqrestore(&pcibios_fwaddrmap_lock, flags);
0129     pcibios_fw_addr_done = true;
0130 }
0131
0132 static int
0133 skip_isa_ioresource_align(struct pci_dev *dev) {
0134
0135     if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) &&
0136         !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
0137         return 1;
0138     return 0;
0139 }
0140
0141 /*
0142  * We need to avoid collisions with `mirrored' VGA ports
0143  * and other strange ISA hardware, so we always want the
0144  * addresses to be allocated in the 0x000-0x0ff region
0145  * modulo 0x400.
0146  *
0147  * Why? Because some silly external IO cards only decode
0148  * the low 10 bits of the IO address. The 0x00-0xff region
0149  * is reserved for motherboard devices that decode all 16
0150  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
0151  * but we want to try to avoid allocating at 0x2900-0x2bff
0152  * which might have be mirrored at 0x0100-0x03ff..
0153  */
0154 resource_size_t
0155 pcibios_align_resource(void *data, const struct resource *res,
0156             resource_size_t size, resource_size_t align)
0157 {
0158     struct pci_dev *dev = data;
0159     resource_size_t start = res->start;
0160
0161     if (res->flags & IORESOURCE_IO) {
0162         if (skip_isa_ioresource_align(dev))
0163             return start;
0164         if (start & 0x300)
0165             start = (start + 0x3ff) & ~0x3ff;
0166     } else if (res->flags & IORESOURCE_MEM) {
0167         /* The low 1MB range is reserved for ISA cards */
0168         if (start < BIOS_END)
0169             start = BIOS_END;
0170     }
0171     return start;
0172 }
0173 EXPORT_SYMBOL(pcibios_align_resource);
0174
0175 /*
0176  *  Handle resources of PCI devices.  If the world were perfect, we could
0177  *  just allocate all the resource regions and do nothing more.  It isn't.
0178  *  On the other hand, we cannot just re-allocate all devices, as it would
0179  *  require us to know lots of host bridge internals.  So we attempt to
0180  *  keep as much of the original configuration as possible, but tweak it
0181  *  when it's found to be wrong.
0182  *
0183  *  Known BIOS problems we have to work around:
0184  *  - I/O or memory regions not configured
0185  *  - regions configured, but not enabled in the command register
0186  *  - bogus I/O addresses above 64K used
0187  *  - expansion ROMs left enabled (this may sound harmless, but given
0188  *    the fact the PCI specs explicitly allow address decoders to be
0189  *    shared between expansion ROMs and other resource regions, it's
0190  *    at least dangerous)
0191  *  - bad resource sizes or overlaps with other regions
0192  *
0193  *  Our solution:
0194  *  (1) Allocate resources for all buses behind PCI-to-PCI bridges.
0195  *      This gives us fixed barriers on where we can allocate.
0196  *  (2) Allocate resources for all enabled devices.  If there is
0197  *      a collision, just mark the resource as unallocated. Also
0198  *      disable expansion ROMs during this step.
0199  *  (3) Try to allocate resources for disabled devices.  If the
0200  *      resources were assigned correctly, everything goes well,
0201  *      if they weren't, they won't disturb allocation of other
0202  *      resources.
0203  *  (4) Assign new addresses to resources which were either
0204  *      not configured at all or misconfigured.  If explicitly
0205  *      requested by the user, configure expansion ROM address
0206  *      as well.
0207  */
0208
0209 static void pcibios_allocate_bridge_resources(struct pci_dev *dev)
0210 {
0211     int idx;
0212     struct resource *r;
0213
0214     for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
0215         r = &dev->resource[idx];
0216         if (!r->flags)
0217             continue;
0218         if (r->parent)  /* Already allocated */
0219             continue;
0220         if (!r->start || pci_claim_bridge_resource(dev, idx) < 0) {
0221             /*
0222              * Something is wrong with the region.
0223              * Invalidate the resource to prevent
0224              * child resource allocations in this
0225              * range.
0226              */
0227             r->start = r->end = 0;
0228             r->flags = 0;
0229         }
0230     }
0231 }
0232
0233 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
0234 {
0235     struct pci_bus *child;
0236
0237     /* Depth-First Search on bus tree */
0238     if (bus->self)
0239         pcibios_allocate_bridge_resources(bus->self);
0240     list_for_each_entry(child, &bus->children, node)
0241         pcibios_allocate_bus_resources(child);
0242 }
0243
0244 struct pci_check_idx_range {
0245     int start;
0246     int end;
0247 };
0248
0249 static void pcibios_allocate_dev_resources(struct pci_dev *dev, int pass)
0250 {
0251     int idx, disabled, i;
0252     u16 command;
0253     struct resource *r;
0254
0255     struct pci_check_idx_range idx_range[] = {
0256         { PCI_STD_RESOURCES, PCI_STD_RESOURCE_END },
0257 #ifdef CONFIG_PCI_IOV
0258         { PCI_IOV_RESOURCES, PCI_IOV_RESOURCE_END },
0259 #endif
0260     };
0261
0262     pci_read_config_word(dev, PCI_COMMAND, &command);
0263     for (i = 0; i < ARRAY_SIZE(idx_range); i++)
0264         for (idx = idx_range[i].start; idx <= idx_range[i].end; idx++) {
0265             r = &dev->resource[idx];
0266             if (r->parent)  /* Already allocated */
0267                 continue;
0268             if (!r->start)  /* Address not assigned at all */
0269                 continue;
0270             if (r->flags & IORESOURCE_IO)
0271                 disabled = !(command & PCI_COMMAND_IO);
0272             else
0273                 disabled = !(command & PCI_COMMAND_MEMORY);
0274             if (pass == disabled) {
0275                 dev_dbg(&dev->dev,
0276                     "BAR %d: reserving %pr (d=%d, p=%d)\n",
0277                     idx, r, disabled, pass);
0278                 if (pci_claim_resource(dev, idx) < 0) {
0279                     if (r->flags & IORESOURCE_PCI_FIXED) {
0280                         dev_info(&dev->dev, "BAR %d %pR is immovable\n",
0281                              idx, r);
0282                     } else {
0283                         /* We'll assign a new address later */
0284                         pcibios_save_fw_addr(dev,
0285                                 idx, r->start);
0286                         r->end -= r->start;
0287                         r->start = 0;
0288                     }
0289                 }
0290             }
0291         }
0292     if (!pass) {
0293         r = &dev->resource[PCI_ROM_RESOURCE];
0294         if (r->flags & IORESOURCE_ROM_ENABLE) {
0295             /* Turn the ROM off, leave the resource region,
0296              * but keep it unregistered. */
0297             u32 reg;
0298             dev_dbg(&dev->dev, "disabling ROM %pR\n", r);
0299             r->flags &= ~IORESOURCE_ROM_ENABLE;
0300             pci_read_config_dword(dev, dev->rom_base_reg, &reg);
0301             pci_write_config_dword(dev, dev->rom_base_reg,
0302                         reg & ~PCI_ROM_ADDRESS_ENABLE);
0303         }
0304     }
0305 }
0306
0307 static void pcibios_allocate_resources(struct pci_bus *bus, int pass)
0308 {
0309     struct pci_dev *dev;
0310     struct pci_bus *child;
0311
0312     list_for_each_entry(dev, &bus->devices, bus_list) {
0313         pcibios_allocate_dev_resources(dev, pass);
0314
0315         child = dev->subordinate;
0316         if (child)
0317             pcibios_allocate_resources(child, pass);
0318     }
0319 }
0320
0321 static void pcibios_allocate_dev_rom_resource(struct pci_dev *dev)
0322 {
0323     struct resource *r;
0324
0325     /*
0326      * Try to use BIOS settings for ROMs, otherwise let
0327      * pci_assign_unassigned_resources() allocate the new
0328      * addresses.
0329      */
0330     r = &dev->resource[PCI_ROM_RESOURCE];
0331     if (!r->flags || !r->start)
0332         return;
0333     if (r->parent) /* Already allocated */
0334         return;
0335
0336     if (pci_claim_resource(dev, PCI_ROM_RESOURCE) < 0) {
0337         r->end -= r->start;
0338         r->start = 0;
0339     }
0340 }
0341 static void pcibios_allocate_rom_resources(struct pci_bus *bus)
0342 {
0343     struct pci_dev *dev;
0344     struct pci_bus *child;
0345
0346     list_for_each_entry(dev, &bus->devices, bus_list) {
0347         pcibios_allocate_dev_rom_resource(dev);
0348
0349         child = dev->subordinate;
0350         if (child)
0351             pcibios_allocate_rom_resources(child);
0352     }
0353 }
0354
0355 static int __init pcibios_assign_resources(void)
0356 {
0357     struct pci_bus *bus;
0358
0359     if (!(pci_probe & PCI_ASSIGN_ROMS))
0360         list_for_each_entry(bus, &pci_root_buses, node)
0361             pcibios_allocate_rom_resources(bus);
0362
0363     pci_assign_unassigned_resources();
0364     pcibios_fw_addr_list_del();
0365
0366     return 0;
0367 }
0368
0369 /*
0370  * This is an fs_initcall (one below subsys_initcall) in order to reserve
0371  * resources properly.
0372  */
0373 fs_initcall(pcibios_assign_resources);
0374
0375 void pcibios_resource_survey_bus(struct pci_bus *bus)
0376 {
0377     dev_printk(KERN_DEBUG, &bus->dev, "Allocating resources\n");
0378
0379     pcibios_allocate_bus_resources(bus);
0380
0381     pcibios_allocate_resources(bus, 0);
0382     pcibios_allocate_resources(bus, 1);
0383
0384     if (!(pci_probe & PCI_ASSIGN_ROMS))
0385         pcibios_allocate_rom_resources(bus);
0386 }
0387
0388 void __init pcibios_resource_survey(void)
0389 {
0390     struct pci_bus *bus;
0391
0392     DBG("PCI: Allocating resources\n");
0393
0394     list_for_each_entry(bus, &pci_root_buses, node)
0395         pcibios_allocate_bus_resources(bus);
0396
0397     list_for_each_entry(bus, &pci_root_buses, node)
0398         pcibios_allocate_resources(bus, 0);
0399     list_for_each_entry(bus, &pci_root_buses, node)
0400         pcibios_allocate_resources(bus, 1);
0401
0402     e820__reserve_resources_late();
0403     /*
0404      * Insert the IO APIC resources after PCI initialization has
0405      * occurred to handle IO APICS that are mapped in on a BAR in
0406      * PCI space, but before trying to assign unassigned pci res.
0407      */
0408     ioapic_insert_resources();
0409 }