x86/pci/direct.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * direct.c - Low-level direct PCI config space access
0004  */
0005
0006 #include <linux/pci.h>
0007 #include <linux/init.h>
0008 #include <linux/dmi.h>
0009 #include <asm/pci_x86.h>
0010
0011 /*
0012  * Functions for accessing PCI base (first 256 bytes) and extended
0013  * (4096 bytes per PCI function) configuration space with type 1
0014  * accesses.
0015  */
0016
0017 #define PCI_CONF1_ADDRESS(bus, devfn, reg) \
0018     (0x80000000 | ((reg & 0xF00) << 16) | (bus << 16) \
0019     | (devfn << 8) | (reg & 0xFC))
0020
0021 static int pci_conf1_read(unsigned int seg, unsigned int bus,
0022               unsigned int devfn, int reg, int len, u32 *value)
0023 {
0024     unsigned long flags;
0025
0026     if (seg || (bus > 255) || (devfn > 255) || (reg > 4095)) {
0027         *value = -1;
0028         return -EINVAL;
0029     }
0030
0031     raw_spin_lock_irqsave(&pci_config_lock, flags);
0032
0033     outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
0034
0035     switch (len) {
0036     case 1:
0037         *value = inb(0xCFC + (reg & 3));
0038         break;
0039     case 2:
0040         *value = inw(0xCFC + (reg & 2));
0041         break;
0042     case 4:
0043         *value = inl(0xCFC);
0044         break;
0045     }
0046
0047     raw_spin_unlock_irqrestore(&pci_config_lock, flags);
0048
0049     return 0;
0050 }
0051
0052 static int pci_conf1_write(unsigned int seg, unsigned int bus,
0053                unsigned int devfn, int reg, int len, u32 value)
0054 {
0055     unsigned long flags;
0056
0057     if (seg || (bus > 255) || (devfn > 255) || (reg > 4095))
0058         return -EINVAL;
0059
0060     raw_spin_lock_irqsave(&pci_config_lock, flags);
0061
0062     outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
0063
0064     switch (len) {
0065     case 1:
0066         outb((u8)value, 0xCFC + (reg & 3));
0067         break;
0068     case 2:
0069         outw((u16)value, 0xCFC + (reg & 2));
0070         break;
0071     case 4:
0072         outl((u32)value, 0xCFC);
0073         break;
0074     }
0075
0076     raw_spin_unlock_irqrestore(&pci_config_lock, flags);
0077
0078     return 0;
0079 }
0080
0081 #undef PCI_CONF1_ADDRESS
0082
0083 const struct pci_raw_ops pci_direct_conf1 = {
0084     .read =     pci_conf1_read,
0085     .write =    pci_conf1_write,
0086 };
0087
0088
0089 /*
0090  * Functions for accessing PCI configuration space with type 2 accesses
0091  */
0092
0093 #define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg)
0094
0095 static int pci_conf2_read(unsigned int seg, unsigned int bus,
0096               unsigned int devfn, int reg, int len, u32 *value)
0097 {
0098     unsigned long flags;
0099     int dev, fn;
0100
0101     WARN_ON(seg);
0102     if ((bus > 255) || (devfn > 255) || (reg > 255)) {
0103         *value = -1;
0104         return -EINVAL;
0105     }
0106
0107     dev = PCI_SLOT(devfn);
0108     fn = PCI_FUNC(devfn);
0109
0110     if (dev & 0x10)
0111         return PCIBIOS_DEVICE_NOT_FOUND;
0112
0113     raw_spin_lock_irqsave(&pci_config_lock, flags);
0114
0115     outb((u8)(0xF0 | (fn << 1)), 0xCF8);
0116     outb((u8)bus, 0xCFA);
0117
0118     switch (len) {
0119     case 1:
0120         *value = inb(PCI_CONF2_ADDRESS(dev, reg));
0121         break;
0122     case 2:
0123         *value = inw(PCI_CONF2_ADDRESS(dev, reg));
0124         break;
0125     case 4:
0126         *value = inl(PCI_CONF2_ADDRESS(dev, reg));
0127         break;
0128     }
0129
0130     outb(0, 0xCF8);
0131
0132     raw_spin_unlock_irqrestore(&pci_config_lock, flags);
0133
0134     return 0;
0135 }
0136
0137 static int pci_conf2_write(unsigned int seg, unsigned int bus,
0138                unsigned int devfn, int reg, int len, u32 value)
0139 {
0140     unsigned long flags;
0141     int dev, fn;
0142
0143     WARN_ON(seg);
0144     if ((bus > 255) || (devfn > 255) || (reg > 255))
0145         return -EINVAL;
0146
0147     dev = PCI_SLOT(devfn);
0148     fn = PCI_FUNC(devfn);
0149
0150     if (dev & 0x10)
0151         return PCIBIOS_DEVICE_NOT_FOUND;
0152
0153     raw_spin_lock_irqsave(&pci_config_lock, flags);
0154
0155     outb((u8)(0xF0 | (fn << 1)), 0xCF8);
0156     outb((u8)bus, 0xCFA);
0157
0158     switch (len) {
0159     case 1:
0160         outb((u8)value, PCI_CONF2_ADDRESS(dev, reg));
0161         break;
0162     case 2:
0163         outw((u16)value, PCI_CONF2_ADDRESS(dev, reg));
0164         break;
0165     case 4:
0166         outl((u32)value, PCI_CONF2_ADDRESS(dev, reg));
0167         break;
0168     }
0169
0170     outb(0, 0xCF8);
0171
0172     raw_spin_unlock_irqrestore(&pci_config_lock, flags);
0173
0174     return 0;
0175 }
0176
0177 #undef PCI_CONF2_ADDRESS
0178
0179 static const struct pci_raw_ops pci_direct_conf2 = {
0180     .read =     pci_conf2_read,
0181     .write =    pci_conf2_write,
0182 };
0183
0184
0185 /*
0186  * Before we decide to use direct hardware access mechanisms, we try to do some
0187  * trivial checks to ensure it at least _seems_ to be working -- we just test
0188  * whether bus 00 contains a host bridge (this is similar to checking
0189  * techniques used in XFree86, but ours should be more reliable since we
0190  * attempt to make use of direct access hints provided by the PCI BIOS).
0191  *
0192  * This should be close to trivial, but it isn't, because there are buggy
0193  * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
0194  */
0195 static int __init pci_sanity_check(const struct pci_raw_ops *o)
0196 {
0197     u32 x = 0;
0198     int devfn;
0199
0200     if (pci_probe & PCI_NO_CHECKS)
0201         return 1;
0202     /* Assume Type 1 works for newer systems.
0203        This handles machines that don't have anything on PCI Bus 0. */
0204     if (dmi_get_bios_year() >= 2001)
0205         return 1;
0206
0207     for (devfn = 0; devfn < 0x100; devfn++) {
0208         if (o->read(0, 0, devfn, PCI_CLASS_DEVICE, 2, &x))
0209             continue;
0210         if (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)
0211             return 1;
0212
0213         if (o->read(0, 0, devfn, PCI_VENDOR_ID, 2, &x))
0214             continue;
0215         if (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)
0216             return 1;
0217     }
0218
0219     DBG(KERN_WARNING "PCI: Sanity check failed\n");
0220     return 0;
0221 }
0222
0223 static int __init pci_check_type1(void)
0224 {
0225     unsigned long flags;
0226     unsigned int tmp;
0227     int works = 0;
0228
0229     local_irq_save(flags);
0230
0231     outb(0x01, 0xCFB);
0232     tmp = inl(0xCF8);
0233     outl(0x80000000, 0xCF8);
0234     if (inl(0xCF8) == 0x80000000 && pci_sanity_check(&pci_direct_conf1)) {
0235         works = 1;
0236     }
0237     outl(tmp, 0xCF8);
0238     local_irq_restore(flags);
0239
0240     return works;
0241 }
0242
0243 static int __init pci_check_type2(void)
0244 {
0245     unsigned long flags;
0246     int works = 0;
0247
0248     local_irq_save(flags);
0249
0250     outb(0x00, 0xCFB);
0251     outb(0x00, 0xCF8);
0252     outb(0x00, 0xCFA);
0253     if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00 &&
0254         pci_sanity_check(&pci_direct_conf2)) {
0255         works = 1;
0256     }
0257
0258     local_irq_restore(flags);
0259
0260     return works;
0261 }
0262
0263 void __init pci_direct_init(int type)
0264 {
0265     if (type == 0)
0266         return;
0267     printk(KERN_INFO "PCI: Using configuration type %d for base access\n",
0268          type);
0269     if (type == 1) {
0270         raw_pci_ops = &pci_direct_conf1;
0271         if (raw_pci_ext_ops)
0272             return;
0273         if (!(pci_probe & PCI_HAS_IO_ECS))
0274             return;
0275         printk(KERN_INFO "PCI: Using configuration type 1 "
0276                "for extended access\n");
0277         raw_pci_ext_ops = &pci_direct_conf1;
0278         return;
0279     }
0280     raw_pci_ops = &pci_direct_conf2;
0281 }
0282
0283 int __init pci_direct_probe(void)
0284 {
0285     if ((pci_probe & PCI_PROBE_CONF1) == 0)
0286         goto type2;
0287     if (!request_region(0xCF8, 8, "PCI conf1"))
0288         goto type2;
0289
0290     if (pci_check_type1()) {
0291         raw_pci_ops = &pci_direct_conf1;
0292         port_cf9_safe = true;
0293         return 1;
0294     }
0295     release_region(0xCF8, 8);
0296
0297  type2:
0298     if ((pci_probe & PCI_PROBE_CONF2) == 0)
0299         return 0;
0300     if (!request_region(0xCF8, 4, "PCI conf2"))
0301         return 0;
0302     if (!request_region(0xC000, 0x1000, "PCI conf2"))
0303         goto fail2;
0304
0305     if (pci_check_type2()) {
0306         raw_pci_ops = &pci_direct_conf2;
0307         port_cf9_safe = true;
0308         return 2;
0309     }
0310
0311     release_region(0xC000, 0x1000);
0312  fail2:
0313     release_region(0xCF8, 4);
0314     return 0;
0315 }