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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Copyright(c) 2010 Intel Corporation. All rights reserved.
0004  *
0005  *  Contact Information:
0006  *    Intel Corporation
0007  *    2200 Mission College Blvd.
0008  *    Santa Clara, CA  97052
0009  *
0010  * This provides access methods for PCI registers that mis-behave on
0011  * the CE4100. Each register can be assigned a private init, read and
0012  * write routine. The exception to this is the bridge device.  The
0013  * bridge device is the only device on bus zero (0) that requires any
0014  * fixup so it is a special case ATM
0015  */
0016 
0017 #include <linux/kernel.h>
0018 #include <linux/pci.h>
0019 #include <linux/init.h>
0020 
0021 #include <asm/ce4100.h>
0022 #include <asm/pci_x86.h>
0023 
0024 struct sim_reg {
0025     u32 value;
0026     u32 mask;
0027 };
0028 
0029 struct sim_dev_reg {
0030     int dev_func;
0031     int reg;
0032     void (*init)(struct sim_dev_reg *reg);
0033     void (*read)(struct sim_dev_reg *reg, u32 *value);
0034     void (*write)(struct sim_dev_reg *reg, u32 value);
0035     struct sim_reg sim_reg;
0036 };
0037 
0038 struct sim_reg_op {
0039     void (*init)(struct sim_dev_reg *reg);
0040     void (*read)(struct sim_dev_reg *reg, u32 value);
0041     void (*write)(struct sim_dev_reg *reg, u32 value);
0042 };
0043 
0044 #define MB (1024 * 1024)
0045 #define KB (1024)
0046 #define SIZE_TO_MASK(size) (~(size - 1))
0047 
0048 #define DEFINE_REG(device, func, offset, size, init_op, read_op, write_op)\
0049 { PCI_DEVFN(device, func), offset, init_op, read_op, write_op,\
0050     {0, SIZE_TO_MASK(size)} },
0051 
0052 /*
0053  * All read/write functions are called with pci_config_lock held.
0054  */
0055 static void reg_init(struct sim_dev_reg *reg)
0056 {
0057     pci_direct_conf1.read(0, 1, reg->dev_func, reg->reg, 4,
0058                   &reg->sim_reg.value);
0059 }
0060 
0061 static void reg_read(struct sim_dev_reg *reg, u32 *value)
0062 {
0063     *value = reg->sim_reg.value;
0064 }
0065 
0066 static void reg_write(struct sim_dev_reg *reg, u32 value)
0067 {
0068     reg->sim_reg.value = (value & reg->sim_reg.mask) |
0069         (reg->sim_reg.value & ~reg->sim_reg.mask);
0070 }
0071 
0072 static void sata_reg_init(struct sim_dev_reg *reg)
0073 {
0074     pci_direct_conf1.read(0, 1, PCI_DEVFN(14, 0), 0x10, 4,
0075                   &reg->sim_reg.value);
0076     reg->sim_reg.value += 0x400;
0077 }
0078 
0079 static void ehci_reg_read(struct sim_dev_reg *reg, u32 *value)
0080 {
0081     reg_read(reg, value);
0082     if (*value != reg->sim_reg.mask)
0083         *value |= 0x100;
0084 }
0085 
0086 void sata_revid_init(struct sim_dev_reg *reg)
0087 {
0088     reg->sim_reg.value = 0x01060100;
0089     reg->sim_reg.mask = 0;
0090 }
0091 
0092 static void sata_revid_read(struct sim_dev_reg *reg, u32 *value)
0093 {
0094     reg_read(reg, value);
0095 }
0096 
0097 static void reg_noirq_read(struct sim_dev_reg *reg, u32 *value)
0098 {
0099     /* force interrupt pin value to 0 */
0100     *value = reg->sim_reg.value & 0xfff00ff;
0101 }
0102 
0103 static struct sim_dev_reg bus1_fixups[] = {
0104     DEFINE_REG(2, 0, 0x10, (16*MB), reg_init, reg_read, reg_write)
0105     DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write)
0106     DEFINE_REG(2, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
0107     DEFINE_REG(3, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
0108     DEFINE_REG(4, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
0109     DEFINE_REG(4, 1, 0x10, (128*KB), reg_init, reg_read, reg_write)
0110     DEFINE_REG(6, 0, 0x10, (512*KB), reg_init, reg_read, reg_write)
0111     DEFINE_REG(6, 1, 0x10, (512*KB), reg_init, reg_read, reg_write)
0112     DEFINE_REG(6, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
0113     DEFINE_REG(8, 0, 0x10, (1*MB), reg_init, reg_read, reg_write)
0114     DEFINE_REG(8, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
0115     DEFINE_REG(8, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
0116     DEFINE_REG(9, 0, 0x10 , (1*MB), reg_init, reg_read, reg_write)
0117     DEFINE_REG(9, 0, 0x14, (64*KB), reg_init, reg_read, reg_write)
0118     DEFINE_REG(10, 0, 0x10, (256), reg_init, reg_read, reg_write)
0119     DEFINE_REG(10, 0, 0x14, (256*MB), reg_init, reg_read, reg_write)
0120     DEFINE_REG(11, 0, 0x10, (256), reg_init, reg_read, reg_write)
0121     DEFINE_REG(11, 0, 0x14, (256), reg_init, reg_read, reg_write)
0122     DEFINE_REG(11, 1, 0x10, (256), reg_init, reg_read, reg_write)
0123     DEFINE_REG(11, 2, 0x10, (256), reg_init, reg_read, reg_write)
0124     DEFINE_REG(11, 2, 0x14, (256), reg_init, reg_read, reg_write)
0125     DEFINE_REG(11, 2, 0x18, (256), reg_init, reg_read, reg_write)
0126     DEFINE_REG(11, 3, 0x10, (256), reg_init, reg_read, reg_write)
0127     DEFINE_REG(11, 3, 0x14, (256), reg_init, reg_read, reg_write)
0128     DEFINE_REG(11, 4, 0x10, (256), reg_init, reg_read, reg_write)
0129     DEFINE_REG(11, 5, 0x10, (64*KB), reg_init, reg_read, reg_write)
0130     DEFINE_REG(11, 6, 0x10, (256), reg_init, reg_read, reg_write)
0131     DEFINE_REG(11, 7, 0x10, (64*KB), reg_init, reg_read, reg_write)
0132     DEFINE_REG(11, 7, 0x3c, 256, reg_init, reg_noirq_read, reg_write)
0133     DEFINE_REG(12, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
0134     DEFINE_REG(12, 0, 0x14, (256), reg_init, reg_read, reg_write)
0135     DEFINE_REG(12, 1, 0x10, (1024), reg_init, reg_read, reg_write)
0136     DEFINE_REG(13, 0, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write)
0137     DEFINE_REG(13, 1, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write)
0138     DEFINE_REG(14, 0, 0x8,  0, sata_revid_init, sata_revid_read, 0)
0139     DEFINE_REG(14, 0, 0x10, 0, reg_init, reg_read, reg_write)
0140     DEFINE_REG(14, 0, 0x14, 0, reg_init, reg_read, reg_write)
0141     DEFINE_REG(14, 0, 0x18, 0, reg_init, reg_read, reg_write)
0142     DEFINE_REG(14, 0, 0x1C, 0, reg_init, reg_read, reg_write)
0143     DEFINE_REG(14, 0, 0x20, 0, reg_init, reg_read, reg_write)
0144     DEFINE_REG(14, 0, 0x24, (0x200), sata_reg_init, reg_read, reg_write)
0145     DEFINE_REG(15, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
0146     DEFINE_REG(15, 0, 0x14, (64*KB), reg_init, reg_read, reg_write)
0147     DEFINE_REG(16, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
0148     DEFINE_REG(16, 0, 0x14, (64*MB), reg_init, reg_read, reg_write)
0149     DEFINE_REG(16, 0, 0x18, (64*MB), reg_init, reg_read, reg_write)
0150     DEFINE_REG(16, 0, 0x3c, 256, reg_init, reg_noirq_read, reg_write)
0151     DEFINE_REG(17, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
0152     DEFINE_REG(18, 0, 0x10, (1*KB), reg_init, reg_read, reg_write)
0153     DEFINE_REG(18, 0, 0x3c, 256, reg_init, reg_noirq_read, reg_write)
0154 };
0155 
0156 static void __init init_sim_regs(void)
0157 {
0158     int i;
0159 
0160     for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
0161         if (bus1_fixups[i].init)
0162             bus1_fixups[i].init(&bus1_fixups[i]);
0163     }
0164 }
0165 
0166 static inline void extract_bytes(u32 *value, int reg, int len)
0167 {
0168     uint32_t mask;
0169 
0170     *value >>= ((reg & 3) * 8);
0171     mask = 0xFFFFFFFF >> ((4 - len) * 8);
0172     *value &= mask;
0173 }
0174 
0175 int bridge_read(unsigned int devfn, int reg, int len, u32 *value)
0176 {
0177     u32 av_bridge_base, av_bridge_limit;
0178     int retval = 0;
0179 
0180     switch (reg) {
0181     /* Make BARs appear to not request any memory. */
0182     case PCI_BASE_ADDRESS_0:
0183     case PCI_BASE_ADDRESS_0 + 1:
0184     case PCI_BASE_ADDRESS_0 + 2:
0185     case PCI_BASE_ADDRESS_0 + 3:
0186         *value = 0;
0187         break;
0188 
0189         /* Since subordinate bus number register is hardwired
0190          * to zero and read only, so do the simulation.
0191          */
0192     case PCI_PRIMARY_BUS:
0193         if (len == 4)
0194             *value = 0x00010100;
0195         break;
0196 
0197     case PCI_SUBORDINATE_BUS:
0198         *value = 1;
0199         break;
0200 
0201     case PCI_MEMORY_BASE:
0202     case PCI_MEMORY_LIMIT:
0203         /* Get the A/V bridge base address. */
0204         pci_direct_conf1.read(0, 0, devfn,
0205                 PCI_BASE_ADDRESS_0, 4, &av_bridge_base);
0206 
0207         av_bridge_limit = av_bridge_base + (512*MB - 1);
0208         av_bridge_limit >>= 16;
0209         av_bridge_limit &= 0xFFF0;
0210 
0211         av_bridge_base >>= 16;
0212         av_bridge_base &= 0xFFF0;
0213 
0214         if (reg == PCI_MEMORY_LIMIT)
0215             *value = av_bridge_limit;
0216         else if (len == 2)
0217             *value = av_bridge_base;
0218         else
0219             *value = (av_bridge_limit << 16) | av_bridge_base;
0220         break;
0221         /* Make prefetchable memory limit smaller than prefetchable
0222          * memory base, so not claim prefetchable memory space.
0223          */
0224     case PCI_PREF_MEMORY_BASE:
0225         *value = 0xFFF0;
0226         break;
0227     case PCI_PREF_MEMORY_LIMIT:
0228         *value = 0x0;
0229         break;
0230         /* Make IO limit smaller than IO base, so not claim IO space. */
0231     case PCI_IO_BASE:
0232         *value = 0xF0;
0233         break;
0234     case PCI_IO_LIMIT:
0235         *value = 0;
0236         break;
0237     default:
0238         retval = 1;
0239     }
0240     return retval;
0241 }
0242 
0243 static int ce4100_bus1_read(unsigned int devfn, int reg, int len, u32 *value)
0244 {
0245     unsigned long flags;
0246     int i;
0247 
0248     for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
0249         if (bus1_fixups[i].dev_func == devfn &&
0250             bus1_fixups[i].reg == (reg & ~3) &&
0251             bus1_fixups[i].read) {
0252 
0253             raw_spin_lock_irqsave(&pci_config_lock, flags);
0254             bus1_fixups[i].read(&(bus1_fixups[i]), value);
0255             raw_spin_unlock_irqrestore(&pci_config_lock, flags);
0256             extract_bytes(value, reg, len);
0257             return 0;
0258         }
0259     }
0260     return -1;
0261 }
0262 
0263 static int ce4100_conf_read(unsigned int seg, unsigned int bus,
0264                 unsigned int devfn, int reg, int len, u32 *value)
0265 {
0266     WARN_ON(seg);
0267 
0268     if (bus == 1 && !ce4100_bus1_read(devfn, reg, len, value))
0269         return 0;
0270 
0271     if (bus == 0 && (PCI_DEVFN(1, 0) == devfn) &&
0272         !bridge_read(devfn, reg, len, value))
0273         return 0;
0274 
0275     return pci_direct_conf1.read(seg, bus, devfn, reg, len, value);
0276 }
0277 
0278 static int ce4100_bus1_write(unsigned int devfn, int reg, int len, u32 value)
0279 {
0280     unsigned long flags;
0281     int i;
0282 
0283     for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
0284         if (bus1_fixups[i].dev_func == devfn &&
0285             bus1_fixups[i].reg == (reg & ~3) &&
0286             bus1_fixups[i].write) {
0287 
0288             raw_spin_lock_irqsave(&pci_config_lock, flags);
0289             bus1_fixups[i].write(&(bus1_fixups[i]), value);
0290             raw_spin_unlock_irqrestore(&pci_config_lock, flags);
0291             return 0;
0292         }
0293     }
0294     return -1;
0295 }
0296 
0297 static int ce4100_conf_write(unsigned int seg, unsigned int bus,
0298                  unsigned int devfn, int reg, int len, u32 value)
0299 {
0300     WARN_ON(seg);
0301 
0302     if (bus == 1 && !ce4100_bus1_write(devfn, reg, len, value))
0303         return 0;
0304 
0305     /* Discard writes to A/V bridge BAR. */
0306     if (bus == 0 && PCI_DEVFN(1, 0) == devfn &&
0307         ((reg & ~3) == PCI_BASE_ADDRESS_0))
0308         return 0;
0309 
0310     return pci_direct_conf1.write(seg, bus, devfn, reg, len, value);
0311 }
0312 
0313 static const struct pci_raw_ops ce4100_pci_conf = {
0314     .read   = ce4100_conf_read,
0315     .write  = ce4100_conf_write,
0316 };
0317 
0318 int __init ce4100_pci_init(void)
0319 {
0320     init_sim_regs();
0321     raw_pci_ops = &ce4100_pci_conf;
0322     /* Indicate caller that it should invoke pci_legacy_init() */
0323     return 1;
0324 }
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