x86/pci/broadcom_bus.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Read address ranges from a Broadcom CNB20LE Host Bridge
0004  *
0005  * Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu>
0006  */
0007
0008 #include <linux/acpi.h>
0009 #include <linux/delay.h>
0010 #include <linux/dmi.h>
0011 #include <linux/pci.h>
0012 #include <linux/init.h>
0013 #include <asm/pci_x86.h>
0014 #include <asm/pci-direct.h>
0015
0016 #include "bus_numa.h"
0017
0018 static void __init cnb20le_res(u8 bus, u8 slot, u8 func)
0019 {
0020     struct pci_root_info *info;
0021     struct pci_root_res *root_res;
0022     struct resource res;
0023     u16 word1, word2;
0024     u8 fbus, lbus;
0025
0026     /* read the PCI bus numbers */
0027     fbus = read_pci_config_byte(bus, slot, func, 0x44);
0028     lbus = read_pci_config_byte(bus, slot, func, 0x45);
0029     info = alloc_pci_root_info(fbus, lbus, 0, 0);
0030
0031     /*
0032      * Add the legacy IDE ports on bus 0
0033      *
0034      * These do not exist anywhere in the bridge registers, AFAICT. I do
0035      * not have the datasheet, so this is the best I can do.
0036      */
0037     if (fbus == 0) {
0038         update_res(info, 0x01f0, 0x01f7, IORESOURCE_IO, 0);
0039         update_res(info, 0x03f6, 0x03f6, IORESOURCE_IO, 0);
0040         update_res(info, 0x0170, 0x0177, IORESOURCE_IO, 0);
0041         update_res(info, 0x0376, 0x0376, IORESOURCE_IO, 0);
0042         update_res(info, 0xffa0, 0xffaf, IORESOURCE_IO, 0);
0043     }
0044
0045     /* read the non-prefetchable memory window */
0046     word1 = read_pci_config_16(bus, slot, func, 0xc0);
0047     word2 = read_pci_config_16(bus, slot, func, 0xc2);
0048     if (word1 != word2) {
0049         res.start = ((resource_size_t) word1 << 16) | 0x0000;
0050         res.end   = ((resource_size_t) word2 << 16) | 0xffff;
0051         res.flags = IORESOURCE_MEM;
0052         update_res(info, res.start, res.end, res.flags, 0);
0053     }
0054
0055     /* read the prefetchable memory window */
0056     word1 = read_pci_config_16(bus, slot, func, 0xc4);
0057     word2 = read_pci_config_16(bus, slot, func, 0xc6);
0058     if (word1 != word2) {
0059         res.start = ((resource_size_t) word1 << 16) | 0x0000;
0060         res.end   = ((resource_size_t) word2 << 16) | 0xffff;
0061         res.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
0062         update_res(info, res.start, res.end, res.flags, 0);
0063     }
0064
0065     /* read the IO port window */
0066     word1 = read_pci_config_16(bus, slot, func, 0xd0);
0067     word2 = read_pci_config_16(bus, slot, func, 0xd2);
0068     if (word1 != word2) {
0069         res.start = word1;
0070         res.end   = word2;
0071         res.flags = IORESOURCE_IO;
0072         update_res(info, res.start, res.end, res.flags, 0);
0073     }
0074
0075     /* print information about this host bridge */
0076     res.start = fbus;
0077     res.end   = lbus;
0078     res.flags = IORESOURCE_BUS;
0079     printk(KERN_INFO "CNB20LE PCI Host Bridge (domain 0000 %pR)\n", &res);
0080
0081     list_for_each_entry(root_res, &info->resources, list)
0082         printk(KERN_INFO "host bridge window %pR\n", &root_res->res);
0083 }
0084
0085 static int __init broadcom_postcore_init(void)
0086 {
0087     u8 bus = 0, slot = 0;
0088     u32 id;
0089     u16 vendor, device;
0090
0091 #ifdef CONFIG_ACPI
0092     /*
0093      * We should get host bridge information from ACPI unless the BIOS
0094      * doesn't support it.
0095      */
0096     if (!acpi_disabled && acpi_os_get_root_pointer())
0097         return 0;
0098 #endif
0099
0100     id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
0101     vendor = id & 0xffff;
0102     device = (id >> 16) & 0xffff;
0103
0104     if (vendor == PCI_VENDOR_ID_SERVERWORKS &&
0105         device == PCI_DEVICE_ID_SERVERWORKS_LE) {
0106         cnb20le_res(bus, slot, 0);
0107         cnb20le_res(bus, slot, 1);
0108     }
0109     return 0;
0110 }
0111
0112 postcore_initcall(broadcom_postcore_init);