kvm/vmx/vmcs.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __KVM_X86_VMX_VMCS_H
0003 #define __KVM_X86_VMX_VMCS_H
0004
0005 #include <linux/ktime.h>
0006 #include <linux/list.h>
0007 #include <linux/nospec.h>
0008
0009 #include <asm/kvm.h>
0010 #include <asm/vmx.h>
0011
0012 #include "capabilities.h"
0013
0014 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
0015
0016 struct vmcs_hdr {
0017     u32 revision_id:31;
0018     u32 shadow_vmcs:1;
0019 };
0020
0021 struct vmcs {
0022     struct vmcs_hdr hdr;
0023     u32 abort;
0024     char data[];
0025 };
0026
0027 DECLARE_PER_CPU(struct vmcs *, current_vmcs);
0028
0029 /*
0030  * vmcs_host_state tracks registers that are loaded from the VMCS on VMEXIT
0031  * and whose values change infrequently, but are not constant.  I.e. this is
0032  * used as a write-through cache of the corresponding VMCS fields.
0033  */
0034 struct vmcs_host_state {
0035     unsigned long cr3;  /* May not match real cr3 */
0036     unsigned long cr4;  /* May not match real cr4 */
0037     unsigned long gs_base;
0038     unsigned long fs_base;
0039     unsigned long rsp;
0040
0041     u16           fs_sel, gs_sel, ldt_sel;
0042 #ifdef CONFIG_X86_64
0043     u16           ds_sel, es_sel;
0044 #endif
0045 };
0046
0047 struct vmcs_controls_shadow {
0048     u32 vm_entry;
0049     u32 vm_exit;
0050     u32 pin;
0051     u32 exec;
0052     u32 secondary_exec;
0053     u64 tertiary_exec;
0054 };
0055
0056 /*
0057  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
0058  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
0059  * loaded on this CPU (so we can clear them if the CPU goes down).
0060  */
0061 struct loaded_vmcs {
0062     struct vmcs *vmcs;
0063     struct vmcs *shadow_vmcs;
0064     int cpu;
0065     bool launched;
0066     bool nmi_known_unmasked;
0067     bool hv_timer_soft_disabled;
0068     /* Support for vnmi-less CPUs */
0069     int soft_vnmi_blocked;
0070     ktime_t entry_time;
0071     s64 vnmi_blocked_time;
0072     unsigned long *msr_bitmap;
0073     struct list_head loaded_vmcss_on_cpu_link;
0074     struct vmcs_host_state host_state;
0075     struct vmcs_controls_shadow controls_shadow;
0076 };
0077
0078 static inline bool is_intr_type(u32 intr_info, u32 type)
0079 {
0080     const u32 mask = INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK;
0081
0082     return (intr_info & mask) == (INTR_INFO_VALID_MASK | type);
0083 }
0084
0085 static inline bool is_intr_type_n(u32 intr_info, u32 type, u8 vector)
0086 {
0087     const u32 mask = INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK |
0088              INTR_INFO_VECTOR_MASK;
0089
0090     return (intr_info & mask) == (INTR_INFO_VALID_MASK | type | vector);
0091 }
0092
0093 static inline bool is_exception_n(u32 intr_info, u8 vector)
0094 {
0095     return is_intr_type_n(intr_info, INTR_TYPE_HARD_EXCEPTION, vector);
0096 }
0097
0098 static inline bool is_debug(u32 intr_info)
0099 {
0100     return is_exception_n(intr_info, DB_VECTOR);
0101 }
0102
0103 static inline bool is_breakpoint(u32 intr_info)
0104 {
0105     return is_exception_n(intr_info, BP_VECTOR);
0106 }
0107
0108 static inline bool is_double_fault(u32 intr_info)
0109 {
0110     return is_exception_n(intr_info, DF_VECTOR);
0111 }
0112
0113 static inline bool is_page_fault(u32 intr_info)
0114 {
0115     return is_exception_n(intr_info, PF_VECTOR);
0116 }
0117
0118 static inline bool is_invalid_opcode(u32 intr_info)
0119 {
0120     return is_exception_n(intr_info, UD_VECTOR);
0121 }
0122
0123 static inline bool is_gp_fault(u32 intr_info)
0124 {
0125     return is_exception_n(intr_info, GP_VECTOR);
0126 }
0127
0128 static inline bool is_alignment_check(u32 intr_info)
0129 {
0130     return is_exception_n(intr_info, AC_VECTOR);
0131 }
0132
0133 static inline bool is_machine_check(u32 intr_info)
0134 {
0135     return is_exception_n(intr_info, MC_VECTOR);
0136 }
0137
0138 static inline bool is_nm_fault(u32 intr_info)
0139 {
0140     return is_exception_n(intr_info, NM_VECTOR);
0141 }
0142
0143 /* Undocumented: icebp/int1 */
0144 static inline bool is_icebp(u32 intr_info)
0145 {
0146     return is_intr_type(intr_info, INTR_TYPE_PRIV_SW_EXCEPTION);
0147 }
0148
0149 static inline bool is_nmi(u32 intr_info)
0150 {
0151     return is_intr_type(intr_info, INTR_TYPE_NMI_INTR);
0152 }
0153
0154 static inline bool is_external_intr(u32 intr_info)
0155 {
0156     return is_intr_type(intr_info, INTR_TYPE_EXT_INTR);
0157 }
0158
0159 static inline bool is_exception_with_error_code(u32 intr_info)
0160 {
0161     const u32 mask = INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK;
0162
0163     return (intr_info & mask) == mask;
0164 }
0165
0166 enum vmcs_field_width {
0167     VMCS_FIELD_WIDTH_U16 = 0,
0168     VMCS_FIELD_WIDTH_U64 = 1,
0169     VMCS_FIELD_WIDTH_U32 = 2,
0170     VMCS_FIELD_WIDTH_NATURAL_WIDTH = 3
0171 };
0172
0173 static inline int vmcs_field_width(unsigned long field)
0174 {
0175     if (0x1 & field)    /* the *_HIGH fields are all 32 bit */
0176         return VMCS_FIELD_WIDTH_U32;
0177     return (field >> 13) & 0x3;
0178 }
0179
0180 static inline int vmcs_field_readonly(unsigned long field)
0181 {
0182     return (((field >> 10) & 0x3) == 1);
0183 }
0184
0185 #define VMCS_FIELD_INDEX_SHIFT      (1)
0186 #define VMCS_FIELD_INDEX_MASK       GENMASK(9, 1)
0187
0188 static inline unsigned int vmcs_field_index(unsigned long field)
0189 {
0190     return (field & VMCS_FIELD_INDEX_MASK) >> VMCS_FIELD_INDEX_SHIFT;
0191 }
0192
0193 #endif /* __KVM_X86_VMX_VMCS_H */