x86/kvm/mmu.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __KVM_X86_MMU_H
0003 #define __KVM_X86_MMU_H
0004
0005 #include <linux/kvm_host.h>
0006 #include "kvm_cache_regs.h"
0007 #include "cpuid.h"
0008
0009 extern bool __read_mostly enable_mmio_caching;
0010
0011 #define PT_WRITABLE_SHIFT 1
0012 #define PT_USER_SHIFT 2
0013
0014 #define PT_PRESENT_MASK (1ULL << 0)
0015 #define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
0016 #define PT_USER_MASK (1ULL << PT_USER_SHIFT)
0017 #define PT_PWT_MASK (1ULL << 3)
0018 #define PT_PCD_MASK (1ULL << 4)
0019 #define PT_ACCESSED_SHIFT 5
0020 #define PT_ACCESSED_MASK (1ULL << PT_ACCESSED_SHIFT)
0021 #define PT_DIRTY_SHIFT 6
0022 #define PT_DIRTY_MASK (1ULL << PT_DIRTY_SHIFT)
0023 #define PT_PAGE_SIZE_SHIFT 7
0024 #define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)
0025 #define PT_PAT_MASK (1ULL << 7)
0026 #define PT_GLOBAL_MASK (1ULL << 8)
0027 #define PT64_NX_SHIFT 63
0028 #define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
0029
0030 #define PT_PAT_SHIFT 7
0031 #define PT_DIR_PAT_SHIFT 12
0032 #define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
0033
0034 #define PT64_ROOT_5LEVEL 5
0035 #define PT64_ROOT_4LEVEL 4
0036 #define PT32_ROOT_LEVEL 2
0037 #define PT32E_ROOT_LEVEL 3
0038
0039 #define KVM_MMU_CR4_ROLE_BITS (X86_CR4_PSE | X86_CR4_PAE | X86_CR4_LA57 | \
0040                    X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE)
0041
0042 #define KVM_MMU_CR0_ROLE_BITS (X86_CR0_PG | X86_CR0_WP)
0043 #define KVM_MMU_EFER_ROLE_BITS (EFER_LME | EFER_NX)
0044
0045 static __always_inline u64 rsvd_bits(int s, int e)
0046 {
0047     BUILD_BUG_ON(__builtin_constant_p(e) && __builtin_constant_p(s) && e < s);
0048
0049     if (__builtin_constant_p(e))
0050         BUILD_BUG_ON(e > 63);
0051     else
0052         e &= 63;
0053
0054     if (e < s)
0055         return 0;
0056
0057     return ((2ULL << (e - s)) - 1) << s;
0058 }
0059
0060 /*
0061  * The number of non-reserved physical address bits irrespective of features
0062  * that repurpose legal bits, e.g. MKTME.
0063  */
0064 extern u8 __read_mostly shadow_phys_bits;
0065
0066 static inline gfn_t kvm_mmu_max_gfn(void)
0067 {
0068     /*
0069      * Note that this uses the host MAXPHYADDR, not the guest's.
0070      * EPT/NPT cannot support GPAs that would exceed host.MAXPHYADDR;
0071      * assuming KVM is running on bare metal, guest accesses beyond
0072      * host.MAXPHYADDR will hit a #PF(RSVD) and never cause a vmexit
0073      * (either EPT Violation/Misconfig or #NPF), and so KVM will never
0074      * install a SPTE for such addresses.  If KVM is running as a VM
0075      * itself, on the other hand, it might see a MAXPHYADDR that is less
0076      * than hardware's real MAXPHYADDR.  Using the host MAXPHYADDR
0077      * disallows such SPTEs entirely and simplifies the TDP MMU.
0078      */
0079     int max_gpa_bits = likely(tdp_enabled) ? shadow_phys_bits : 52;
0080
0081     return (1ULL << (max_gpa_bits - PAGE_SHIFT)) - 1;
0082 }
0083
0084 static inline u8 kvm_get_shadow_phys_bits(void)
0085 {
0086     /*
0087      * boot_cpu_data.x86_phys_bits is reduced when MKTME or SME are detected
0088      * in CPU detection code, but the processor treats those reduced bits as
0089      * 'keyID' thus they are not reserved bits. Therefore KVM needs to look at
0090      * the physical address bits reported by CPUID.
0091      */
0092     if (likely(boot_cpu_data.extended_cpuid_level >= 0x80000008))
0093         return cpuid_eax(0x80000008) & 0xff;
0094
0095     /*
0096      * Quite weird to have VMX or SVM but not MAXPHYADDR; probably a VM with
0097      * custom CPUID.  Proceed with whatever the kernel found since these features
0098      * aren't virtualizable (SME/SEV also require CPUIDs higher than 0x80000008).
0099      */
0100     return boot_cpu_data.x86_phys_bits;
0101 }
0102
0103 void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask);
0104 void kvm_mmu_set_me_spte_mask(u64 me_value, u64 me_mask);
0105 void kvm_mmu_set_ept_masks(bool has_ad_bits, bool has_exec_only);
0106
0107 void kvm_init_mmu(struct kvm_vcpu *vcpu);
0108 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
0109                  unsigned long cr4, u64 efer, gpa_t nested_cr3);
0110 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
0111                  int huge_page_level, bool accessed_dirty,
0112                  gpa_t new_eptp);
0113 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu);
0114 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
0115                 u64 fault_address, char *insn, int insn_len);
0116
0117 int kvm_mmu_load(struct kvm_vcpu *vcpu);
0118 void kvm_mmu_unload(struct kvm_vcpu *vcpu);
0119 void kvm_mmu_free_obsolete_roots(struct kvm_vcpu *vcpu);
0120 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu);
0121 void kvm_mmu_sync_prev_roots(struct kvm_vcpu *vcpu);
0122
0123 static inline int kvm_mmu_reload(struct kvm_vcpu *vcpu)
0124 {
0125     if (likely(vcpu->arch.mmu->root.hpa != INVALID_PAGE))
0126         return 0;
0127
0128     return kvm_mmu_load(vcpu);
0129 }
0130
0131 static inline unsigned long kvm_get_pcid(struct kvm_vcpu *vcpu, gpa_t cr3)
0132 {
0133     BUILD_BUG_ON((X86_CR3_PCID_MASK & PAGE_MASK) != 0);
0134
0135     return kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)
0136            ? cr3 & X86_CR3_PCID_MASK
0137            : 0;
0138 }
0139
0140 static inline unsigned long kvm_get_active_pcid(struct kvm_vcpu *vcpu)
0141 {
0142     return kvm_get_pcid(vcpu, kvm_read_cr3(vcpu));
0143 }
0144
0145 static inline void kvm_mmu_load_pgd(struct kvm_vcpu *vcpu)
0146 {
0147     u64 root_hpa = vcpu->arch.mmu->root.hpa;
0148
0149     if (!VALID_PAGE(root_hpa))
0150         return;
0151
0152     static_call(kvm_x86_load_mmu_pgd)(vcpu, root_hpa,
0153                       vcpu->arch.mmu->root_role.level);
0154 }
0155
0156 /*
0157  * Check if a given access (described through the I/D, W/R and U/S bits of a
0158  * page fault error code pfec) causes a permission fault with the given PTE
0159  * access rights (in ACC_* format).
0160  *
0161  * Return zero if the access does not fault; return the page fault error code
0162  * if the access faults.
0163  */
0164 static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
0165                   unsigned pte_access, unsigned pte_pkey,
0166                   u64 access)
0167 {
0168     /* strip nested paging fault error codes */
0169     unsigned int pfec = access;
0170     unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
0171
0172     /*
0173      * For explicit supervisor accesses, SMAP is disabled if EFLAGS.AC = 1.
0174      * For implicit supervisor accesses, SMAP cannot be overridden.
0175      *
0176      * SMAP works on supervisor accesses only, and not_smap can
0177      * be set or not set when user access with neither has any bearing
0178      * on the result.
0179      *
0180      * We put the SMAP checking bit in place of the PFERR_RSVD_MASK bit;
0181      * this bit will always be zero in pfec, but it will be one in index
0182      * if SMAP checks are being disabled.
0183      */
0184     u64 implicit_access = access & PFERR_IMPLICIT_ACCESS;
0185     bool not_smap = ((rflags & X86_EFLAGS_AC) | implicit_access) == X86_EFLAGS_AC;
0186     int index = (pfec + (not_smap << PFERR_RSVD_BIT)) >> 1;
0187     bool fault = (mmu->permissions[index] >> pte_access) & 1;
0188     u32 errcode = PFERR_PRESENT_MASK;
0189
0190     WARN_ON(pfec & (PFERR_PK_MASK | PFERR_RSVD_MASK));
0191     if (unlikely(mmu->pkru_mask)) {
0192         u32 pkru_bits, offset;
0193
0194         /*
0195         * PKRU defines 32 bits, there are 16 domains and 2
0196         * attribute bits per domain in pkru.  pte_pkey is the
0197         * index of the protection domain, so pte_pkey * 2 is
0198         * is the index of the first bit for the domain.
0199         */
0200         pkru_bits = (vcpu->arch.pkru >> (pte_pkey * 2)) & 3;
0201
0202         /* clear present bit, replace PFEC.RSVD with ACC_USER_MASK. */
0203         offset = (pfec & ~1) +
0204             ((pte_access & PT_USER_MASK) << (PFERR_RSVD_BIT - PT_USER_SHIFT));
0205
0206         pkru_bits &= mmu->pkru_mask >> offset;
0207         errcode |= -pkru_bits & PFERR_PK_MASK;
0208         fault |= (pkru_bits != 0);
0209     }
0210
0211     return -(u32)fault & errcode;
0212 }
0213
0214 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end);
0215
0216 int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu);
0217
0218 int kvm_mmu_post_init_vm(struct kvm *kvm);
0219 void kvm_mmu_pre_destroy_vm(struct kvm *kvm);
0220
0221 static inline bool kvm_shadow_root_allocated(struct kvm *kvm)
0222 {
0223     /*
0224      * Read shadow_root_allocated before related pointers. Hence, threads
0225      * reading shadow_root_allocated in any lock context are guaranteed to
0226      * see the pointers. Pairs with smp_store_release in
0227      * mmu_first_shadow_root_alloc.
0228      */
0229     return smp_load_acquire(&kvm->arch.shadow_root_allocated);
0230 }
0231
0232 #ifdef CONFIG_X86_64
0233 static inline bool is_tdp_mmu_enabled(struct kvm *kvm) { return kvm->arch.tdp_mmu_enabled; }
0234 #else
0235 static inline bool is_tdp_mmu_enabled(struct kvm *kvm) { return false; }
0236 #endif
0237
0238 static inline bool kvm_memslots_have_rmaps(struct kvm *kvm)
0239 {
0240     return !is_tdp_mmu_enabled(kvm) || kvm_shadow_root_allocated(kvm);
0241 }
0242
0243 static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level)
0244 {
0245     /* KVM_HPAGE_GFN_SHIFT(PG_LEVEL_4K) must be 0. */
0246     return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
0247         (base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
0248 }
0249
0250 static inline unsigned long
0251 __kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, unsigned long npages,
0252               int level)
0253 {
0254     return gfn_to_index(slot->base_gfn + npages - 1,
0255                 slot->base_gfn, level) + 1;
0256 }
0257
0258 static inline unsigned long
0259 kvm_mmu_slot_lpages(struct kvm_memory_slot *slot, int level)
0260 {
0261     return __kvm_mmu_slot_lpages(slot, slot->npages, level);
0262 }
0263
0264 static inline void kvm_update_page_stats(struct kvm *kvm, int level, int count)
0265 {
0266     atomic64_add(count, &kvm->stat.pages[level - 1]);
0267 }
0268
0269 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
0270                struct x86_exception *exception);
0271
0272 static inline gpa_t kvm_translate_gpa(struct kvm_vcpu *vcpu,
0273                       struct kvm_mmu *mmu,
0274                       gpa_t gpa, u64 access,
0275                       struct x86_exception *exception)
0276 {
0277     if (mmu != &vcpu->arch.nested_mmu)
0278         return gpa;
0279     return translate_nested_gpa(vcpu, gpa, access, exception);
0280 }
0281 #endif