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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __KVM_X86_LAPIC_H
0003 #define __KVM_X86_LAPIC_H
0004 
0005 #include <kvm/iodev.h>
0006 
0007 #include <linux/kvm_host.h>
0008 
0009 #include "hyperv.h"
0010 
0011 #define KVM_APIC_INIT       0
0012 #define KVM_APIC_SIPI       1
0013 
0014 #define APIC_SHORT_MASK         0xc0000
0015 #define APIC_DEST_NOSHORT       0x0
0016 #define APIC_DEST_MASK          0x800
0017 
0018 #define APIC_BUS_CYCLE_NS       1
0019 #define APIC_BUS_FREQUENCY      (1000000000ULL / APIC_BUS_CYCLE_NS)
0020 
0021 #define APIC_BROADCAST          0xFF
0022 #define X2APIC_BROADCAST        0xFFFFFFFFul
0023 
0024 enum lapic_mode {
0025     LAPIC_MODE_DISABLED = 0,
0026     LAPIC_MODE_INVALID = X2APIC_ENABLE,
0027     LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
0028     LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
0029 };
0030 
0031 enum lapic_lvt_entry {
0032     LVT_TIMER,
0033     LVT_THERMAL_MONITOR,
0034     LVT_PERFORMANCE_COUNTER,
0035     LVT_LINT0,
0036     LVT_LINT1,
0037     LVT_ERROR,
0038     LVT_CMCI,
0039 
0040     KVM_APIC_MAX_NR_LVT_ENTRIES,
0041 };
0042 
0043 #define APIC_LVTx(x) ((x) == LVT_CMCI ? APIC_LVTCMCI : APIC_LVTT + 0x10 * (x))
0044 
0045 struct kvm_timer {
0046     struct hrtimer timer;
0047     s64 period;                 /* unit: ns */
0048     ktime_t target_expiration;
0049     u32 timer_mode;
0050     u32 timer_mode_mask;
0051     u64 tscdeadline;
0052     u64 expired_tscdeadline;
0053     u32 timer_advance_ns;
0054     atomic_t pending;           /* accumulated triggered timers */
0055     bool hv_timer_in_use;
0056 };
0057 
0058 struct kvm_lapic {
0059     unsigned long base_address;
0060     struct kvm_io_device dev;
0061     struct kvm_timer lapic_timer;
0062     u32 divide_count;
0063     struct kvm_vcpu *vcpu;
0064     bool apicv_active;
0065     bool sw_enabled;
0066     bool irr_pending;
0067     bool lvt0_in_nmi_mode;
0068     /* Number of bits set in ISR. */
0069     s16 isr_count;
0070     /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
0071     int highest_isr_cache;
0072     /**
0073      * APIC register page.  The layout matches the register layout seen by
0074      * the guest 1:1, because it is accessed by the vmx microcode.
0075      * Note: Only one register, the TPR, is used by the microcode.
0076      */
0077     void *regs;
0078     gpa_t vapic_addr;
0079     struct gfn_to_hva_cache vapic_cache;
0080     unsigned long pending_events;
0081     unsigned int sipi_vector;
0082     int nr_lvt_entries;
0083 };
0084 
0085 struct dest_map;
0086 
0087 int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns);
0088 void kvm_free_lapic(struct kvm_vcpu *vcpu);
0089 
0090 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
0091 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
0092 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
0093 int kvm_apic_accept_events(struct kvm_vcpu *vcpu);
0094 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
0095 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
0096 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
0097 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
0098 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
0099 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
0100 void kvm_recalculate_apic_map(struct kvm *kvm);
0101 void kvm_apic_set_version(struct kvm_vcpu *vcpu);
0102 void kvm_apic_after_set_mcg_cap(struct kvm_vcpu *vcpu);
0103 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
0104                int shorthand, unsigned int dest, int dest_mode);
0105 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2);
0106 void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec);
0107 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
0108 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
0109 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
0110 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
0111              struct dest_map *dest_map);
0112 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
0113 void kvm_apic_update_apicv(struct kvm_vcpu *vcpu);
0114 
0115 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
0116         struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);
0117 void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);
0118 
0119 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
0120 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
0121 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
0122 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
0123 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu);
0124 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
0125 
0126 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
0127 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
0128 
0129 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
0130 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
0131 
0132 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
0133 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
0134 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
0135 
0136 int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data);
0137 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
0138 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
0139 
0140 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
0141 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
0142 
0143 int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
0144 void kvm_lapic_exit(void);
0145 
0146 #define VEC_POS(v) ((v) & (32 - 1))
0147 #define REG_POS(v) (((v) >> 5) << 4)
0148 
0149 static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
0150 {
0151     clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
0152 }
0153 
0154 static inline void kvm_lapic_set_vector(int vec, void *bitmap)
0155 {
0156     set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
0157 }
0158 
0159 static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
0160 {
0161     kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
0162     /*
0163      * irr_pending must be true if any interrupt is pending; set it after
0164      * APIC_IRR to avoid race with apic_clear_irr
0165      */
0166     apic->irr_pending = true;
0167 }
0168 
0169 static inline u32 __kvm_lapic_get_reg(char *regs, int reg_off)
0170 {
0171     return *((u32 *) (regs + reg_off));
0172 }
0173 
0174 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
0175 {
0176     return __kvm_lapic_get_reg(apic->regs, reg_off);
0177 }
0178 
0179 DECLARE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
0180 
0181 static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
0182 {
0183     if (static_branch_unlikely(&kvm_has_noapic_vcpu))
0184         return vcpu->arch.apic;
0185     return true;
0186 }
0187 
0188 extern struct static_key_false_deferred apic_hw_disabled;
0189 
0190 static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
0191 {
0192     if (static_branch_unlikely(&apic_hw_disabled.key))
0193         return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
0194     return MSR_IA32_APICBASE_ENABLE;
0195 }
0196 
0197 extern struct static_key_false_deferred apic_sw_disabled;
0198 
0199 static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
0200 {
0201     if (static_branch_unlikely(&apic_sw_disabled.key))
0202         return apic->sw_enabled;
0203     return true;
0204 }
0205 
0206 static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
0207 {
0208     return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
0209 }
0210 
0211 static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
0212 {
0213     return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
0214 }
0215 
0216 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
0217 {
0218     return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
0219 }
0220 
0221 static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
0222 {
0223     return lapic_in_kernel(vcpu) && vcpu->arch.apic->apicv_active;
0224 }
0225 
0226 static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
0227 {
0228     return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
0229 }
0230 
0231 static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
0232 {
0233     return (irq->delivery_mode == APIC_DM_LOWEST ||
0234             irq->msi_redir_hint);
0235 }
0236 
0237 static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
0238 {
0239     return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
0240 }
0241 
0242 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
0243 
0244 void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);
0245 
0246 void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
0247                   unsigned long *vcpu_bitmap);
0248 
0249 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
0250             struct kvm_vcpu **dest_vcpu);
0251 int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
0252             const unsigned long *bitmap, u32 bitmap_size);
0253 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
0254 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
0255 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
0256 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
0257 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
0258 bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu);
0259 
0260 static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
0261 {
0262     return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
0263 }
0264 
0265 static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
0266 {
0267     return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
0268 }
0269 
0270 #endif
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