x86/kvm/i8259.c

0001 /*
0002  * 8259 interrupt controller emulation
0003  *
0004  * Copyright (c) 2003-2004 Fabrice Bellard
0005  * Copyright (c) 2007 Intel Corporation
0006  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
0007  *
0008  * Permission is hereby granted, free of charge, to any person obtaining a copy
0009  * of this software and associated documentation files (the "Software"), to deal
0010  * in the Software without restriction, including without limitation the rights
0011  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
0012  * copies of the Software, and to permit persons to whom the Software is
0013  * furnished to do so, subject to the following conditions:
0014  *
0015  * The above copyright notice and this permission notice shall be included in
0016  * all copies or substantial portions of the Software.
0017  *
0018  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0019  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0020  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
0021  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0022  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
0023  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
0024  * THE SOFTWARE.
0025  * Authors:
0026  *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
0027  *   Port from Qemu.
0028  */
0029 #include <linux/mm.h>
0030 #include <linux/slab.h>
0031 #include <linux/bitops.h>
0032 #include "irq.h"
0033
0034 #include <linux/kvm_host.h>
0035 #include "trace.h"
0036
0037 #define pr_pic_unimpl(fmt, ...) \
0038     pr_err_ratelimited("kvm: pic: " fmt, ## __VA_ARGS__)
0039
0040 static void pic_irq_request(struct kvm *kvm, int level);
0041
0042 static void pic_lock(struct kvm_pic *s)
0043     __acquires(&s->lock)
0044 {
0045     spin_lock(&s->lock);
0046 }
0047
0048 static void pic_unlock(struct kvm_pic *s)
0049     __releases(&s->lock)
0050 {
0051     bool wakeup = s->wakeup_needed;
0052     struct kvm_vcpu *vcpu;
0053     unsigned long i;
0054
0055     s->wakeup_needed = false;
0056
0057     spin_unlock(&s->lock);
0058
0059     if (wakeup) {
0060         kvm_for_each_vcpu(i, vcpu, s->kvm) {
0061             if (kvm_apic_accept_pic_intr(vcpu)) {
0062                 kvm_make_request(KVM_REQ_EVENT, vcpu);
0063                 kvm_vcpu_kick(vcpu);
0064                 return;
0065             }
0066         }
0067     }
0068 }
0069
0070 static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
0071 {
0072     s->isr &= ~(1 << irq);
0073     if (s != &s->pics_state->pics[0])
0074         irq += 8;
0075     /*
0076      * We are dropping lock while calling ack notifiers since ack
0077      * notifier callbacks for assigned devices call into PIC recursively.
0078      * Other interrupt may be delivered to PIC while lock is dropped but
0079      * it should be safe since PIC state is already updated at this stage.
0080      */
0081     pic_unlock(s->pics_state);
0082     kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
0083     pic_lock(s->pics_state);
0084 }
0085
0086 /*
0087  * set irq level. If an edge is detected, then the IRR is set to 1
0088  */
0089 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
0090 {
0091     int mask, ret = 1;
0092     mask = 1 << irq;
0093     if (s->elcr & mask) /* level triggered */
0094         if (level) {
0095             ret = !(s->irr & mask);
0096             s->irr |= mask;
0097             s->last_irr |= mask;
0098         } else {
0099             s->irr &= ~mask;
0100             s->last_irr &= ~mask;
0101         }
0102     else    /* edge triggered */
0103         if (level) {
0104             if ((s->last_irr & mask) == 0) {
0105                 ret = !(s->irr & mask);
0106                 s->irr |= mask;
0107             }
0108             s->last_irr |= mask;
0109         } else
0110             s->last_irr &= ~mask;
0111
0112     return (s->imr & mask) ? -1 : ret;
0113 }
0114
0115 /*
0116  * return the highest priority found in mask (highest = smallest
0117  * number). Return 8 if no irq
0118  */
0119 static inline int get_priority(struct kvm_kpic_state *s, int mask)
0120 {
0121     int priority;
0122     if (mask == 0)
0123         return 8;
0124     priority = 0;
0125     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
0126         priority++;
0127     return priority;
0128 }
0129
0130 /*
0131  * return the pic wanted interrupt. return -1 if none
0132  */
0133 static int pic_get_irq(struct kvm_kpic_state *s)
0134 {
0135     int mask, cur_priority, priority;
0136
0137     mask = s->irr & ~s->imr;
0138     priority = get_priority(s, mask);
0139     if (priority == 8)
0140         return -1;
0141     /*
0142      * compute current priority. If special fully nested mode on the
0143      * master, the IRQ coming from the slave is not taken into account
0144      * for the priority computation.
0145      */
0146     mask = s->isr;
0147     if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
0148         mask &= ~(1 << 2);
0149     cur_priority = get_priority(s, mask);
0150     if (priority < cur_priority)
0151         /*
0152          * higher priority found: an irq should be generated
0153          */
0154         return (priority + s->priority_add) & 7;
0155     else
0156         return -1;
0157 }
0158
0159 /*
0160  * raise irq to CPU if necessary. must be called every time the active
0161  * irq may change
0162  */
0163 static void pic_update_irq(struct kvm_pic *s)
0164 {
0165     int irq2, irq;
0166
0167     irq2 = pic_get_irq(&s->pics[1]);
0168     if (irq2 >= 0) {
0169         /*
0170          * if irq request by slave pic, signal master PIC
0171          */
0172         pic_set_irq1(&s->pics[0], 2, 1);
0173         pic_set_irq1(&s->pics[0], 2, 0);
0174     }
0175     irq = pic_get_irq(&s->pics[0]);
0176     pic_irq_request(s->kvm, irq >= 0);
0177 }
0178
0179 void kvm_pic_update_irq(struct kvm_pic *s)
0180 {
0181     pic_lock(s);
0182     pic_update_irq(s);
0183     pic_unlock(s);
0184 }
0185
0186 int kvm_pic_set_irq(struct kvm_pic *s, int irq, int irq_source_id, int level)
0187 {
0188     int ret, irq_level;
0189
0190     BUG_ON(irq < 0 || irq >= PIC_NUM_PINS);
0191
0192     pic_lock(s);
0193     irq_level = __kvm_irq_line_state(&s->irq_states[irq],
0194                      irq_source_id, level);
0195     ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, irq_level);
0196     pic_update_irq(s);
0197     trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
0198                   s->pics[irq >> 3].imr, ret == 0);
0199     pic_unlock(s);
0200
0201     return ret;
0202 }
0203
0204 void kvm_pic_clear_all(struct kvm_pic *s, int irq_source_id)
0205 {
0206     int i;
0207
0208     pic_lock(s);
0209     for (i = 0; i < PIC_NUM_PINS; i++)
0210         __clear_bit(irq_source_id, &s->irq_states[i]);
0211     pic_unlock(s);
0212 }
0213
0214 /*
0215  * acknowledge interrupt 'irq'
0216  */
0217 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
0218 {
0219     s->isr |= 1 << irq;
0220     /*
0221      * We don't clear a level sensitive interrupt here
0222      */
0223     if (!(s->elcr & (1 << irq)))
0224         s->irr &= ~(1 << irq);
0225
0226     if (s->auto_eoi) {
0227         if (s->rotate_on_auto_eoi)
0228             s->priority_add = (irq + 1) & 7;
0229         pic_clear_isr(s, irq);
0230     }
0231
0232 }
0233
0234 int kvm_pic_read_irq(struct kvm *kvm)
0235 {
0236     int irq, irq2, intno;
0237     struct kvm_pic *s = kvm->arch.vpic;
0238
0239     s->output = 0;
0240
0241     pic_lock(s);
0242     irq = pic_get_irq(&s->pics[0]);
0243     if (irq >= 0) {
0244         pic_intack(&s->pics[0], irq);
0245         if (irq == 2) {
0246             irq2 = pic_get_irq(&s->pics[1]);
0247             if (irq2 >= 0)
0248                 pic_intack(&s->pics[1], irq2);
0249             else
0250                 /*
0251                  * spurious IRQ on slave controller
0252                  */
0253                 irq2 = 7;
0254             intno = s->pics[1].irq_base + irq2;
0255         } else
0256             intno = s->pics[0].irq_base + irq;
0257     } else {
0258         /*
0259          * spurious IRQ on host controller
0260          */
0261         irq = 7;
0262         intno = s->pics[0].irq_base + irq;
0263     }
0264     pic_update_irq(s);
0265     pic_unlock(s);
0266
0267     return intno;
0268 }
0269
0270 static void kvm_pic_reset(struct kvm_kpic_state *s)
0271 {
0272     int irq;
0273     unsigned long i;
0274     struct kvm_vcpu *vcpu;
0275     u8 edge_irr = s->irr & ~s->elcr;
0276     bool found = false;
0277
0278     s->last_irr = 0;
0279     s->irr &= s->elcr;
0280     s->imr = 0;
0281     s->priority_add = 0;
0282     s->special_mask = 0;
0283     s->read_reg_select = 0;
0284     if (!s->init4) {
0285         s->special_fully_nested_mode = 0;
0286         s->auto_eoi = 0;
0287     }
0288     s->init_state = 1;
0289
0290     kvm_for_each_vcpu(i, vcpu, s->pics_state->kvm)
0291         if (kvm_apic_accept_pic_intr(vcpu)) {
0292             found = true;
0293             break;
0294         }
0295
0296
0297     if (!found)
0298         return;
0299
0300     for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
0301         if (edge_irr & (1 << irq))
0302             pic_clear_isr(s, irq);
0303 }
0304
0305 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
0306 {
0307     struct kvm_kpic_state *s = opaque;
0308     int priority, cmd, irq;
0309
0310     addr &= 1;
0311     if (addr == 0) {
0312         if (val & 0x10) {
0313             s->init4 = val & 1;
0314             if (val & 0x02)
0315                 pr_pic_unimpl("single mode not supported");
0316             if (val & 0x08)
0317                 pr_pic_unimpl(
0318                         "level sensitive irq not supported");
0319             kvm_pic_reset(s);
0320         } else if (val & 0x08) {
0321             if (val & 0x04)
0322                 s->poll = 1;
0323             if (val & 0x02)
0324                 s->read_reg_select = val & 1;
0325             if (val & 0x40)
0326                 s->special_mask = (val >> 5) & 1;
0327         } else {
0328             cmd = val >> 5;
0329             switch (cmd) {
0330             case 0:
0331             case 4:
0332                 s->rotate_on_auto_eoi = cmd >> 2;
0333                 break;
0334             case 1: /* end of interrupt */
0335             case 5:
0336                 priority = get_priority(s, s->isr);
0337                 if (priority != 8) {
0338                     irq = (priority + s->priority_add) & 7;
0339                     if (cmd == 5)
0340                         s->priority_add = (irq + 1) & 7;
0341                     pic_clear_isr(s, irq);
0342                     pic_update_irq(s->pics_state);
0343                 }
0344                 break;
0345             case 3:
0346                 irq = val & 7;
0347                 pic_clear_isr(s, irq);
0348                 pic_update_irq(s->pics_state);
0349                 break;
0350             case 6:
0351                 s->priority_add = (val + 1) & 7;
0352                 pic_update_irq(s->pics_state);
0353                 break;
0354             case 7:
0355                 irq = val & 7;
0356                 s->priority_add = (irq + 1) & 7;
0357                 pic_clear_isr(s, irq);
0358                 pic_update_irq(s->pics_state);
0359                 break;
0360             default:
0361                 break;  /* no operation */
0362             }
0363         }
0364     } else
0365         switch (s->init_state) {
0366         case 0: { /* normal mode */
0367             u8 imr_diff = s->imr ^ val,
0368                 off = (s == &s->pics_state->pics[0]) ? 0 : 8;
0369             s->imr = val;
0370             for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
0371                 if (imr_diff & (1 << irq))
0372                     kvm_fire_mask_notifiers(
0373                         s->pics_state->kvm,
0374                         SELECT_PIC(irq + off),
0375                         irq + off,
0376                         !!(s->imr & (1 << irq)));
0377             pic_update_irq(s->pics_state);
0378             break;
0379         }
0380         case 1:
0381             s->irq_base = val & 0xf8;
0382             s->init_state = 2;
0383             break;
0384         case 2:
0385             if (s->init4)
0386                 s->init_state = 3;
0387             else
0388                 s->init_state = 0;
0389             break;
0390         case 3:
0391             s->special_fully_nested_mode = (val >> 4) & 1;
0392             s->auto_eoi = (val >> 1) & 1;
0393             s->init_state = 0;
0394             break;
0395         }
0396 }
0397
0398 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
0399 {
0400     int ret;
0401
0402     ret = pic_get_irq(s);
0403     if (ret >= 0) {
0404         if (addr1 >> 7) {
0405             s->pics_state->pics[0].isr &= ~(1 << 2);
0406             s->pics_state->pics[0].irr &= ~(1 << 2);
0407         }
0408         s->irr &= ~(1 << ret);
0409         pic_clear_isr(s, ret);
0410         if (addr1 >> 7 || ret != 2)
0411             pic_update_irq(s->pics_state);
0412     } else {
0413         ret = 0x07;
0414         pic_update_irq(s->pics_state);
0415     }
0416
0417     return ret;
0418 }
0419
0420 static u32 pic_ioport_read(void *opaque, u32 addr)
0421 {
0422     struct kvm_kpic_state *s = opaque;
0423     int ret;
0424
0425     if (s->poll) {
0426         ret = pic_poll_read(s, addr);
0427         s->poll = 0;
0428     } else
0429         if ((addr & 1) == 0)
0430             if (s->read_reg_select)
0431                 ret = s->isr;
0432             else
0433                 ret = s->irr;
0434         else
0435             ret = s->imr;
0436     return ret;
0437 }
0438
0439 static void elcr_ioport_write(void *opaque, u32 val)
0440 {
0441     struct kvm_kpic_state *s = opaque;
0442     s->elcr = val & s->elcr_mask;
0443 }
0444
0445 static u32 elcr_ioport_read(void *opaque)
0446 {
0447     struct kvm_kpic_state *s = opaque;
0448     return s->elcr;
0449 }
0450
0451 static int picdev_write(struct kvm_pic *s,
0452              gpa_t addr, int len, const void *val)
0453 {
0454     unsigned char data = *(unsigned char *)val;
0455
0456     if (len != 1) {
0457         pr_pic_unimpl("non byte write\n");
0458         return 0;
0459     }
0460     switch (addr) {
0461     case 0x20:
0462     case 0x21:
0463         pic_lock(s);
0464         pic_ioport_write(&s->pics[0], addr, data);
0465         pic_unlock(s);
0466         break;
0467     case 0xa0:
0468     case 0xa1:
0469         pic_lock(s);
0470         pic_ioport_write(&s->pics[1], addr, data);
0471         pic_unlock(s);
0472         break;
0473     case 0x4d0:
0474     case 0x4d1:
0475         pic_lock(s);
0476         elcr_ioport_write(&s->pics[addr & 1], data);
0477         pic_unlock(s);
0478         break;
0479     default:
0480         return -EOPNOTSUPP;
0481     }
0482     return 0;
0483 }
0484
0485 static int picdev_read(struct kvm_pic *s,
0486                gpa_t addr, int len, void *val)
0487 {
0488     unsigned char *data = (unsigned char *)val;
0489
0490     if (len != 1) {
0491         memset(val, 0, len);
0492         pr_pic_unimpl("non byte read\n");
0493         return 0;
0494     }
0495     switch (addr) {
0496     case 0x20:
0497     case 0x21:
0498     case 0xa0:
0499     case 0xa1:
0500         pic_lock(s);
0501         *data = pic_ioport_read(&s->pics[addr >> 7], addr);
0502         pic_unlock(s);
0503         break;
0504     case 0x4d0:
0505     case 0x4d1:
0506         pic_lock(s);
0507         *data = elcr_ioport_read(&s->pics[addr & 1]);
0508         pic_unlock(s);
0509         break;
0510     default:
0511         return -EOPNOTSUPP;
0512     }
0513     return 0;
0514 }
0515
0516 static int picdev_master_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
0517                    gpa_t addr, int len, const void *val)
0518 {
0519     return picdev_write(container_of(dev, struct kvm_pic, dev_master),
0520                 addr, len, val);
0521 }
0522
0523 static int picdev_master_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
0524                   gpa_t addr, int len, void *val)
0525 {
0526     return picdev_read(container_of(dev, struct kvm_pic, dev_master),
0527                 addr, len, val);
0528 }
0529
0530 static int picdev_slave_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
0531                   gpa_t addr, int len, const void *val)
0532 {
0533     return picdev_write(container_of(dev, struct kvm_pic, dev_slave),
0534                 addr, len, val);
0535 }
0536
0537 static int picdev_slave_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
0538                  gpa_t addr, int len, void *val)
0539 {
0540     return picdev_read(container_of(dev, struct kvm_pic, dev_slave),
0541                 addr, len, val);
0542 }
0543
0544 static int picdev_elcr_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
0545                  gpa_t addr, int len, const void *val)
0546 {
0547     return picdev_write(container_of(dev, struct kvm_pic, dev_elcr),
0548                 addr, len, val);
0549 }
0550
0551 static int picdev_elcr_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
0552                 gpa_t addr, int len, void *val)
0553 {
0554     return picdev_read(container_of(dev, struct kvm_pic, dev_elcr),
0555                 addr, len, val);
0556 }
0557
0558 /*
0559  * callback when PIC0 irq status changed
0560  */
0561 static void pic_irq_request(struct kvm *kvm, int level)
0562 {
0563     struct kvm_pic *s = kvm->arch.vpic;
0564
0565     if (!s->output)
0566         s->wakeup_needed = true;
0567     s->output = level;
0568 }
0569
0570 static const struct kvm_io_device_ops picdev_master_ops = {
0571     .read     = picdev_master_read,
0572     .write    = picdev_master_write,
0573 };
0574
0575 static const struct kvm_io_device_ops picdev_slave_ops = {
0576     .read     = picdev_slave_read,
0577     .write    = picdev_slave_write,
0578 };
0579
0580 static const struct kvm_io_device_ops picdev_elcr_ops = {
0581     .read     = picdev_elcr_read,
0582     .write    = picdev_elcr_write,
0583 };
0584
0585 int kvm_pic_init(struct kvm *kvm)
0586 {
0587     struct kvm_pic *s;
0588     int ret;
0589
0590     s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL_ACCOUNT);
0591     if (!s)
0592         return -ENOMEM;
0593     spin_lock_init(&s->lock);
0594     s->kvm = kvm;
0595     s->pics[0].elcr_mask = 0xf8;
0596     s->pics[1].elcr_mask = 0xde;
0597     s->pics[0].pics_state = s;
0598     s->pics[1].pics_state = s;
0599
0600     /*
0601      * Initialize PIO device
0602      */
0603     kvm_iodevice_init(&s->dev_master, &picdev_master_ops);
0604     kvm_iodevice_init(&s->dev_slave, &picdev_slave_ops);
0605     kvm_iodevice_init(&s->dev_elcr, &picdev_elcr_ops);
0606     mutex_lock(&kvm->slots_lock);
0607     ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x20, 2,
0608                       &s->dev_master);
0609     if (ret < 0)
0610         goto fail_unlock;
0611
0612     ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0xa0, 2, &s->dev_slave);
0613     if (ret < 0)
0614         goto fail_unreg_2;
0615
0616     ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x4d0, 2, &s->dev_elcr);
0617     if (ret < 0)
0618         goto fail_unreg_1;
0619
0620     mutex_unlock(&kvm->slots_lock);
0621
0622     kvm->arch.vpic = s;
0623
0624     return 0;
0625
0626 fail_unreg_1:
0627     kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_slave);
0628
0629 fail_unreg_2:
0630     kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_master);
0631
0632 fail_unlock:
0633     mutex_unlock(&kvm->slots_lock);
0634
0635     kfree(s);
0636
0637     return ret;
0638 }
0639
0640 void kvm_pic_destroy(struct kvm *kvm)
0641 {
0642     struct kvm_pic *vpic = kvm->arch.vpic;
0643
0644     if (!vpic)
0645         return;
0646
0647     mutex_lock(&kvm->slots_lock);
0648     kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_master);
0649     kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_slave);
0650     kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_elcr);
0651     mutex_unlock(&kvm->slots_lock);
0652
0653     kvm->arch.vpic = NULL;
0654     kfree(vpic);
0655 }