x86/kernel/tsc_sync.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * check TSC synchronization.
0004  *
0005  * Copyright (C) 2006, Red Hat, Inc., Ingo Molnar
0006  *
0007  * We check whether all boot CPUs have their TSC's synchronized,
0008  * print a warning if not and turn off the TSC clock-source.
0009  *
0010  * The warp-check is point-to-point between two CPUs, the CPU
0011  * initiating the bootup is the 'source CPU', the freshly booting
0012  * CPU is the 'target CPU'.
0013  *
0014  * Only two CPUs may participate - they can enter in any order.
0015  * ( The serial nature of the boot logic and the CPU hotplug lock
0016  *   protects against more than 2 CPUs entering this code. )
0017  */
0018 #include <linux/topology.h>
0019 #include <linux/spinlock.h>
0020 #include <linux/kernel.h>
0021 #include <linux/smp.h>
0022 #include <linux/nmi.h>
0023 #include <asm/tsc.h>
0024
0025 struct tsc_adjust {
0026     s64     bootval;
0027     s64     adjusted;
0028     unsigned long   nextcheck;
0029     bool        warned;
0030 };
0031
0032 static DEFINE_PER_CPU(struct tsc_adjust, tsc_adjust);
0033 static struct timer_list tsc_sync_check_timer;
0034
0035 /*
0036  * TSC's on different sockets may be reset asynchronously.
0037  * This may cause the TSC ADJUST value on socket 0 to be NOT 0.
0038  */
0039 bool __read_mostly tsc_async_resets;
0040
0041 void mark_tsc_async_resets(char *reason)
0042 {
0043     if (tsc_async_resets)
0044         return;
0045     tsc_async_resets = true;
0046     pr_info("tsc: Marking TSC async resets true due to %s\n", reason);
0047 }
0048
0049 void tsc_verify_tsc_adjust(bool resume)
0050 {
0051     struct tsc_adjust *adj = this_cpu_ptr(&tsc_adjust);
0052     s64 curval;
0053
0054     if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
0055         return;
0056
0057     /* Skip unnecessary error messages if TSC already unstable */
0058     if (check_tsc_unstable())
0059         return;
0060
0061     /* Rate limit the MSR check */
0062     if (!resume && time_before(jiffies, adj->nextcheck))
0063         return;
0064
0065     adj->nextcheck = jiffies + HZ;
0066
0067     rdmsrl(MSR_IA32_TSC_ADJUST, curval);
0068     if (adj->adjusted == curval)
0069         return;
0070
0071     /* Restore the original value */
0072     wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted);
0073
0074     if (!adj->warned || resume) {
0075         pr_warn(FW_BUG "TSC ADJUST differs: CPU%u %lld --> %lld. Restoring\n",
0076             smp_processor_id(), adj->adjusted, curval);
0077         adj->warned = true;
0078     }
0079 }
0080
0081 /*
0082  * Normally the tsc_sync will be checked every time system enters idle
0083  * state, but there is still caveat that a system won't enter idle,
0084  * either because it's too busy or configured purposely to not enter
0085  * idle.
0086  *
0087  * So setup a periodic timer (every 10 minutes) to make sure the check
0088  * is always on.
0089  */
0090
0091 #define SYNC_CHECK_INTERVAL     (HZ * 600)
0092
0093 static void tsc_sync_check_timer_fn(struct timer_list *unused)
0094 {
0095     int next_cpu;
0096
0097     tsc_verify_tsc_adjust(false);
0098
0099     /* Run the check for all onlined CPUs in turn */
0100     next_cpu = cpumask_next(raw_smp_processor_id(), cpu_online_mask);
0101     if (next_cpu >= nr_cpu_ids)
0102         next_cpu = cpumask_first(cpu_online_mask);
0103
0104     tsc_sync_check_timer.expires += SYNC_CHECK_INTERVAL;
0105     add_timer_on(&tsc_sync_check_timer, next_cpu);
0106 }
0107
0108 static int __init start_sync_check_timer(void)
0109 {
0110     if (!cpu_feature_enabled(X86_FEATURE_TSC_ADJUST) || tsc_clocksource_reliable)
0111         return 0;
0112
0113     timer_setup(&tsc_sync_check_timer, tsc_sync_check_timer_fn, 0);
0114     tsc_sync_check_timer.expires = jiffies + SYNC_CHECK_INTERVAL;
0115     add_timer(&tsc_sync_check_timer);
0116
0117     return 0;
0118 }
0119 late_initcall(start_sync_check_timer);
0120
0121 static void tsc_sanitize_first_cpu(struct tsc_adjust *cur, s64 bootval,
0122                    unsigned int cpu, bool bootcpu)
0123 {
0124     /*
0125      * First online CPU in a package stores the boot value in the
0126      * adjustment value. This value might change later via the sync
0127      * mechanism. If that fails we still can yell about boot values not
0128      * being consistent.
0129      *
0130      * On the boot cpu we just force set the ADJUST value to 0 if it's
0131      * non zero. We don't do that on non boot cpus because physical
0132      * hotplug should have set the ADJUST register to a value > 0 so
0133      * the TSC is in sync with the already running cpus.
0134      *
0135      * Also don't force the ADJUST value to zero if that is a valid value
0136      * for socket 0 as determined by the system arch.  This is required
0137      * when multiple sockets are reset asynchronously with each other
0138      * and socket 0 may not have an TSC ADJUST value of 0.
0139      */
0140     if (bootcpu && bootval != 0) {
0141         if (likely(!tsc_async_resets)) {
0142             pr_warn(FW_BUG "TSC ADJUST: CPU%u: %lld force to 0\n",
0143                 cpu, bootval);
0144             wrmsrl(MSR_IA32_TSC_ADJUST, 0);
0145             bootval = 0;
0146         } else {
0147             pr_info("TSC ADJUST: CPU%u: %lld NOT forced to 0\n",
0148                 cpu, bootval);
0149         }
0150     }
0151     cur->adjusted = bootval;
0152 }
0153
0154 #ifndef CONFIG_SMP
0155 bool __init tsc_store_and_check_tsc_adjust(bool bootcpu)
0156 {
0157     struct tsc_adjust *cur = this_cpu_ptr(&tsc_adjust);
0158     s64 bootval;
0159
0160     if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
0161         return false;
0162
0163     /* Skip unnecessary error messages if TSC already unstable */
0164     if (check_tsc_unstable())
0165         return false;
0166
0167     rdmsrl(MSR_IA32_TSC_ADJUST, bootval);
0168     cur->bootval = bootval;
0169     cur->nextcheck = jiffies + HZ;
0170     tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(), bootcpu);
0171     return false;
0172 }
0173
0174 #else /* !CONFIG_SMP */
0175
0176 /*
0177  * Store and check the TSC ADJUST MSR if available
0178  */
0179 bool tsc_store_and_check_tsc_adjust(bool bootcpu)
0180 {
0181     struct tsc_adjust *ref, *cur = this_cpu_ptr(&tsc_adjust);
0182     unsigned int refcpu, cpu = smp_processor_id();
0183     struct cpumask *mask;
0184     s64 bootval;
0185
0186     if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
0187         return false;
0188
0189     rdmsrl(MSR_IA32_TSC_ADJUST, bootval);
0190     cur->bootval = bootval;
0191     cur->nextcheck = jiffies + HZ;
0192     cur->warned = false;
0193
0194     /*
0195      * If a non-zero TSC value for socket 0 may be valid then the default
0196      * adjusted value cannot assumed to be zero either.
0197      */
0198     if (tsc_async_resets)
0199         cur->adjusted = bootval;
0200
0201     /*
0202      * Check whether this CPU is the first in a package to come up. In
0203      * this case do not check the boot value against another package
0204      * because the new package might have been physically hotplugged,
0205      * where TSC_ADJUST is expected to be different. When called on the
0206      * boot CPU topology_core_cpumask() might not be available yet.
0207      */
0208     mask = topology_core_cpumask(cpu);
0209     refcpu = mask ? cpumask_any_but(mask, cpu) : nr_cpu_ids;
0210
0211     if (refcpu >= nr_cpu_ids) {
0212         tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(),
0213                        bootcpu);
0214         return false;
0215     }
0216
0217     ref = per_cpu_ptr(&tsc_adjust, refcpu);
0218     /*
0219      * Compare the boot value and complain if it differs in the
0220      * package.
0221      */
0222     if (bootval != ref->bootval)
0223         printk_once(FW_BUG "TSC ADJUST differs within socket(s), fixing all errors\n");
0224
0225     /*
0226      * The TSC_ADJUST values in a package must be the same. If the boot
0227      * value on this newly upcoming CPU differs from the adjustment
0228      * value of the already online CPU in this package, set it to that
0229      * adjusted value.
0230      */
0231     if (bootval != ref->adjusted) {
0232         cur->adjusted = ref->adjusted;
0233         wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted);
0234     }
0235     /*
0236      * We have the TSCs forced to be in sync on this package. Skip sync
0237      * test:
0238      */
0239     return true;
0240 }
0241
0242 /*
0243  * Entry/exit counters that make sure that both CPUs
0244  * run the measurement code at once:
0245  */
0246 static atomic_t start_count;
0247 static atomic_t stop_count;
0248 static atomic_t skip_test;
0249 static atomic_t test_runs;
0250
0251 /*
0252  * We use a raw spinlock in this exceptional case, because
0253  * we want to have the fastest, inlined, non-debug version
0254  * of a critical section, to be able to prove TSC time-warps:
0255  */
0256 static arch_spinlock_t sync_lock = __ARCH_SPIN_LOCK_UNLOCKED;
0257
0258 static cycles_t last_tsc;
0259 static cycles_t max_warp;
0260 static int nr_warps;
0261 static int random_warps;
0262
0263 /*
0264  * TSC-warp measurement loop running on both CPUs.  This is not called
0265  * if there is no TSC.
0266  */
0267 static cycles_t check_tsc_warp(unsigned int timeout)
0268 {
0269     cycles_t start, now, prev, end, cur_max_warp = 0;
0270     int i, cur_warps = 0;
0271
0272     start = rdtsc_ordered();
0273     /*
0274      * The measurement runs for 'timeout' msecs:
0275      */
0276     end = start + (cycles_t) tsc_khz * timeout;
0277
0278     for (i = 0; ; i++) {
0279         /*
0280          * We take the global lock, measure TSC, save the
0281          * previous TSC that was measured (possibly on
0282          * another CPU) and update the previous TSC timestamp.
0283          */
0284         arch_spin_lock(&sync_lock);
0285         prev = last_tsc;
0286         now = rdtsc_ordered();
0287         last_tsc = now;
0288         arch_spin_unlock(&sync_lock);
0289
0290         /*
0291          * Be nice every now and then (and also check whether
0292          * measurement is done [we also insert a 10 million
0293          * loops safety exit, so we dont lock up in case the
0294          * TSC readout is totally broken]):
0295          */
0296         if (unlikely(!(i & 7))) {
0297             if (now > end || i > 10000000)
0298                 break;
0299             cpu_relax();
0300             touch_nmi_watchdog();
0301         }
0302         /*
0303          * Outside the critical section we can now see whether
0304          * we saw a time-warp of the TSC going backwards:
0305          */
0306         if (unlikely(prev > now)) {
0307             arch_spin_lock(&sync_lock);
0308             max_warp = max(max_warp, prev - now);
0309             cur_max_warp = max_warp;
0310             /*
0311              * Check whether this bounces back and forth. Only
0312              * one CPU should observe time going backwards.
0313              */
0314             if (cur_warps != nr_warps)
0315                 random_warps++;
0316             nr_warps++;
0317             cur_warps = nr_warps;
0318             arch_spin_unlock(&sync_lock);
0319         }
0320     }
0321     WARN(!(now-start),
0322         "Warning: zero tsc calibration delta: %Ld [max: %Ld]\n",
0323             now-start, end-start);
0324     return cur_max_warp;
0325 }
0326
0327 /*
0328  * If the target CPU coming online doesn't have any of its core-siblings
0329  * online, a timeout of 20msec will be used for the TSC-warp measurement
0330  * loop. Otherwise a smaller timeout of 2msec will be used, as we have some
0331  * information about this socket already (and this information grows as we
0332  * have more and more logical-siblings in that socket).
0333  *
0334  * Ideally we should be able to skip the TSC sync check on the other
0335  * core-siblings, if the first logical CPU in a socket passed the sync test.
0336  * But as the TSC is per-logical CPU and can potentially be modified wrongly
0337  * by the bios, TSC sync test for smaller duration should be able
0338  * to catch such errors. Also this will catch the condition where all the
0339  * cores in the socket don't get reset at the same time.
0340  */
0341 static inline unsigned int loop_timeout(int cpu)
0342 {
0343     return (cpumask_weight(topology_core_cpumask(cpu)) > 1) ? 2 : 20;
0344 }
0345
0346 /*
0347  * Source CPU calls into this - it waits for the freshly booted
0348  * target CPU to arrive and then starts the measurement:
0349  */
0350 void check_tsc_sync_source(int cpu)
0351 {
0352     int cpus = 2;
0353
0354     /*
0355      * No need to check if we already know that the TSC is not
0356      * synchronized or if we have no TSC.
0357      */
0358     if (unsynchronized_tsc())
0359         return;
0360
0361     /*
0362      * Set the maximum number of test runs to
0363      *  1 if the CPU does not provide the TSC_ADJUST MSR
0364      *  3 if the MSR is available, so the target can try to adjust
0365      */
0366     if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST))
0367         atomic_set(&test_runs, 1);
0368     else
0369         atomic_set(&test_runs, 3);
0370 retry:
0371     /*
0372      * Wait for the target to start or to skip the test:
0373      */
0374     while (atomic_read(&start_count) != cpus - 1) {
0375         if (atomic_read(&skip_test) > 0) {
0376             atomic_set(&skip_test, 0);
0377             return;
0378         }
0379         cpu_relax();
0380     }
0381
0382     /*
0383      * Trigger the target to continue into the measurement too:
0384      */
0385     atomic_inc(&start_count);
0386
0387     check_tsc_warp(loop_timeout(cpu));
0388
0389     while (atomic_read(&stop_count) != cpus-1)
0390         cpu_relax();
0391
0392     /*
0393      * If the test was successful set the number of runs to zero and
0394      * stop. If not, decrement the number of runs an check if we can
0395      * retry. In case of random warps no retry is attempted.
0396      */
0397     if (!nr_warps) {
0398         atomic_set(&test_runs, 0);
0399
0400         pr_debug("TSC synchronization [CPU#%d -> CPU#%d]: passed\n",
0401             smp_processor_id(), cpu);
0402
0403     } else if (atomic_dec_and_test(&test_runs) || random_warps) {
0404         /* Force it to 0 if random warps brought us here */
0405         atomic_set(&test_runs, 0);
0406
0407         pr_warn("TSC synchronization [CPU#%d -> CPU#%d]:\n",
0408             smp_processor_id(), cpu);
0409         pr_warn("Measured %Ld cycles TSC warp between CPUs, "
0410             "turning off TSC clock.\n", max_warp);
0411         if (random_warps)
0412             pr_warn("TSC warped randomly between CPUs\n");
0413         mark_tsc_unstable("check_tsc_sync_source failed");
0414     }
0415
0416     /*
0417      * Reset it - just in case we boot another CPU later:
0418      */
0419     atomic_set(&start_count, 0);
0420     random_warps = 0;
0421     nr_warps = 0;
0422     max_warp = 0;
0423     last_tsc = 0;
0424
0425     /*
0426      * Let the target continue with the bootup:
0427      */
0428     atomic_inc(&stop_count);
0429
0430     /*
0431      * Retry, if there is a chance to do so.
0432      */
0433     if (atomic_read(&test_runs) > 0)
0434         goto retry;
0435 }
0436
0437 /*
0438  * Freshly booted CPUs call into this:
0439  */
0440 void check_tsc_sync_target(void)
0441 {
0442     struct tsc_adjust *cur = this_cpu_ptr(&tsc_adjust);
0443     unsigned int cpu = smp_processor_id();
0444     cycles_t cur_max_warp, gbl_max_warp;
0445     int cpus = 2;
0446
0447     /* Also aborts if there is no TSC. */
0448     if (unsynchronized_tsc())
0449         return;
0450
0451     /*
0452      * Store, verify and sanitize the TSC adjust register. If
0453      * successful skip the test.
0454      *
0455      * The test is also skipped when the TSC is marked reliable. This
0456      * is true for SoCs which have no fallback clocksource. On these
0457      * SoCs the TSC is frequency synchronized, but still the TSC ADJUST
0458      * register might have been wreckaged by the BIOS..
0459      */
0460     if (tsc_store_and_check_tsc_adjust(false) || tsc_clocksource_reliable) {
0461         atomic_inc(&skip_test);
0462         return;
0463     }
0464
0465 retry:
0466     /*
0467      * Register this CPU's participation and wait for the
0468      * source CPU to start the measurement:
0469      */
0470     atomic_inc(&start_count);
0471     while (atomic_read(&start_count) != cpus)
0472         cpu_relax();
0473
0474     cur_max_warp = check_tsc_warp(loop_timeout(cpu));
0475
0476     /*
0477      * Store the maximum observed warp value for a potential retry:
0478      */
0479     gbl_max_warp = max_warp;
0480
0481     /*
0482      * Ok, we are done:
0483      */
0484     atomic_inc(&stop_count);
0485
0486     /*
0487      * Wait for the source CPU to print stuff:
0488      */
0489     while (atomic_read(&stop_count) != cpus)
0490         cpu_relax();
0491
0492     /*
0493      * Reset it for the next sync test:
0494      */
0495     atomic_set(&stop_count, 0);
0496
0497     /*
0498      * Check the number of remaining test runs. If not zero, the test
0499      * failed and a retry with adjusted TSC is possible. If zero the
0500      * test was either successful or failed terminally.
0501      */
0502     if (!atomic_read(&test_runs))
0503         return;
0504
0505     /*
0506      * If the warp value of this CPU is 0, then the other CPU
0507      * observed time going backwards so this TSC was ahead and
0508      * needs to move backwards.
0509      */
0510     if (!cur_max_warp)
0511         cur_max_warp = -gbl_max_warp;
0512
0513     /*
0514      * Add the result to the previous adjustment value.
0515      *
0516      * The adjustment value is slightly off by the overhead of the
0517      * sync mechanism (observed values are ~200 TSC cycles), but this
0518      * really depends on CPU, node distance and frequency. So
0519      * compensating for this is hard to get right. Experiments show
0520      * that the warp is not longer detectable when the observed warp
0521      * value is used. In the worst case the adjustment needs to go
0522      * through a 3rd run for fine tuning.
0523      */
0524     cur->adjusted += cur_max_warp;
0525
0526     pr_warn("TSC ADJUST compensate: CPU%u observed %lld warp. Adjust: %lld\n",
0527         cpu, cur_max_warp, cur->adjusted);
0528
0529     wrmsrl(MSR_IA32_TSC_ADJUST, cur->adjusted);
0530     goto retry;
0531
0532 }
0533
0534 #endif /* CONFIG_SMP */